Added: Xeon Phi Manager
[barrelfish] / devices / xeon_phi / xeon_phi_boot.dev
1 /*
2  * Copyright (c) 2014 ETH Zurich. All rights reserved.
3  *
4  * This file is distributed under the terms in the attached LICENSE file.
5  * If you do not find this file, copies can be found by writing to:
6  * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
7  */
8
9 /*
10  * xeon_phi_boot.dev
11  *
12  * description: register definitions for the Xeon Phi Boot Time Registers
13  */
14
15 device xeon_phi_boot lsbfirst ( addr sbox_base, addr dbox_base ) "Intel Xeon Phi Boot Registers" {
16
17     /*
18      * Protection Level: Ring 0
19      * Visibility: Host / Coprocessor
20      * Reset Dmain: CSR_RESET, HOT_RESET
21      * Register Access: TRM
22      */
23
24      constants offset width(32) "" {
25          address_shift=12;
26          address_mask=0xfffff000;
27      };
28
29     /*
30      * alias for scratch register 2
31      */
32     register download rw addr(sbox_base, 0xAB28) {
33         status       1 "Download status bit";
34         apicid       9 "APIC ID to send the boot interrupt";
35         _            2 "unused";
36         offset      20 "Load offset";         
37     };
38     
39     /*
40      * alias for scratch register 3
41      */
42     register res_size rw addr(sbox_base, 0xAB2C) {
43         os 32 "Reserved size";
44     };
45     
46     /*
47      * alias for scratch register 5
48      */
49     register os_size rw addr(sbox_base, 0xAB34) {
50         size 32 "Size of the loaded image";
51     };
52     
53     constants mem width(2) "" {
54           mem_all    = 0x0;
55           mem_half   = 0x1;
56           mem_third  = 0x2;
57           mem_fourth = 0x3;
58     };
59     
60     register meminfo rw addr(sbox_base, 0xAB20) {
61           test_disable  1 "Memtest disable";
62           usage         2 "Memory usage";
63           size_kb      29 "Memory size in KB";
64     };
65     
66     register reset rw addr(sbox_base, 0x4010) {
67         reset  1 "Perform device rest";
68         _     31; 
69     };
70     
71     /*
72      * Note: The post codes are represented as a two byte ASCII values  
73      */
74     constants postcodes width(16) "The Xeon Phi Post codes" {
75         postcode_lidt           = 0x3031 "01 LIDT";
76         postcode_sboxinit       = 0x3032 "02 SBOX initialization";
77         postcode_gddrtop        = 0x3033 "03 Set GDDR Top";
78         postcode_memtest        = 0x3034 "04 Begin memory test";
79         postcode_e820           = 0x3035 "05 Program E820 table";
80         postcode_dbox           = 0x3036 "06 Initialize DBOX";
81         postcode_cache          = 0x3039 "09 Enable Cache";    
82         postcode_initap         = 0x3062 "0b Pass initialization params to APs";
83         postcode_code           = 0x3063 "0c Cache C code";
84         postcode_mp             = 0x3045 "0E Program MP table";
85         postcode_apwkup         = 0x3046 "0F Wake up APs";
86         postcode_apboot         = 0x3130 "10 Wait for APs to boot";
87         postcode_sig            = 0x3131 "11 Signal host to download OS";
88         postcode_ready          = 0x3132 "12 Wait for download READY";
89         postcode_boot           = 0x3133 "13 Signal to boot received";
90         postcode_pinfo          = 0x3135 "15 Report platform information";
91         postcode_ptable         = 0x3137 "17 Page table setup";
92         postcode_memtrain       = 0x3330 "30 Begin memory training";
93         postcode_gddrtrain      = 0x3331 "31 GDDR Training to query memory modules";
94         postcode_findgddrtrain  = 0x3332 "32 Find GDDR training parameters in flash";
95         postcode_mmiotrain      = 0x3333 "33 MMIO training";
96         postcode_rcomptrain     = 0x3334 "34 RCOMP training";
97         postcode_dcctrain       = 0x3335 "35 DCC disable training";
98         postcode_hcktrain       = 0x3336 "36 HCK training";
99         postcode_ucodetrain     = 0x3337 "37 UCode Training";
100         postcode_vendortrain    = 0x3338 "38 Vendor specific training";
101         postcode_addrtrain      = 0x3339 "39 GDDR address training";
102         postcode_gddrident      = 0x3341 "3A GDDR memory module identification";
103         postcode_wcktrain       = 0x3362 "3b GDDR WCK training";
104         postcode_cdrdtrain      = 0x3343 "3C GDDR read training with CDR enabled";
105         postcode_cdretrain      = 0x3364 "3d GDDR Read Training with CDR disabled";
106         postcode_wrtrain        = 0x3345 "3E GDDR Write Training";
107         postcode_fintrain       = 0x3346 "3F Finalize GDDR Training";
108         postcode_osauth         = 0x3430 "40 Begin Coprocessor OS authentification";
109         postcode_loading0       = 0x3530 "50 Coprocessor OS Loading 0";
110         postcode_loading1       = 0x3531 "51 Coprocessor OS Loading 1";
111         postcode_loading2       = 0x3532 "52 Coprocessor OS Loading 2";
112         postcode_loading3       = 0x3533 "53 Coprocessor OS Loading 3";
113         postcode_loading4       = 0x3534 "54 Coprocessor OS Loading 4";
114         postcode_loading5       = 0x3535 "55 Coprocessor OS Loading 5";
115         postcode_loading6       = 0x3536 "56 Coprocessor OS Loading 6";
116         postcode_loading7       = 0x3537 "57 Coprocessor OS Loading 7";
117         postcode_loading8       = 0x3538 "58 Coprocessor OS Loading 8";
118         postcode_loading9       = 0x3539 "59 Coprocessor OS Loading 9";
119         postcode_loadingb       = 0x3541 "5A Coprocessor OS Loading A";
120         postcode_loadinga       = 0x3542 "5B Coprocessor OS Loading B";
121         postcode_loadingc       = 0x3543 "5C Coprocessor OS Loading C";
122         postcode_loadingd       = 0x3544 "5D Coprocessor OS Loading D";
123         postcode_loadinge       = 0x3545 "5E Coprocessor OS Loading E";
124         postcode_loadingf       = 0x3546 "5F Coprocessor OS Loading F";
125         postcode_gp             = 0x3650 "6P Int 13 - General Protection Fault";
126         postcode_tss            = 0x3735 "75 Int 10 - Invalid TSS";
127         postcode_fpu            = 0x3837 "87 Int 16 - x87 FPU Error";
128         postcode_algin          = 0x4143 "AC INT 17 - Alignment Check";
129         postcode_bp             = 0x6250 "bP INT 3 - Break Point";
130         postcode_bound          = 0x6272 "br INT 5 - BOUND Range Exceeded";
131         postcode_mc             = 0x4343 "CC INT 18 - Machine Check";
132         postcode_seg            = 0x636F "co INT 9 - Coprocessor Segmenet Overrun";
133         postcode_dbg            = 0x6462 "db INT 1 - Debug";
134         postcode_div            = 0x6445 "dE INT 0 - Divide Error";
135         postcode_df             = 0x6446 "dF INT 8 - Double Fault";
136         postcode_memf           = 0x4545 "EE Memory Test Failed";
137         postcode_pnf            = 0x4630 "F0 GDDR Parameters not found";
138         postcode_pllf           = 0x4631 "F1 GBOX PLL lock failure";
139         postcode_memtf          = 0x4632 "F2 GDDR failed memory training";
140         postcode_memqf          = 0x4633 "F3 GDDR memory module query failed";
141         postcode_mempf          = 0x4634 "F4 Memory preservation failure";
142         postcode_sf             = 0x4635 "F5 INT 12 - Stack Fault";
143         postcode_done           = 0x4646 "FF - Bootstrap finished execution";
144         postcode_ld             = 0x4C64 "Ld - Locking down hardware access";
145         postcode_authf          = 0x6E41 "nA - OS Image failed Authentification";
146         postcode_dna            = 0x6E64 "nd INT 7 - Device not Available";
147         postcode_nmi            = 0x6E6F "no INT 2 - Non-maskable Interrupt";
148         postcode_snp            = 0x6E50 "nP INT 11 - Segment Not Present";
149         postcode_of             = 0x6F46 "oF INT 4 - Overflow";
150         postcode_pf             = 0x5046 "PF INT 14 - Pagefault";
151         postcode_rs             = 0x7235 "r5 INT 15 - Reserved";
152         postcode_iop            = 0x7564 "ud INT 6 - Invalid OP code";
153     };
154     
155     constants postcodes_special width(32) "The Xeon Phi Post codes" {
156         postcode_invalid = 0x0;
157         postcode_fatal   = 0xffffffff;
158     };
159     
160     
161     register postcode rw addr(dbox_base, 0x242c) {
162         code  16 type(postcodes);
163         _     16;
164     };
165     
166     register postcode_raw rw also addr(dbox_base, 0x242c) {
167         code0  8;
168         code1  8;
169         _     16;
170     };
171
172 };
173