Sockeye: Start reimplementing net builder on top of instantiator
[barrelfish] / socs / omap44xx.soc
1 /*
2  * Copyright (c) 2017, ETH Zurich. All rights reserved.
3  *
4  * This file is distributed under the terms in the attached LICENSE file.
5  * If you do not find this file, copies can be found by writing to:
6  * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich.
7  * Attn: Systems Group.
8  */
9
10 /**
11  * Physical memory map for TI OMAP4460 SoC
12  *
13  * This is derived from:
14  * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
15  * Manual Version Q
16  *
17  */
18
19 import omap44xx/cortexA9-subsystem
20
21 /*
22  * 2.2 L3 Memory space mapping
23  */
24 /* Q0 */
25 SRAM is memory accept [0x0/30]
26
27 /* Q1 */
28 L3_OCM_RAM is memory accept [0x0-0xDFFF]
29
30 /* Q2 */
31 SDRAM is memory accept [0x0/30]
32
33 /* TODO: Tiler view */
34
35 L3 is map [
36         0x00000000/30 to SRAM
37         /* 0x40000000-0x4002FFFF reserved */
38         /* 0x40030000-0x4003BFFF Cortex-A9 ROM */
39         /* 0x4003C000-0x400FFFFF reserved */ //TRM: 0x40034000-0x400FFFFF?
40         /* 0x40100000/20 L4_ABE private access for Cortex A9
41         /* 0x40200000/20 reserved */
42         0x40300000-0x4030DFFF to L3_OCM_RAM
43         /* 0x4030E000-0x43FFFFFF reserved */
44         0x44000000/26 to L3_config
45         0x48000000/24 to L4_PER at 0x48000000
46         0x49000000/24 to L4_ABE
47         0x4A000000/24 to L4_CFG at 0x4A000000
48         /* 0x4B000000/24 reserved */
49         0x4C000000/24 to EMIF1
50         0x4D000000/24 to EMIF2
51         0x4E000000/25 to DMM
52         0x50000000/25 to GPMC
53         0x52000000/25 to ISS
54         0x54000000/24 to L3_EMU at 0x54000000
55         0x55000000/24 to CORTEXM3
56         0x56000000/25 to SGX
57         0x58000000/24 to Display
58         /* 0x59000000/24 reserved */
59         // 0x5A000000/24 IVA-HD configuration
60         // 0x5B000000/24 IVA-HD SL2
61         /* 0x5C000000/26 reserved */
62         // 0x60000000/28 Tiler address mapping
63         0x80000000/30 to SDRAM
64       ]
65
66 /*
67  * 2.2.1 L3_EMU Memory Space Mapping
68  */
69 L3_EMU is map [
70             0x54000000/20 to MIPI_STM_0
71             0x54100000/18 to MIPI_STM_1
72             0x54140000/13 to A9_CPU0_debug_PMU
73             0x54142000/13 to A9_CPU1_debug_PMU
74             /* 0x54144000/14 reserved */
75             0x54148000/12 to CTI0
76             0x54149000/12 to CTI1
77             /* 0x5414A000/13 reserved */
78             0x5414C000/12 to PTM0
79             0x5414D000/12 to PTM1
80             /* 0x5414E000/13 reserved */
81             0x54158000/12 to A9_CS-TF
82             0x54159000/12 to DAP_PC
83             /* 0x5415A000-0x5415EFFF reserved */
84             0x5416F000/12 to APB
85             0x54160000/12 to DRM
86             0x54161000/12 to MIPI_STM
87             0x54162000/12 to CS-ETB
88             0x54163000/12 to CS-TPIU
89             0x54164000/12 to CS-TF
90             /* 0x54165000/13 reserved */
91             // 0x54167000/12 Technology specific registers
92             /* 0x54168000-0x5417FFFF reserved */
93             // 0x54180000/12 Technology specific registers
94             /* 0x54181000-0x541FFFFF reserved */
95             // XXX: What about 0x54200000-0x54FFFFFF?
96           ]
97
98 /*
99  * 2.3.1 L4_CFG Memory Space Mapping
100  */
101 SAR_ROM is device accept [0x0/13]
102
103 L4_CFG is map [
104             0x4A000000/11 to CFG_AP
105             0x4A000800/11 to CFG_LA
106             0x4A001000/12 to CFG_IP0
107             0x4A002000/12 to SYSCTRL_GENERAL_CORE
108             // 0x4A003000/12 L4 interconnect
109             0x4A004000/12 to CM1
110             // 0x4A005000/12 L4 interconnect
111             /* 0x4A006000/13 reserved
112             0x4A008000/13 to CM2
113             // 0x4A00A000/12 L4 interconnect
114             /* 0x4A00B000-0x4A055FFF reserved */
115             0x4A056000/12 to SDMA
116             // 0x4A057000/12 L4 interconnect
117             0x4A058000/12 to HSI
118             // 0x4A05C000/12 L4 interconnect
119             /* 0x4A05D000/12 reserved */
120             0x4A05E000/13 to SAR_ROM
121             // 0x4A060000/12 L4 interconnect
122             /* 0x4A061000/12 reserved */
123             0x4A062000/12 to HSUSBTLL
124             // 0x4A063000/12 L4 interconnect
125             0x4A064000/12 to HSUSBHOST
126             // 0x4A065000/12 L4 interconnect
127             0x4A066000/12 to DSP at 0x01C20000
128             // 0x4A067000/12 L4 interconnect
129             /* 0x4A068000-0x4A0A8FFF reserved */
130             0x4A0A9000/12 to FSUSBHOST
131             // 0x4A0AA000/12 L4 interconnect
132             0x4A0AB000/12 to HSUSBOTG
133             // 0x4A0AC000/12 L4 interconnect
134             0x4A0AD000/12 to USBPHY
135             // 0x4A0AE000/12 L4 interconnect
136             /* 0x4A0AF000-0x4A0D8FFF reserved */
137             0x4A0D9000/12 to SR_MPU
138             // 0x4A0DA000/12 L4 interconnect
139             0x4A0DB000/12 to SR_IVA
140             // 0x4A0DC000/12 L4 interconnect
141             0x4A0DD000/12 to SR_CORE
142             // 0x4A0DE000/12 L4 interconnect
143             /* 0x4A0DF000-0x4A0F3FFF reserved */
144             0x4A0F4000/12 to System_Mailbox
145             // 0x4A0F5000/12 L4 interconnect
146             0x4A0F6000/12 to Spinlock
147             // 0x4A0F7000/12 L4 interconnect
148             /* 0x4A0F8000/15 reserved */
149             0x4A100000/12 to SYSCTRL_PADCONF_CORE
150             // 0x4A101000/12 L4 interconnect
151             0x4A102000/12 to OCP-WP
152             // 0x4A103000/12 L4 interconnect
153             /* 0x4A104000-0x4A109FFF reserved */
154             0x4A10A000/12 to FDIF
155             // 0x4A10B000/12 L4 interconnect
156             /* 0x4A10C000-0x4A203FFF reserved */
157             0x4A204000/12 to C2C_INIT_firewall
158             // 0x4A205000/12 L4 interconnect
159             0x4A206000/12 to C2C_TARGET_firewall
160             // 0x4A207000/12 L4 interconnect
161             /* 0x4A208000/13 reserved */
162             0x4A20A000/12 to MA_firewall
163             // 0x4A20B000/12 L4 interconnect
164             0x4A20C000/12 to EMIF_firewall
165             // 0x4A20D000/12 L4 interconnect
166             /* 0x4A20E000/13 reserved */
167             0x4A210000/12 to GPMC_firewall
168             // 0x4A211000/12 L4 interconnect
169             0x4A212000/12 to L3_OCMC_RAM_firewall
170             // 0x4A213000/12 L4 interconnect
171             0x4A214000/12 to SGX_firewall
172             // 0x4A215000/12 L4 interconnect
173             0x4A216000/12 to ISS_firewall
174             // 0x4A217000/12 L4 interconnect
175             0x4A218000/12 to M3_firewall
176             // 0x4A219000/12 L4 interconnect
177             /* 0x4A21A000/13 reserved */
178             0x4A21C000/12 to DSS_firewall
179             // 0x4A21D000/12 L4 interconnect
180             0x4A21E000/12 to SL2_firewall
181             // 0x4A21F000/12 L4 interconnect
182             0x4A220000/12 to IVA-HD_firewall
183             // 0x4A221000/12 L4 interconnect
184             /* 0x4A222000/14 reserved */
185             0x4A226000/12 to L4-EMU_firewall
186             // 0x4A227000/12 L4 interconnect
187             0x4A228000/12 to L4-ABE_firewall
188             // 0x4A229000/12 L4 interconnect
189             /* 0x4A22A000-0x4A2FFFFF reserved */
190             0x4A300000/18 to L4_WKUP at 0x4A300000
191             // 0x4A340000/12 L4 interconnect
192             /* 0x4A341000-0x4AFFFFFF reserved */
193           ]
194
195
196 /*
197  * 2.3.2 L4_WKUP Memory Space Mapping
198  */
199 SAR_RAM1 is memory accept [0x0/12]
200 SAR_RAM2 is memory accept [0x0/10]
201 SAR_RAM3 is memory accept [0x0/11]
202 SAR_RAM4 is memory accept [0x0/10]
203
204 L4_WKUP is map [
205                 0x4A300000/11 to WKUP_AP
206                 0x4A300800/11 to WKUP_LA
207                 0x4A301000/12 to WKUP_IP0
208                 /* 0x4A302000/13 reserved */
209                 0x4A304000/12 to S32KTIMER
210                 // 0x4A305000/12 L4 interconnect
211                 0x4A306000/13 to PRM
212                 // 0x4A308000/12 L4 interconnect
213                 /* 0x4A309000/12 reserved */
214                 0x4A30A000/12 to SCRM
215                 // 0x4A30B000/12 L4 interconnect
216                 0x4A30C000/12 to SYSCTRL_GENERAL_WKUP
217                 // 0x4A30D000/12 L4 interconnect
218                 /* 0x4A30E000/13 reserved */
219                 0x4A310000/12 to GPIO1
220                 // 0x4A311000/12 L4 interconnect
221                 /* 0x4A312000/13 reserved */
222                 0x4A314000/12 to WDTIMER2
223                 // 0x4A315000/12 L4 interconnect
224                 /* 0x4A316000/13 reserved */
225                 0x4A318000/12 to GPTIMER1
226                 // 0x4A319000/12 L4 interconnect
227                 /* 0x4A31A000/13 reserved (XXX: 'Module - Address space 0'?) */
228                 0x4A31C000/12 to Keyboard
229                 // 0x4A31D000/12 L4 interconnect
230                 0x4A31E000/12 to SYSCTRL_PADCONF_WKUP
231                 // 0x4A31F000/12 L4 interconnect
232                 /* 0x4A320000-0x4A325FFF reserved */
233                 0x4A326000/12 to SAR_RAM1
234                 0x4A327000/10 to SAR_RAM2
235                 /* 0x4A327400-0x4A327FFF reserved */
236                 0x4A328000/11 to SAR_RAM3
237                 /* 0x4A328800-0x4A328FFF reserved */
238                 0x4A329000/10 to SAR_RAM4
239                 /* 0x4A329400-0x4A329FFF reserved */
240                 // 0x4A32A000/12 L4 interconnect
241                 /* 0x4A32B000-0x4A33FFFF reserved */
242            ]
243
244 /*
245  * 2.3.3 L4_PER Memory Space Mapping
246  */
247 L4_PER is map [
248             0x48000000/11 to PER_AP
249             0x48000800/11 to PER_LA
250             0x48001000/10 to PER_IP0
251             0x48001400/10 to PER_IP1
252             0x48001800/10 to PER_IP2
253             0x48001C00/10 to PER_IP3
254             /* 0x48002000-0x4801FFFF reserved */
255             0x48020000/12 to UART3
256             // 0x48021000/12 L4 interconnect
257             /* 0x48022000/16 reserved */
258             0x48032000/12 to GPTIMER2
259             // 0x48033000/12 L4 interconnect
260             0x48034000/12 to GPTIMER3
261             // 0x48035000/12 L4 interconnect
262             0x48036000/12 to GPTIMER4
263             // 0x48037000/12 L4 interconnect
264             /* 0x48038000-0x4803DFFF reserved */
265             0x4803E000/12 to GPTIMER9
266             // 0x4803F000/12 L4 interconnect
267             0x48040000/16 to Display
268             // 0x48050000/12 L4 interconnect
269             /* 0x48051000/14 reserved */
270             0x48055000/12 to GPIO2
271             // 0x48056000/12 L4 interconnect
272             0x48057000/12 to GPIO3
273             // 0x48058000/12 L4 interconnect
274             0x48059000/12 to GPIO4
275             // 0x4805A000/12 L4 interconnect
276             0x4805B000/12 to GPIO5
277             // 0x4805C000/12 L4 interconnect
278             0x4805D000/12 to GPIO6
279             // 0x4805E000/12 L4 interconnect
280             /* 0x4805F000/12 reserved */
281             0x48060000/12 to I2C3
282             // 0x48061000/12 L4 interconnect
283             /* 0x48062000/15 reserved */
284             0x4806A000/12 to UART1
285             // 0x4806B000/12 L4 interconnect
286             0x4806C000/12 to UART2
287             // 0x4806D000/12 L4 interconnect
288             0x4806E000/12 to UART4
289             // 0x4806F000/12 L4 interconnect
290             0x48070000/12 to I2C1
291             // 0x48071000/12 L4 interconnect
292             0x48072000/12 to I2C2
293             // 0x48073000/12 L4 interconnect
294             /* 0x48074000/13 reserved */
295             0x48076000/12 to SLIMBUS2
296             // 0x48077000/12 L4 interconnect
297             0x48078000/12 to ELM
298             // 0x48079000/12 L4 interconnect
299             /* 0x4807A000-0x48085FFF reserved */
300             0x48086000/12 to GPTIMER10
301             // 0x48087000/12 L4 interconnect
302             0x48088000/12 to GPTIMER11
303             // 0x48089000/12 L4 interconnect
304             /* 0x4808A000-0x48095FFF reserved */
305             0x48096000/12 to McBSP4
306             // 0x48097000/12 L4 interconnect
307             0x48098000/12 to McSPI1
308             // 0x48099000/12 L4 interconnect
309             0x4809A000/12 to McSPI2
310             // 0x4809B000/12 L4 interconnect
311             0x4809C000/12 to HSMMC1
312             // 0x4809D000/12 L4 interconnect
313             /* 0x4809E000-0x480ACFFF reserved */
314             0x480AD000/12 to MMC_SD3
315             // 0x480AE000/12 L4 interconnect
316             /* 0x480AF000-0x480B1FFF reserved */
317             0x480B2000/12 to HDQ
318             // 0x480B3000/12 L4 interconnect
319             0x480B4000/12 to HSMMC2
320             // 0x480B5000/12 L4 interconnect
321             /* 0x480B6000/13 reserved */
322             0x480B8000/12 to McSPI3
323             // 0x480B9000/12 L4 interconnect
324             0x480BA000/12 to McSPI4
325             // 0x480BB000/12 L4 interconnect
326             /* 0x480BC000-0x480D0FFF reserved */
327             0x480D1000/12 to MMC_SD4
328             // 0x480D2000/12 L4 interconnect
329             /* 0x480D3000/13 reserved */
330             0x480D5000/12 to MMC_SD5
331             // 0x480D6000/12 L4 interconnect
332             /* 0x480D7000-0x4834FFFF reserved */
333             0x48350000/12 to I2C4
334             // 0x48351000/12 L4 interconnect
335             /* 0x48352000-0x48FFFFFF reserved */
336           ]
337
338 /*
339  * 2.3.4 L4_ABE Memory Space Mapping
340  */
341 DMEM,
342 CMEM,
343 SMEM are memory accept [0x0/16]
344
345 L4_ABE is accept [0x00000/14] // XXX: First 16KB do what?
346           map [
347             /* 0x04000-0x021FFF reserved */
348             0x22000/12 to McBSP1
349             // 0x23000/12 L4 interconnect
350             0x24000/12 to McBSP2
351             // 0x25000/12 L4 interconnect
352             0x26000/12 to McBSP3
353             // 0x27000/12 L4 interconnect
354             0x28000/12 to McASP
355             // 0x29000/12 L4 interconnect
356             0x2A000/12 to McASP_DATA
357             // 0x2B000/12 L4 interconnect
358             0x2C000/12 to SLIMBUS1
359             // 0x2D000/12 L4 interconnect
360             0x2E000/12 to DMIC
361             // 0x2F000/12 L4 interconnect
362             0x30000/12 to WDTIMER3
363             // 0x31000/12 L4 interconnect
364             0x32000/12 to McPDM
365             // 0x33000/12 L4 interconnect
366             /* 0x34000/14 reserved */
367             0x38000/12 to GPTIMER5
368             // 0x39000/12 L4 interconnect
369             0x3A000/12 to GPTIMER6
370             // 0x3B000/12 L4 interconnect
371             0x3C000/12 to GPTIMER7
372             // 0x3D000/12 L4 interconnect
373             0x3E000/12 to GPTIMER8
374             // 0x3F000/12 L4 interconnect
375             /* 0x40000/18 reserved */
376             0x80000/16 to DMEM
377             // 0x90000/12 L4 interconnect
378             /* 0x91000-0x9FFFF reserved */
379             0xA0000/16 to CMEM
380             // 0xB0000/12 L4 interconnect
381             /* 0xB1000-0xBFFFF reserved */
382             0xC0000/16 to SMEM
383             // 0xD0000/12 L4 interconnect
384             /* 0xD1000/17 reserved */
385             0xF1000/12 to AESS
386             // 0xF2000/12 L4 interconnect
387             /* 0xF3000-0xFFFFF reserved */
388           ]
389
390 /*
391  * Cortex A9 Memory Space Mapping
392  */
393 CortexA9-Subsystem as CortexA9_SS with
394     CORTEXA9_{c in [1..2]} > CPU_{c}
395     L3 < L3
396     L4_ABE < L4_ABE
397
398 /*
399  * 2.4 Dual Cortex-M3 Subsystem Memory Space Mapping
400  */
401 CORTEXM3_ROM is memory accept [0x0/14]
402 CORTEXM3_RAM is memory accept [0x0/16]
403
404 // TODO: address space not accessible from L3
405 CORTEXM3 is map [
406                     0x00000000-0x54FFFFFF to L3
407                     0x55000000/14 to CORTEXM3_ROM
408                     0x55020000/16 to CORTEXM3_RAM
409                     /* 0x55030000/16 reserved */
410                     0x55040000/18 to ISS at 0x10000 // XXX: Not accessible from L3?
411                     0x55080000/12 to M3_MMU
412                     0x55081000/12 to M3_WUGEN
413                     /* 0x55082000-0x55FFFFFF reserved */
414                     0x56000000/25 to L3
415                 ]
416
417 /*
418  * 2.5 DSP Subsystem Memory Space Mapping
419  */
420  // TODO: address space not accessible from L4_CFG
421  DSP is map [
422             0x01C20000/12 to SYSC
423         ]
424
425 /*
426  * 2.6 Display Subsystem Memory Space Mapping
427  */
428 Display is map [
429                 // 0x0000/12 Display subsystem registers
430                 0x1000/12 to DISPC
431                 0x2000/12 to RFBI
432                 0x3000/12 to VENC
433                 0x4000/12 to DSI1
434                 0x5000/12 to DSI2
435                 0x6000/12 to HDMI
436                 0x7000/12 to HDCP
437            ]
438
439 /*
440  * 3 Power, Reset and Clock Management
441  */
442 /*
443 /* 3.11.1 PRM Instance Summary */
444 INTRCONN_SOCKET_PRM is device accept [0x0/8]
445 CKGEN_PRM is device accept [0x0/8]
446 MPU_PRM is device accept [0x0/8]
447 DSP_PRM is device accept [0x0/8]
448 ABE_PRM is device accept [0x0/8]
449 ALWAYS_ON_PRM is device accept [0x0/8]
450 CORE_PRM is device accept [0x0/11]
451 IVAHD_PRM is device accept [0x0/8]
452 CAM_PRM is device accept [0x0/8]
453 DSS_PRM is device accept [0x0/8]
454 SGX_PRM is device accept [0x0/8]
455 L3INIT_PRM is device accept [0x0/8]
456 L4PER_PRM is device accept [0x0/9]
457 WKUP_PRM is device accept [0x0/8]
458 WKUP_CM is device accept [0x0/8]
459 EMU_PRM is device accept [0x0/8]
460 EMU_CM is device accept [0x0/8]
461 DEVICE_PRM is device accept [0x0/8]
462 INSTR_PRM is device accept [0x0/8]
463 PRM is map [
464             0x0000/8 to INTRCONN_SOCKET_PRM
465             0x0100/8 to CKGEN_PRM
466             0x0300/8 to MPU_PRM
467             0x0400/8 to DSP_PRM
468             0x0500/8 to ABE_PRM
469             0x0600/8 to ALWAYS_ON_PRM
470             0x0700/11 to CORE_PRM
471             0x0F00/8 to IVAHD_PRM
472             0x1000/8 to CAM_PRM
473             0x1100/8 to DSS_PRM
474             0x1200/8 to SGX_PRM
475             0x1300/8 to L3INIT_PRM
476             0x1400/9 to L4PER_PRM
477             0x1700/8 to WKUP_PRM
478             0x1800/8 to WKUP_CM
479             0x1900/8 to EMU_PRM
480             0x1A00/8 to EMU_CM
481             0x1B00/8 to DEVICE_PRM
482             0x1F00/8 to INSTR_PRM
483        ]
484
485 /* 3.11.21 CM1 Instance Summary */
486 INTERCONN_SOCKET_CM1 is device accept [0x0/8]
487 CKGEN_CM1 is device accept [0x0/9]
488 CM1 is map [
489         0x000/8 to INTERCONN_SOCKET_CM1
490         0x100/9 to CKGEN_CM1
491        ]
492
493 /* 3.11.29 CM2 Instance Summary */
494 INTRCONN_SOCKET_CM2 is device accept [0x0/8]
495 CKGEN_CM2 is device accept [0x0/8]
496 ALWAYS_ON_CM2 is device accept [0x0/8]
497 CORE_CM2 is device accept [0x0/11]
498 IVAHD_CM2 is device accept [0x0/8]
499 CAM_CM2 is device accept [0x0/8]
500 DSS_CM2 is device accept [0x0/8]
501 SGX_CM2 is device accept [0x0/8]
502 L3INIT_CM2 is device accept [0x0/8]
503 L4PER_CM2 is device accept [0x0/9]
504 RESTORE_CM2 is device accept [0x0/8]
505 INSTR_CM2 is device accept [0x0/8]
506 CM2 is map [
507         0x0000/8 to INTRCONN_SOCKET_CM2
508         0x0100/8 to CKGEN_CM2
509         0x0600/8 to ALWAYS_ON_CM2
510         0x0700/11 to CORE_CM2
511         0x0F00/8 to IVAHD_CM2
512         0x1000/8 to CAM_CM2
513         0x1200/8 to SGX_CM2
514         0x1300/8 to L3INIT_CM2
515         0x1400/9 to L4PER_CM2
516         0x1E00/8 to RESTORE_CM2
517         0x1F00/8 to INSTR_CM2
518        ]
519
520 /* 3.12 SCRM Register Manual */
521 SCRM is device accept [0x0/12]
522
523 /* 3.13 SR Register Manual */
524 SR_MPU is device accept [0x0/8]
525 SR_IVA is device accept [0x0/8]
526 SR_CORE is device accept [0x0/8]
527
528 /*
529  * 5 DSP Subsystem
530  */
531 SYS_INTC is device accept [0x0/16]
532 SYS_PD is device accept [0x0/16]
533 EDM is device accept [0x0/12]
534 TPCC is device accept [0x0/16]
535 TPTC0,
536 TPTC1 are device accept [0x0/10]
537 SYSC is device accept [0x0/12]
538 WUGEN is device accept [0x0/12]
539 L1_SCACHE,
540 L2_SCACHE are device accept [0x0/8]
541 SCACHE_SCTM is device accept [0x0/9]
542 SCACHE_MMU is device accept [0x0/11]
543
544 /*
545  * 6 IVA-HD Subsystem
546  */
547 SYSCTRL is device accept [0x0/10]
548
549 /*
550  * 7 Dual Cortex-M3 MPU Subsystem
551  */
552 M3_WUGEN is device accept [0x0/12]
553
554 /*
555  * 8 Imaging Subsystem
556  */
557 ISS_TOP is device accept [0x0/8]
558 ISP5 is device accept [0x0/16]
559 SIMCOP is device accept [0x0/17]
560 ISS is map [
561             0x00000/8 to ISS_TOP
562             // TODO: Interfaces
563             0x10000/17 to ISP5
564             0x20000/17 to SIMCOP
565           ]
566
567 /*
568  * 9 Face Detect
569  */
570 FDIF is device accept [0x0/12]
571
572 /*
573  * 10 Display Subsystem
574  */
575 DISPC,
576 RFBI,
577 VENC,
578 DSI1,
579 DSI2,
580 HDMI,
581 HDCP are device accept [0x0/12]
582
583 /*
584  * 11 2D/3D Graphics Accelerator
585  */
586 SGX is device accept [0x0/25]
587
588 /*
589  * 12 Audio Backend
590  */
591 AESS is device accept [0x0/12]
592
593 /*
594  * 13 Interconnect
595  */
596 /* 13.2 L3 Interconnect */
597 L3_config is device accept [0x0/26]
598 C2C_INIT_firewall is device accept [0x0/12] // not in TRM, from omap44xx_map.h
599 C2C_TARGET_firewall is device accept [0x0/12] // not in TRM, from omap44xx_map.h
600 MA_firewall is device accept[0x0/12]
601 EMIF_firewall is device accept [0x0/12]
602 GPMC_firewall is device accept [0x0/12]
603 L3_OCMC_RAM_firewall is device accept [0x0/12]
604 SGX_firewall is device accept [0x0/12]
605 ISS_firewall is device accept [0x0/12]
606 M3_firewall is device accept [0x0/12]
607 DSS_firewall is device accept [0x0/12]
608 SL2_firewall is device accept [0x0/12]
609 IVA-HD_firewall is device accept [0x0/12]
610 L4-EMU_firewall is device accept [0x0/12]
611 L4-ABE_firewall is device accept [0x0/12]
612
613 /* 13.3 L4 Interconnects */
614 PER_AP is device accept [0x0/11]
615 PER_LA is device accept [0x0/11]
616 PER_IP0 is device accept [0x0/10]
617 PER_IP1 is device accept [0x0/10]
618 PER_IP2 is device accept [0x0/10]
619 PER_IP3 is device accept [0x0/10]
620
621 CFG_AP is device accept [0x0/11]
622 CFG_LA is device accept [0x0/11]
623 CFG_IP0 is device accept [0x0/12]
624
625 WKUP_AP is device accept [0x0/11]
626 WKUP_LA is device accept [0x0/11]
627 WKUP_IP0 is device accept [0x0/12]
628
629 /*
630  * 15 Memory Subsystem
631  */
632 DMM is device accept [0x0/25]
633 EMIF1,
634 EMIF2 are device accept [0x4D000000/24]
635 GPMC is device accept [0x0/25]
636 ELM is device accept [0x48078000/12]
637
638 /*
639  * 16 SDMA
640  */
641 SDMA is device accept [0x0/12]
642
643 /*
644  * 17 Interrupt Controllers
645  */
646 // TODO
647
648 /*
649  * 18 Control Module
650  */
651 SYSCTRL_GENERAL_CORE,
652 SYSCTRL_GENERAL_WKUP,
653 SYSCTRL_PADCONF_CORE,
654 SYSCTRL_PADCONF_WKUP are device accept [0x0/12]
655
656
657 /*
658  * 19 Mailbox
659  */
660 System_Mailbox,
661 IVAHD_Mailbox are device accept[0x0/12]
662
663 /*
664  * 20 Memory Management Units
665  */
666 M3_MMU,
667 DSP_MMU are device accept [0x0/12]
668
669 /*
670  * 21 Spinlock
671  */
672 Spinlock is device accept [0x0/12]
673
674 /*
675  * 22 Timers
676  */
677 /* 22.2 General Purpose Timers */
678 GPTIMER{[1..11]} are device accept [0x0/12]
679
680 /* 22.3 Watchdog Timers */
681 WDTIMER{[2..3]} are device accept [0x0/12]
682
683 /* 22.4 32-KHz Synchronized Timer */
684 S32KTIMER is device accept [0x0/12]
685
686 /*
687  * 23 Serial Communication Interface
688  */
689
690 /* 23.1 Multimaster High-Speed I2C Controller */
691 I2C{[1..4]} are device accept [0x0/8]
692
693 /* 23.2 HDQ/1-Wire */
694 HDQ is device accept [0x0/12]
695
696 /* 23.3.1 UART/IrDA/CIR */
697 UART{[1..4]} are device accept [0x0/10]
698
699 /* 23.4 Mulitchannel Serial Port Interface */
700 McSPI{[1..4]} are device accept [0x0/12]
701
702 /* 23.5 Multichannel Buffered Serial Port */
703 McBSP{[1..4]} are device accept [0x0/12]
704
705 /* 23.6 Multichannel PDM Controller */
706 McPDM is device accept [0x0/12]
707
708 /* 23.7 Digital Microphone Module */
709 DMIC is device accept [0x0/12]
710
711 /* 23.8 Multichannel Audio Serial Port */
712 McASP is device accept [0x0/12]
713 McASP_DATA is device accept [0x0/12]
714
715 /* 23.9 Serial Low-Power Inter-Chip Media Bus Controller */
716 SLIMBUS{[1..2]} are device accept [0x0/12]
717
718 /* 23.10 MIPI-HSI */
719 HSI_TOP is device accept [0x0-0x1400]
720 HSI_DMA_CHANNELS is device accept [0x0/10]
721 HSI_PORTS is device accept [0x0/13]
722
723 HSI is map [
724         0x0000-0x1400 to HSI_TOP
725         0x1800/10 to HSI_DMA_CHANNELS
726         0x000/13 to HSI_PORTS
727        ]
728
729 /* 23.11 High-Speed Multiport USB Host Subsystem */
730 HSUSBTLL is device accept [0x0/12]
731 HSUSBHOST is device accept [0x0/12]
732
733 /* 23.12 High-Speed USB OTG Controller */
734 HSUSBOTG is device accept [0x0/12]
735 USBPHY is device accept [0x0/12]
736
737 /* 23.13 Full-speed USB Host Controller */
738 FSUSBHOST is device accept[0x0/12]
739
740 /*
741  * 24 MMC/SD/SDIO
742  */
743 HSMMC{[1..2]},
744 MMC_SD{[3..5]} are device accept [0x0/12]
745
746 /*
747  * 25 General Purpose Interface
748  */
749 GPIO{[1..6]} are device accept [0x0/12]
750
751 /*
752  * 26 Keyboard Controller
753  */
754 Keyboard is device accept [0x0/12]
755
756 /*
757  * 28.10 On-Chip Debug Support Memory Mapping
758  */
759 MIPI_STM_0 is device accept [0x0/20]
760 MIPI_STM_1 is device accept [0x0/18]
761 A9_CPU0_debug_PMU is device accept [0x0/13]
762 A9_CPU1_debug_PMU is device accept [0x0/13]
763 CTI0 is device accept [0x0/12]
764 CTI1 is device accept [0x0/12]
765 PTM0 is device accept [0x0/12]
766 PTM1 is device accept [0x0/12]
767 A9_CS-TF is device accept [0x0/12]
768 DAP_PC is device accept [0x0/12]
769 APB is device accept [0x0/12]
770 DRM is device accept [0x0/12]
771 MIPI_STM is device accept [0x0/12]
772 CS-ETB is device accept [0x0/12]
773 CS-TPIU is device accept [0x0/12]
774 CS-TF is device accept [0x0/12]
775
776 OCP-WP is device accept [0x0/12]
777
778 PMI is device accept [0x0/8]