timer interrupts enabled
authorClaudio Föllmi <foellmic@student.ethz.ch>
Wed, 4 Sep 2013 23:15:10 +0000 (01:15 +0200)
committerClaudio Föllmi <foellmic@student.ethz.ch>
Wed, 4 Sep 2013 23:15:10 +0000 (01:15 +0200)
commita99b6f3f9a3bcddf4e9df34d8b5fe55571b03399
tree9446b136863e05b638dd91fef43fa19623d6342e
parente22a7dadb9129b0928bc8e76e202aa506b49fdb3
timer interrupts enabled

fixed interrupt handler writing to trap area for non-trap interrupts
enabled timer interrupts at reasonable intervals (reasonable for -O2 and no caches)
added system call for restoring a context (just for armv7-m, replacing a x86-specific interrupt),
because the ONLY way to restore an IT block is by exiting handler mode (there is literally no other mechanism)
(will only be called if userspace tries to restore a context that was saved by the kernel, and comes from interrupting an IT block or a ldm/stm instruction)

You may want to use -O2 from now on (because we use interrupts, and thrashing is possible)
The compiler we use will probably complain up to 3 times ("unable to find a register to spill in class 'GENERAL_REGS'")
just retry the faulting compile instruction with -O1, and then restart make
15 files changed:
devices/omap/omap44xx_cortex_m3_nvic.dev
include/arch/arm/barrelfish/syscall_arch.h
include/barrelfish_kpi/sys_debug.h
include/barrelfish_kpi/syscalls.h
kernel/arch/armv7-m/exceptions.S
kernel/arch/armv7-m/exec.c
kernel/arch/armv7-m/exn.c
kernel/arch/armv7-m/init.c
kernel/arch/armv7/syscall.c
kernel/include/arch/armv7-m/armv7_syscall.h
kernel/include/arch/armv7-m/exceptions.h
lib/barrelfish/arch/arm/dispatch.c
lib/barrelfish/arch/arm/entry.S
lib/barrelfish/arch/arm/syscall.S
lib/barrelfish/arch/arm/syscalls.c