-- Mackerel 1 device descriptions
[ mackerel (options arch) f
- | f <- [ "ac97_base_audio",
- "ac97_ext_audio",
- "ac97_ext_codec",
- "ac97_ext_modem",
- "acpi_ec",
+ | f <- [ "acpi_ec",
"ahci_hba",
"ahci_port",
"amd_vmcb",
-- Mackerel 2 device descriptions
[ mackerel2 (options arch) f
- | f <- ["pc16550d_uart",
- "ixp2800_icp_pic",
- "ixp2800_uart",
- "ixp2800_icp_pit",
- "lpc_kbd"
+ | f <- [ "ac97_base_audio",
+ "ac97_ext_audio",
+ "ac97_ext_codec",
+ "ac97_ext_modem",
+ "pc16550d",
+ "ixp2800_icp_pic",
+ "ixp2800_uart",
+ "ixp2800_icp_pit",
+ "lpc_kbd"
], arch <- allArchitectures
]
* Semiconductor (TL/C/8652 and RRD-B30M75).
*/
-device pc16550d_uart lsbfirst ( io base ) "PC16550D UART" {
+device pc16550d lsbfirst ( io base ) "PC16550D UART" {
constants trigger_lvl "RCVR FIFO trigger level" {
bytes1 = 0b00 "Every byte";
bytes4 = 0b01 "Every 4th byte";
and write functions that \Mac code requires, and some other
preprocessor macros to ensure correct C code generation.
-\Mac prefixes all declarations in the file with the
-name of the file plus an underscore (``\texttt{DEV\_}''). However, for
-most (though not all) declarations this prefix can be overridden by
-defining the macro ``\texttt{DEV\_PREFIX}'' before including the file.
-This is at first sight a little confusing. Suppose we have a device
-called \texttt{pc16550d\_uart}. By default, any declaration
-\texttt{foo} in \Mac file will correspond to
-\texttt{pc16550d\_uart\_foo} in the header file.
+%% \Mac prefixes all declarations in the file with the
+%% name of the file plus an underscore (``\texttt{DEV\_}''). However, for
+%% most (though not all) declarations this prefix can be overridden by
+%% defining the macro ``\texttt{DEV\_PREFIX}'' before including the file.
-If, however, we include a line:
+%% This is at first sight a little confusing. Suppose we have a device
+%% called \texttt{pc16550d\_uart}. By default, any declaration
+%% \texttt{foo} in \Mac file will correspond to
+%% \texttt{pc16550d\_uart\_foo} in the header file.
-\begin{quote}
- \texttt{\#define pc16550d\_uart\_PREFIX uart}
-\end{quote}
+%% If, however, we include a line:
+
+%% \begin{quote}
+%% \texttt{\#define pc16550d\_uart\_PREFIX uart}
+%% \end{quote}
--- before including the header file, that declaration is likely to now
-be \texttt{uart\_foo}.
+%% -- before including the header file, that declaration is likely to now
+%% be \texttt{uart\_foo}.
In the rest of this chapter, we'll use ``\texttt{DN\_}'' as the
device prefix that cannot be redefined in this manner, and ``\texttt{DP\_}''
preprocessor macros to ensure correct C code generation.
\Mac prefixes all declarations in the file with the
-name of the file plus an underscore (``\texttt{DEV\_}''). However, for
-most (though not all) declarations this prefix can be overridden by
-defining the macro ``\texttt{DEV\_PREFIX}'' before including the file.
+name of the file plus an underscore (``\texttt{DEV\_}'').
-This is at first sight a little confusing. Suppose we have a device
-called \texttt{pc16550d\_uart}. By default, any declaration
-\texttt{foo} in \Mac file will correspond to
-\texttt{pc16550d\_uart\_foo} in the header file.
-If, however, we include a line:
+%% However, for
+%% most (though not all) declarations this prefix can be overridden by
+%% defining the macro ``\texttt{DEV\_PREFIX}'' before including the file.
-\begin{quote}
- \texttt{\#define pc16550d\_uart\_PREFIX uart}
-\end{quote}
+%% This is at first sight a little confusing. Suppose we have a device
+%% called \texttt{pc16550d\_uart}. By default, any declaration
+%% \texttt{foo} in \Mac file will correspond to
+%% \texttt{pc16550d\_uart\_foo} in the header file.
+
+%% If, however, we include a line:
+
+%% \begin{quote}
+%% \texttt{\#define pc16550d\_uart\_PREFIX uart}
+%% \end{quote}
--- before including the header file, that declaration is likely to now
-be \texttt{uart\_foo}.
+%% -- before including the header file, that declaration is likely to now
+%% be \texttt{uart\_foo}.
In the rest of this chapter, we'll use ``\texttt{DN\_}'' as the
device prefix that cannot be redefined in this manner, and ``\texttt{DP\_}''
x86_sFiles = [ "init_ap_x86_64.S", "init_ap_x86_32.S" ]
absolute_cFiles = (map in_x86_dir x86_cFiles)
absolute_sFiles = (map in_x86_dir x86_sFiles)
- mackerelFiles = [ "lpc_pic", "pc16550d_uart", "ia32",
+ mackerelFiles = [ "lpc_pic", "pc16550d", "ia32",
"xapic", "cmos", "amd_vmcb", "cpuid", "lpc_rtc" ]
libs = [ "elf_kernel" ]
in mkrules "x86_64" cfiles sfiles mackerelFiles libs absolute_cFiles absolute_sFiles [] []),
x86_sFiles = [ "init_ap_x86_64.S", "init_ap_x86_32.S" ]
absolute_cFiles = (map in_x86_dir x86_cFiles)
absolute_sFiles = (map in_x86_dir x86_sFiles)
- mackerelFiles = [ "lpc_pic", "pc16550d_uart", "ia32",
+ mackerelFiles = [ "lpc_pic", "pc16550d", "ia32",
"xapic", "cmos", "cpuid", "lpc_rtc" ]
libs = [ "elf_kernel" ]
in mkrules "x86_32" cfiles sfiles mackerelFiles libs absolute_cFiles absolute_sFiles [] []),
indep_sFiles = (map in_x86_dir x86_sFiles)
mackerelFiles =
if Config.rck_emu then
- [ "pc16550d_uart", "ia32", "xapic", "rck", "eMAC", "lpc_pic", "cmos", "cpuid" ]
+ [ "pc16550d", "ia32", "xapic", "rck", "eMAC", "lpc_pic", "cmos", "cpuid" ]
else
- [ "pc16550d_uart", "ia32", "xapic", "rck", "eMAC", "cpuid" ]
+ [ "pc16550d", "ia32", "xapic", "rck", "eMAC", "cpuid" ]
libs = [ "elf_kernel" ]
in mkrules "scc" cfiles sfiles mackerelFiles libs indep_cFiles indep_sFiles arch_cfiles arch_sfiles),
#include <lpc_pic_dev.h>
/// The dual PIC
-static LPC_PIC_t pic;
+static lpc_pic_t pic;
/**
* \brief Send end of interrupt.
void pic_eoi(int irq)
{
// Send specific end of interrupt message
- static LPC_PIC_ocw2_t eoi = {
- .rsleoi = LPC_PIC_seoi
+ static lpc_pic_ocw2_t eoi = {
+ .rsleoi = lpc_pic_seoi
};
if(irq < 8) {
eoi.level = irq;
- LPC_PIC_master_ocw2_wr(&pic, eoi);
+ lpc_pic_master_ocw2_wr(&pic, eoi);
} else {
eoi.level = irq - 8;
- LPC_PIC_slave_ocw2_wr(&pic, eoi);
+ lpc_pic_slave_ocw2_wr(&pic, eoi);
}
}
*/
bool pic_have_interrupt(int irq)
{
- static const LPC_PIC_ocw3_t read_is = {
- .rrc = LPC_PIC_read_is
+ static const lpc_pic_ocw3_t read_is = {
+ .rrc = lpc_pic_read_is
};
if(irq < 8) {
// send read ISR command
- LPC_PIC_master_ocw3_wr(&pic, read_is);
+ lpc_pic_master_ocw3_wr(&pic, read_is);
// read ISR and check bit
- return (LPC_PIC_master_ocw3rd_rd(&pic) & (1 << irq)) != 0;
+ return (lpc_pic_master_ocw3rd_rd(&pic) & (1 << irq)) != 0;
} else {
- LPC_PIC_slave_ocw3_wr(&pic, read_is);
- return (LPC_PIC_slave_ocw3rd_rd(&pic) & (1 << (irq -8))) != 0;
+ lpc_pic_slave_ocw3_wr(&pic, read_is);
+ return (lpc_pic_slave_ocw3rd_rd(&pic) & (1 << (irq -8))) != 0;
}
}
*/
int pic_pending_interrupt(void)
{
- static const LPC_PIC_ocw3_t read_is = {
- .rrc = LPC_PIC_read_is
+ static const lpc_pic_ocw3_t read_is = {
+ .rrc = lpc_pic_read_is
};
uint8_t isr;
// try master first
- LPC_PIC_master_ocw3_wr(&pic, read_is);
- isr = LPC_PIC_master_ocw3rd_rd(&pic);
+ lpc_pic_master_ocw3_wr(&pic, read_is);
+ isr = lpc_pic_master_ocw3rd_rd(&pic);
if (isr != 0) {
return mask_to_interrupt(isr);
}
// try slave
- LPC_PIC_slave_ocw3_wr(&pic, read_is);
- isr = LPC_PIC_slave_ocw3rd_rd(&pic);
+ lpc_pic_slave_ocw3_wr(&pic, read_is);
+ isr = lpc_pic_slave_ocw3rd_rd(&pic);
if (isr != 0) {
return mask_to_interrupt(isr) + 8;
}
void pic_init(void)
{
// setup mackerel state
- LPC_PIC_initialize(&pic, 0);
+ lpc_pic_initialize(&pic, 0);
- LPC_PIC_icw1_t icw1 = { .ltim = 0 };
- LPC_PIC_pic_master_icw3_t master_icw3 = {
+ lpc_pic_icw1_t icw1 = { .ltim = 0 };
+ lpc_pic_pic_master_icw3_t master_icw3 = {
.cascade = 1 /* Slaves attached to IR line 2 */
};
- LPC_PIC_pic_slave_icw3_t slave_icw3 = {
+ lpc_pic_pic_slave_icw3_t slave_icw3 = {
.slave_id = 2 /* This slave in IR line 2 of master */
};
- LPC_PIC_icw4_t icw4 = {
+ lpc_pic_icw4_t icw4 = {
.aeoi = 0,
.sfnm = 0
};
// Setup 8259A PIC for proper protected mode interrupt delivery
/* ICW1 */
- LPC_PIC_master_icw1_wr(&pic, icw1);
- LPC_PIC_slave_icw1_wr(&pic, icw1);
+ lpc_pic_master_icw1_wr(&pic, icw1);
+ lpc_pic_slave_icw1_wr(&pic, icw1);
/* ICW2 */
- LPC_PIC_master_icw2_wr_raw(&pic, 0x20); // IDT offset 0x20
- LPC_PIC_slave_icw2_wr_raw(&pic, 0x28); // IDT offset 0x28
+ lpc_pic_master_icw2_wr_raw(&pic, 0x20); // IDT offset 0x20
+ lpc_pic_slave_icw2_wr_raw(&pic, 0x28); // IDT offset 0x28
/* ICW3 */
- LPC_PIC_master_icw3_wr(&pic, master_icw3);
- LPC_PIC_slave_icw3_wr(&pic, slave_icw3);
+ lpc_pic_master_icw3_wr(&pic, master_icw3);
+ lpc_pic_slave_icw3_wr(&pic, slave_icw3);
/* ICW4 */
- LPC_PIC_master_icw4_wr(&pic, icw4);
- LPC_PIC_slave_icw4_wr(&pic, icw4);
+ lpc_pic_master_icw4_wr(&pic, icw4);
+ lpc_pic_slave_icw4_wr(&pic, icw4);
if (CPU_IS_M5_SIMULATOR) {
printf("Warning: not setting elcr1 elcr2 on M5\n");
} else {
// Set all interrupts to be edge triggered
- LPC_PIC_pic_master_trigger_t elcr1 = {
+ lpc_pic_pic_master_trigger_t elcr1 = {
.irq3_ecl = 0,
.irq4_ecl = 0,
.irq5_ecl = 0,
.irq6_ecl = 0,
.irq7_ecl = 0
};
- LPC_PIC_master_trigger_wr(&pic, elcr1);
+ lpc_pic_master_trigger_wr(&pic, elcr1);
- LPC_PIC_pic_slave_trigger_t elcr2 = {
+ lpc_pic_pic_slave_trigger_t elcr2 = {
.irq9_ecl = 0,
.irq10_ecl = 0,
.irq11_ecl = 0,
.irq14_ecl = 0,
.irq15_ecl = 0
};
- LPC_PIC_slave_trigger_wr(&pic, elcr2);
+ lpc_pic_slave_trigger_wr(&pic, elcr2);
}
// Mask all interrupts (except cascade IRQ 2)
- LPC_PIC_slave_ocw1_wr(&pic, 0xff);
- LPC_PIC_master_ocw1_wr(&pic, ~(1 << 2));
+ lpc_pic_slave_ocw1_wr(&pic, 0xff);
+ lpc_pic_master_ocw1_wr(&pic, ~(1 << 2));
}
/**
if(irq < 8) {
// Master controller
uint8_t mask = 1 << irq;
- uint8_t val = LPC_PIC_master_ocw1_rd(&pic);
+ uint8_t val = lpc_pic_master_ocw1_rd(&pic);
if(enable) {
val &= ~mask;
val |= mask;
}
- LPC_PIC_master_ocw1_wr(&pic, val);
+ lpc_pic_master_ocw1_wr(&pic, val);
} else {
// Slave controller
uint8_t mask = 1 << (irq - 8);
- uint8_t val = LPC_PIC_slave_ocw1_rd(&pic);
+ uint8_t val = lpc_pic_slave_ocw1_rd(&pic);
if(enable) {
val &= ~mask;
val |= mask;
}
- LPC_PIC_slave_ocw1_wr(&pic, val);
+ lpc_pic_slave_ocw1_wr(&pic, val);
}
}
#include <arch/x86/rtc.h>
#include "lpc_rtc_dev.h"
-static LPC_rtc_t rtc;
+static lpc_rtc_t rtc;
/** \brief This function reads the hardware clock.
This function reads the hardware real time clock and fills the
void rtc_write_cmos(int addr, uint8_t b)
{
- LPC_rtc_ndx_wr(&rtc,addr);
- LPC_rtc_target_wr(&rtc,b);
+ lpc_rtc_ndx_wr(&rtc,addr);
+ lpc_rtc_target_wr(&rtc,b);
}
void rtc_write_extended(int addr, uint8_t b)
{
- LPC_rtc_endx_wr(&rtc,addr);
- LPC_rtc_etarget_wr(&rtc,b);
+ lpc_rtc_endx_wr(&rtc,addr);
+ lpc_rtc_etarget_wr(&rtc,b);
}
uint8_t rtc_read_cmos(int addr)
{
- LPC_rtc_ndx_wr(&rtc,addr);
- return LPC_rtc_target_rd(&rtc);
+ lpc_rtc_ndx_wr(&rtc,addr);
+ return lpc_rtc_target_rd(&rtc);
}
uint8_t rtc_read_extended(int addr, uint8_t b)
{
- LPC_rtc_endx_wr(&rtc,addr);
- return LPC_rtc_etarget_rd(&rtc);
+ lpc_rtc_endx_wr(&rtc,addr);
+ return lpc_rtc_etarget_rd(&rtc);
}
-static inline uint8_t _rtc_read( LPC_rtc_t *rt, uint8_t _r)
+static inline uint8_t _rtc_read( lpc_rtc_t *rt, uint8_t _r)
{
- LPC_rtc_ndx_wr(rt,_r);
- return LPC_rtc_target_rd(rt);
+ lpc_rtc_ndx_wr(rt,_r);
+ return lpc_rtc_target_rd(rt);
}
uint8_t sec, min, hr;
// read hour
- hr = _rtc_read(&rtc, LPC_rtc_hours );
+ hr = _rtc_read(&rtc, lpc_rtc_hours );
// read minutes
- min = _rtc_read(&rtc, LPC_rtc_minutes );
+ min = _rtc_read(&rtc, lpc_rtc_minutes );
// read seconds
- sec = _rtc_read(&rtc, LPC_rtc_seconds );
+ sec = _rtc_read(&rtc, lpc_rtc_seconds );
// Convert in the case of BCD hours
- LPC_rtc_ndx_wr(&rtc, LPC_rtc_regb);
- if ( LPC_rtc_regb_rd(&rtc).dm ) {
+ lpc_rtc_ndx_wr(&rtc, lpc_rtc_regb);
+ if ( lpc_rtc_regb_rd(&rtc).dm ) {
t->hr = hr;
t->min = min;
t->sec = sec;
uint8_t rtc_read_secs(void)
{
- while(_rtc_read(&rtc, LPC_rtc_rega) & 128);
- return _rtc_read(&rtc, LPC_rtc_seconds);
+ while(_rtc_read(&rtc, lpc_rtc_rega) & 128);
+ return _rtc_read(&rtc, lpc_rtc_seconds);
}
void rtc_init(void)
{
- LPC_rtc_initialize(&rtc, 0x00);
+ lpc_rtc_initialize(&rtc, 0x00);
// Set RTC to binary mode (not BCD), no interrupts
/* rtc_write_cmos(0xb, (1 << 1) | (1 << 2)); */
#include <kernel.h>
#include <x86.h>
#include <serial.h>
-#include "pc16550d_uart_dev.h"
+#include "pc16550d_dev.h"
int serial_portbase = 0x3f8; // COM1 default, can be changed via command-line arg
#define HEXLETTER 0x3a
#define HEXCORRECTION 0x7
-static PC16550D_UART_t uart;
+static pc16550d_t uart;
/** \brief Initialise the serial driver. */
errval_t serial_console_init(uint8_t ordinal)
{
assert(ordinal == 0); // multiple ports NYI
- PC16550D_UART_initialize(&uart, serial_portbase);
+ pc16550d_initialize(&uart, serial_portbase);
// XXX: if non-BSP core, assume HW is already initialised
if (!arch_core_is_bsp()) {
// Initialize UART
// disable interrupt
- PC16550D_UART_ier_t ier = PC16550D_UART_ier_default;
- ier = PC16550D_UART_ier_erbfi_insert(ier, 0);
- PC16550D_UART_ier_wr(&uart, ier);
+ pc16550d_ier_t ier = pc16550d_ier_default;
+ ier = pc16550d_ier_erbfi_insert(ier, 0);
+ pc16550d_ier_wr(&uart, ier);
// enable FIFOs
- PC16550D_UART_fcr_t fcr = PC16550D_UART_fcr_default;
- fcr = PC16550D_UART_fcr_fifoe_insert(fcr, 1);
+ pc16550d_fcr_t fcr = pc16550d_fcr_default;
+ fcr = pc16550d_fcr_fifoe_insert(fcr, 1);
// FIFOs hold 14 bytes
- fcr = PC16550D_UART_fcr_rtrigger_insert(fcr, PC16550D_UART_bytes14);
- PC16550D_UART_fcr_wr(&uart, fcr);
+ fcr = pc16550d_fcr_rtrigger_insert(fcr, pc16550d_bytes14);
+ pc16550d_fcr_wr(&uart, fcr);
- PC16550D_UART_lcr_t lcr = PC16550D_UART_lcr_default;
- lcr = PC16550D_UART_lcr_wls_insert(lcr, PC16550D_UART_bits8); // 8 data bits
- lcr = PC16550D_UART_lcr_stb_insert(lcr, 1); // 1 stop bit
- lcr = PC16550D_UART_lcr_pen_insert(lcr, 0); // no parity
- PC16550D_UART_lcr_wr(&uart, lcr);
+ pc16550d_lcr_t lcr = pc16550d_lcr_default;
+ lcr = pc16550d_lcr_wls_insert(lcr, pc16550d_bits8); // 8 data bits
+ lcr = pc16550d_lcr_stb_insert(lcr, 1); // 1 stop bit
+ lcr = pc16550d_lcr_pen_insert(lcr, 0); // no parity
+ pc16550d_lcr_wr(&uart, lcr);
// set data terminal ready
- PC16550D_UART_mcr_t mcr = PC16550D_UART_mcr_default;
- mcr = PC16550D_UART_mcr_dtr_insert(mcr, 1);
- mcr = PC16550D_UART_mcr_out_insert(mcr, 2);
- PC16550D_UART_mcr_wr(&uart, mcr);
+ pc16550d_mcr_t mcr = pc16550d_mcr_default;
+ mcr = pc16550d_mcr_dtr_insert(mcr, 1);
+ mcr = pc16550d_mcr_out_insert(mcr, 2);
+ pc16550d_mcr_wr(&uart, mcr);
// Set baudrate (XXX: hard-coded to 115200)
if (!CPU_IS_M5_SIMULATOR) {
- PC16550D_UART_lcr_dlab_wrf(&uart, 1);
- PC16550D_UART_dl_wr(&uart, PC16550D_UART_baud115200);
- PC16550D_UART_lcr_dlab_wrf(&uart, 0);
+ pc16550d_lcr_dlab_wrf(&uart, 1);
+ pc16550d_dl_wr(&uart, pc16550d_baud115200);
+ pc16550d_lcr_dlab_wrf(&uart, 0);
}
return SYS_ERR_OK;
void serial_console_putchar(char c)
{
// Wait until FIFO can hold more characters
- while(!PC16550D_UART_lsr_thre_rdf(&uart));
+ while(!pc16550d_lsr_thre_rdf(&uart));
// Write character
- PC16550D_UART_thr_wr(&uart, c);
+ pc16550d_thr_wr(&uart, c);
}
/** \brief Reads a single character from the default serial port.
char serial_console_getchar(void)
{
// Read as many characters as possible from FIFO
- while( !PC16550D_UART_lsr_dr_rdf(&uart));
- return PC16550D_UART_rbr_rd(&uart);
+ while( !pc16550d_lsr_dr_rdf(&uart));
+ return pc16550d_rbr_rd(&uart);
}
errval_t serial_debug_init(uint8_t ordinal)
qual_trec t l = qual_name (TT.tt_name t) l
qual_name :: TN.Name -> [ String ] -> String
-qual_name (TN.Name dn tn) l = concat $ intersperse "_" ([dn] ++ l ++ [tn])
+qual_name (TN.Name dn tn) l = concat $ intersperse "_" ([dn, tn] ++ l)
--
-- Language mapping: C type and name definitions
-------------------------------------------------------------------------
builtin_to_c :: TN.Name -> String
-builtin_to_c (TN.Name _ t) = (t ++ "_t")
+builtin_to_c tn = (TN.typeName tn) ++ "_t"
round_field_size w
| w <= 8 = "uint8_t"
--
regtype_c_name :: TT.Rec -> String
regtype_c_name rt
- | TT.is_builtin rt = (TT.type_name rt) ++ "_t"
+ | TT.is_builtin rt = (TN.typeName $ TT.tt_name rt) ++ "_t"
| otherwise = qual_typerec rt ["t"]
regtype_initial_macro_name :: TT.Rec -> String
register_shadow_ref :: RT.Rec -> C.Expr
register_shadow_ref r =
- let deref = C.DerefField (C.Variable cv_dev) (register_shadow_name r)
+ let deref = C.DerefField (C.Variable cv_dev) (device_shadow_field_name r)
in
if RT.is_array r then
C.SubscriptOf deref (C.Variable cv_i)
*
****************************************************************/
-static struct LPC_timer_t timer; ///< Mackerel state for timer registers
+static struct lpc_timer_t timer; ///< Mackerel state for timer registers
static timer_handler_fn timer_handler; ///< Expiry handler
/// Remaining value of current timeout, in timer ticks
LPC_DEBUG("timer0_set: programming %s timer for %u ticks\n",
periodic ? "periodic" : "one-shot", count);
*/
- struct LPC_timer_tcw_t tcw = {
+ struct lpc_timer_tcw_t tcw = {
.bcd = 0, // Binary mode (no BCD)
- .mode = periodic ? LPC_timer_rtgen : LPC_timer_oseoc, // Operating mode
- .rwsel = LPC_timer_lmsb, // First MSB, then LSB
- .select = LPC_timer_c0 // Select counter 0
+ .mode = periodic ? lpc_timer_rtgen : lpc_timer_oseoc, // Operating mode
+ .rwsel = lpc_timer_lmsb, // First MSB, then LSB
+ .select = lpc_timer_c0 // Select counter 0
};
// Prepare timer 0 to set its count
- LPC_timer_tcw_wr(&timer, tcw);
+ lpc_timer_tcw_wr(&timer, tcw);
if (count > 0) {
// Set the count/rate (LSB, then MSB)
- LPC_timer_cntacc0_wr(&timer, count & 0xff);
- LPC_timer_cntacc0_wr(&timer, count >> 8);
+ lpc_timer_cntacc0_wr(&timer, count & 0xff);
+ lpc_timer_cntacc0_wr(&timer, count >> 8);
}
}
static uint16_t timer0_read(void)
{
uint16_t val;
- LPC_timer_sbyte_fmt_t status;
+ lpc_timer_sbyte_fmt_t status;
do {
// 1. Issue read back command to read the status and count of the counter
- struct LPC_timer_rdbk_cmd_t cmd = {
+ struct lpc_timer_rdbk_cmd_t cmd = {
.c0 = 1, .c1 = 0, .c2 = 0, // select counter 0 only
.stat = 0, .count = 0 // latch both status and count
};
- LPC_timer_rdbk_cmd_wr(&timer, cmd);
+ lpc_timer_rdbk_cmd_wr(&timer, cmd);
// 2. Read status
- status = LPC_timer_sbyte_fmt0_rd(&timer);
+ status = lpc_timer_sbyte_fmt0_rd(&timer);
// 3. Read value latched value (LSB, then MSB)
// (we must do this even if the status shows an invalid count)
- val = LPC_timer_cntacc0_rd(&timer) << 8;
- val |= LPC_timer_cntacc0_rd(&timer);
+ val = lpc_timer_cntacc0_rd(&timer) << 8;
+ val |= lpc_timer_cntacc0_rd(&timer);
LPC_DEBUG("timer0_read:%s %u ticks remaining\n",
status.cnt_stat ? " null count read," : "", val);
{
LPC_DEBUG("timer_init: called\n");
- LPC_timer_initialize(&timer, TIMER_IOBASE);
+ lpc_timer_initialize(&timer, TIMER_IOBASE);
timer0_set(0, false);
timer_init_complete();
[ build application { target = "serial",
cFiles = [ "serial.c", "main.c"],
flounderBindings = [ "serial" ],
- mackerelDevices = [ "pc16550d_uart" ],
+ mackerelDevices = [ "pc16550d" ],
addLibraries = ["pci"]
}
]
#include <barrelfish/barrelfish.h>
#include <pci/pci.h>
#include "serial.h"
-#include "pc16550d_uart_dev.h"
+#include "pc16550d_dev.h"
-static struct PC16550D_UART_t uart;
+static struct pc16550d_t uart;
static uint16_t portbase;
static void serial_interrupt(void *arg)
{
- PC16550D_UART_iir_t iir = PC16550D_UART_iir_rd(&uart);
+ pc16550d_iir_t iir = pc16550d_iir_rd(&uart);
// Assert no error happened
- assert(PC16550D_UART_iir_iid_extract(iir) != PC16550D_UART_rls
- && PC16550D_UART_iir_iid_extract(iir) != PC16550D_UART_ms);
+ assert(pc16550d_iir_iid_extract(iir) != pc16550d_rls
+ && pc16550d_iir_iid_extract(iir) != pc16550d_ms);
// Read serial port just like with polling
serial_poll();
static void real_init(void)
{
// Initialize Mackerel with base port
- PC16550D_UART_initialize(&uart, portbase);
+ pc16550d_initialize(&uart, portbase);
// enable interrupt
- PC16550D_UART_ier_t ier = PC16550D_UART_ier_default;
- ier = PC16550D_UART_ier_erbfi_insert(ier, 1);
- PC16550D_UART_ier_wr(&uart, ier);
+ pc16550d_ier_t ier = pc16550d_ier_default;
+ ier = pc16550d_ier_erbfi_insert(ier, 1);
+ pc16550d_ier_wr(&uart, ier);
// enable FIFOs
- PC16550D_UART_fcr_t fcr = PC16550D_UART_fcr_default;
- fcr = PC16550D_UART_fcr_fifoe_insert(fcr, 1);
+ pc16550d_fcr_t fcr = pc16550d_fcr_default;
+ fcr = pc16550d_fcr_fifoe_insert(fcr, 1);
// FIFOs hold 14 bytes
- fcr = PC16550D_UART_fcr_rtrigger_insert(fcr, PC16550D_UART_bytes14);
- PC16550D_UART_fcr_wr(&uart, fcr);
+ fcr = pc16550d_fcr_rtrigger_insert(fcr, pc16550d_bytes14);
+ pc16550d_fcr_wr(&uart, fcr);
- PC16550D_UART_lcr_t lcr = PC16550D_UART_lcr_default;
- lcr = PC16550D_UART_lcr_wls_insert(lcr, PC16550D_UART_bits8); // 8 data bits
- lcr = PC16550D_UART_lcr_stb_insert(lcr, 1); // 1 stop bit
- lcr = PC16550D_UART_lcr_pen_insert(lcr, 0); // no parity
- PC16550D_UART_lcr_wr(&uart, lcr);
+ pc16550d_lcr_t lcr = pc16550d_lcr_default;
+ lcr = pc16550d_lcr_wls_insert(lcr, pc16550d_bits8); // 8 data bits
+ lcr = pc16550d_lcr_stb_insert(lcr, 1); // 1 stop bit
+ lcr = pc16550d_lcr_pen_insert(lcr, 0); // no parity
+ pc16550d_lcr_wr(&uart, lcr);
// set data terminal ready
- PC16550D_UART_mcr_t mcr = PC16550D_UART_mcr_default;
- mcr = PC16550D_UART_mcr_dtr_insert(mcr, 1);
- mcr = PC16550D_UART_mcr_out_insert(mcr, 2);
- PC16550D_UART_mcr_wr(&uart, mcr);
+ pc16550d_mcr_t mcr = pc16550d_mcr_default;
+ mcr = pc16550d_mcr_dtr_insert(mcr, 1);
+ mcr = pc16550d_mcr_out_insert(mcr, 2);
+ pc16550d_mcr_wr(&uart, mcr);
// Set baudrate (XXX: hard-coded to 115200)
- PC16550D_UART_lcr_dlab_wrf(&uart, 1);
- PC16550D_UART_dl_wr(&uart, PC16550D_UART_baud115200);
- PC16550D_UART_lcr_dlab_wrf(&uart, 0);
+ pc16550d_lcr_dlab_wrf(&uart, 1);
+ pc16550d_dl_wr(&uart, pc16550d_baud115200);
+ pc16550d_lcr_dlab_wrf(&uart, 0);
// offer service now we're up
start_service();
static void serial_putc(char c)
{
// Wait until FIFO can hold more characters
- while(!PC16550D_UART_lsr_thre_rdf(&uart));
+ while(!pc16550d_lsr_thre_rdf(&uart));
// Write character
- PC16550D_UART_thr_wr(&uart, c);
+ pc16550d_thr_wr(&uart, c);
}
void serial_write(char *c, size_t len)
void serial_poll(void)
{
// Read as many characters as possible from FIFO
- while(PC16550D_UART_lsr_dr_rdf(&uart)) {
- char c = PC16550D_UART_rbr_rd(&uart);
+ while(pc16550d_lsr_dr_rdf(&uart)) {
+ char c = pc16550d_rbr_rd(&uart);
serial_input(&c, 1);
}
}
#include "pci_debug.h"
#include "acpi_ec_dev.h"
-#define EC_CMD(c) (EC_cmd_t){ .cmd = c }
+#define EC_CMD(c) (acpi_ec_cmd_t){ .cmd = c }
struct ec {
ACPI_HANDLE handle; ///< Handle to EC object
ACPI_INTEGER uid; ///< UID of this EC object
bool use_glk; ///< Whether to use the ACPI global lock
- EC_t dev; ///< Mackerel device status
+ acpi_ec_t dev; ///< Mackerel device status
};
static ACPI_STATUS doread(struct ec *ec, uint8_t addr, uint8_t *data)
{
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
// send the read command
- EC_cmd_wr(&ec->dev, EC_CMD(EC_read));
+ acpi_ec_cmd_wr(&ec->dev, EC_CMD(acpi_ec_read));
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
// send the address
- EC_data_wr(&ec->dev, addr);
+ acpi_ec_data_wr(&ec->dev, addr);
// spinwait for output buffer full
- while (!EC_status_rd(&ec->dev).obf) ;
+ while (!acpi_ec_status_rd(&ec->dev).obf) ;
// read byte
- *data = EC_data_rd(&ec->dev);
+ *data = acpi_ec_data_rd(&ec->dev);
return AE_OK;
}
static ACPI_STATUS dowrite(struct ec *ec, uint8_t addr, uint8_t data)
{
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
// send the write command
- EC_cmd_wr(&ec->dev, EC_CMD(EC_write));
+ acpi_ec_cmd_wr(&ec->dev, EC_CMD(acpi_ec_write));
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
- EC_data_wr(&ec->dev, addr);
+ acpi_ec_data_wr(&ec->dev, addr);
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
// write byte
- EC_data_wr(&ec->dev, data);
+ acpi_ec_data_wr(&ec->dev, data);
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
return AE_OK;
}
ACPI_STATUS as;
/* check if an SCI is pending */
- if (EC_status_rd(&ec->dev).sci_evt) {
+ if (acpi_ec_status_rd(&ec->dev).sci_evt) {
// spinwait for input buffer empty
- while (EC_status_rd(&ec->dev).ibf) ;
+ while (acpi_ec_status_rd(&ec->dev).ibf) ;
// send query command
- EC_cmd_wr(&ec->dev, EC_CMD(EC_query));
+ acpi_ec_cmd_wr(&ec->dev, EC_CMD(acpi_ec_query));
// spinwait for output buffer full
- while (!EC_status_rd(&ec->dev).obf) ;
+ while (!acpi_ec_status_rd(&ec->dev).obf) ;
// read data
- uint8_t data = EC_data_rd(&ec->dev);
+ uint8_t data = acpi_ec_data_rd(&ec->dev);
printf("EC: GPE query %X\n", data);
}
// init mackerel state
- EC_initialize(&ec->dev, ioports[0], ioports[1]);
+ acpi_ec_initialize(&ec->dev, ioports[0], ioports[1]);
// register GPE handler
as = AcpiInstallGpeHandler(NULL, gpe, ACPI_GPE_EDGE_TRIGGERED, gpe_handler,
// init mackerel state
assert(ecdt->Control.SpaceId == ACPI_ADR_SPACE_SYSTEM_IO);
assert(ecdt->Data.SpaceId == ACPI_ADR_SPACE_SYSTEM_IO);
- EC_initialize(&ec->dev, ecdt->Data.Address, ecdt->Control.Address);
+ acpi_ec_initialize(&ec->dev, ecdt->Data.Address, ecdt->Control.Address);
// register GPE handler
as = AcpiInstallGpeHandler(NULL, ecdt->Gpe, ACPI_GPE_EDGE_TRIGGERED,
errval_t ioapic_init(struct ioapic *a, lvaddr_t base, uint8_t id,
uint32_t irqbase)
{
- LPC_IOAPIC_initialize(&a->dev, (void *)base);
+ lpc_ioapic_initialize(&a->dev, (void *)base);
a->irqbase = irqbase;
// Write I/O APIC ID
- LPC_IOAPIC_id_wr(&a->dev, (LPC_IOAPIC_id_t) { .id = id });
+ lpc_ioapic_id_wr(&a->dev, (lpc_ioapic_id_t) { .id = id });
// Check number of supported IRQs
- a->nintis = LPC_IOAPIC_ver_rd(&a->dev).mre + 1;
+ a->nintis = lpc_ioapic_ver_rd(&a->dev).mre + 1;
if (a->nintis == 1) {
PCI_DEBUG("Warning: I/O APIC claims only to support a single interrupt!"
" This is probably going to break...\n");
void ioapic_toggle_inti(struct ioapic *a, int inti, bool enable)
{
assert(inti >= 0 && inti < a->nintis);
- LPC_IOAPIC_redir_tbl_t tbl = LPC_IOAPIC_redirtbl_rd(&a->dev, inti);
+ lpc_ioapic_redir_tbl_t tbl = lpc_ioapic_redirtbl_rd(&a->dev, inti);
tbl.mask = enable ? 0 : 1;
- LPC_IOAPIC_redirtbl_wr(&a->dev, inti, tbl);
+ lpc_ioapic_redirtbl_wr(&a->dev, inti, tbl);
}
-void ioapic_setup_inti(struct ioapic *a, int inti, LPC_IOAPIC_redir_tbl_t entry)
+void ioapic_setup_inti(struct ioapic *a, int inti, lpc_ioapic_redir_tbl_t entry)
{
assert(inti >= 0 && inti < a->nintis);
- LPC_IOAPIC_redirtbl_wr(&a->dev, inti, entry);
+ lpc_ioapic_redirtbl_wr(&a->dev, inti, entry);
}
void ioapic_route_inti(struct ioapic *a, int inti, uint8_t vector, uint8_t dest)
{
assert(inti >= 0 && inti < a->nintis);
- LPC_IOAPIC_redir_tbl_t tbl = LPC_IOAPIC_redirtbl_rd(&a->dev, inti);
+ lpc_ioapic_redir_tbl_t tbl = lpc_ioapic_redirtbl_rd(&a->dev, inti);
tbl.vector = vector;
tbl.dest = dest;
- LPC_IOAPIC_redirtbl_wr(&a->dev, inti, tbl);
+ lpc_ioapic_redirtbl_wr(&a->dev, inti, tbl);
}
#ifndef LPC_IOAPIC_IOAPIC_H
#define LPC_IOAPIC_IOAPIC_H
-static inline uint32_t lpc_ioapic_ioapic_read_32(LPC_IOAPIC_t *dev,
+static inline uint32_t lpc_ioapic_ioapic_read_32(lpc_ioapic_t *dev,
size_t offset);
-static inline uint64_t lpc_ioapic_ioapic_read_64(LPC_IOAPIC_t *dev,
+static inline uint64_t lpc_ioapic_ioapic_read_64(lpc_ioapic_t *dev,
size_t offset);
-static inline void lpc_ioapic_ioapic_write_32(LPC_IOAPIC_t *dev, size_t offset,
+static inline void lpc_ioapic_ioapic_write_32(lpc_ioapic_t *dev, size_t offset,
uint32_t value);
-static inline void lpc_ioapic_ioapic_write_64(LPC_IOAPIC_t *dev, size_t offset,
+static inline void lpc_ioapic_ioapic_write_64(lpc_ioapic_t *dev, size_t offset,
uint64_t value);
#endif
projects / barrelfish / commitdiff