Non-working checkpoint
authorTimothy Roscoe <troscoe@inf.ethz.ch>
Fri, 17 Feb 2017 12:29:59 +0000 (13:29 +0100)
committerTimothy Roscoe <troscoe@inf.ethz.ch>
Fri, 17 Feb 2017 12:29:59 +0000 (13:29 +0100)
include/maps/cn88xx.h [new file with mode: 0644]
kernel/Hakefile
kernel/arch/armv8/plat_cn88xx.c [new file with mode: 0644]
platforms/Hakefile

diff --git a/include/maps/cn88xx.h b/include/maps/cn88xx.h
new file mode 100644 (file)
index 0000000..21f1eed
--- /dev/null
@@ -0,0 +1,67 @@
+/**
+ * \file
+ * \brief Physical address map for Cavium ThunderX CN88xx SoCs
+ */
+
+/*
+ * Copyright (c) 2017 ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+/* 
+ * See Cavium CN88xx Hardware Manual 2.55P, in particular Chapter 4
+ */
+
+#ifndef CN88XX_MAP_H
+#define CN88XX_MAP_H
+
+/*
+ * DRAM/L2 cached memory
+ */
+#define CN88XX_MAP_LMC_OFFSET  0x0000000000000000UL
+#define CN88XX_MAP_LMC_MASK    0x000000FFFFFFFFFFUL
+
+/*
+ * Converting a base address to a CCPI-node address
+ */
+#define CN88XX_MAP_LMC_CCPI_OFFSET(_ccpi,_a)                   \
+    (((_ccpi & 0x3) << 40) | ((_a) & CN88XX_MAP_LMC_MASK))
+#define CN88XX_MAP_IO_CCPI_OFFSET(_ccpi,_a) \
+    (((_ccpi & 0x3) << 44) | (_a))
+
+/*
+ * I/O spaces
+ */
+#define CN88XX_MAP_NCB_OFFSET   0x800000000000UL
+#define CN88XX_MAP_RSL_OFFSET   0x87E000000000UL
+#define CN88XX_MAP_AP_OFFSET    0x87F000000000UL
+#define CN88XX_MAP_SLI_OFFSET   0x880000000000UL
+
+/*
+ * Devices
+ */
+
+/*
+ * UARTs
+ */
+#define CN88XX_MAP_UART0_OFFSET 0x87E024000000UL
+#define CN88XX_MAP_UART0_MSIX   0x87E024F00000UL
+#define CN88XX_MAP_UART1_OFFSET 0x87E025000000UL
+#define CN88XX_MAP_UART1_MSIX   0x87E025F00000UL
+
+/*
+ * The GIC
+ */
+
+#define CN88XX_MAP_GIC_GICD_OFFFSET    0x801000000000UL
+#define CN88XX_MAP_GIC_GICD_SIZE       0x000000010000UL
+#define CN88XX_MAP_GIC_CCS_OFFSET      0x801000010000UL
+#define CN88XX_MAP_GIC_CCS_SIZE                0x000000010000UL
+#define CN88XX_MAP_GIC_GITS_OFFSET     0x801000020000UL 
+#define CN88XX_MAP_GIC_GICRX_OFFSET    0x801080000000UL
+
+#endif /* CN88XX_MAP_H */
index bd49d2f..fcead02 100644 (file)
@@ -556,7 +556,7 @@ let
         "arch/arm/irq.c"
     ],
     mackerelDevices = [
-        "arm",
+      "arm",
         "armv8",
         "arm_icp_pit",
         "gic_v3",
@@ -566,5 +566,50 @@ let
         "elf",
         "cpio"
     ]
-    }
+    },
+  
+  --
+  -- Cavium ThunderX CN88xx series SoC,
+  --
+  cpuDriver {
+     target = "cn88xx",
+     architectures = [ "armv8" ],
+     assemblyFiles = [
+        "arch/armv8/efiboot.S",
+        "arch/armv8/sysreg.S",
+        "arch/armv8/exceptions.S"
+     ],
+     cFiles = [
+         "arch/arm/misc.c",
+         "arch/arm/pl011.c",
+         "arch/arm/kputchar.c",
+         "arch/arm/gdb_arch.c",
+         "arch/armv8/plat_cn88xx.c",
+         "arch/armv8/init.c",
+         "arch/armv8/gdb_arch.c",
+         "arch/armv8/efiboot_init.c",
+         -----
+         "arch/armv8/kernel_multiboot2.c",
+         "arch/armv8/dispatch.c",
+         "arch/armv8/exec.c",
+         "arch/armv8/exn.c",
+         "arch/armv8/paging.c",
+         "arch/armv8/startup_arch.c",
+         "arch/armv8/syscall.c",
+         "arch/armv8/timers.c",
+         "arch/arm/debug.c",
+         "arch/arm/gic.c",
+         "arch/arm/irq.c"
+     ],
+     mackerelDevices = [
+        "arm",
+        "pl011_uart",
+        "pl130_gic",
+        "arm_icp_pit"
+     ],
+     addLibraries = [
+        "elf",
+        "cpio"
+    ]
+  }
   ]
diff --git a/kernel/arch/armv8/plat_cn88xx.c b/kernel/arch/armv8/plat_cn88xx.c
new file mode 100644 (file)
index 0000000..cfccdd6
--- /dev/null
@@ -0,0 +1,212 @@
+/**
+ * \file plat_arm_vm_consts.c
+ * \brief 
+ */
+
+
+/*
+ * Copyright (c) 2016 ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+#include <kernel.h>
+#include <maps/cn88xx.h>
+#include <offsets.h>
+#include <platform.h>
+#include <serial.h>
+#include <arch/arm/pl011.h>
+#include <arch/armv8/gic_v3.h>
+
+lpaddr_t phys_memory_start = CN88XX_MAP_LMC_OFFSET;
+
+/*
+ * ----------------------------------------------------------------------------
+ * GIC
+ * ----------------------------------------------------------------------------
+ */
+
+lpaddr_t platform_gic_cpu_base  = CN88XX_MAP_GIC_GICD;
+lpaddr_t platform_gic_dist_base = CN88XX_MAP_GIC_CCS;
+
+/*
+ * ----------------------------------------------------------------------------
+ * UART
+ * ----------------------------------------------------------------------------
+ */
+
+/* the maximum number of UARTS supported */
+#define MAX_NUM_UARTS 2
+
+/* the serial console port */
+unsigned int serial_console_port = 0;
+
+/* the debug console port */
+unsigned int serial_debug_port = 0;
+
+/* the number of physical ports */
+unsigned serial_num_physical_ports = 1;
+
+/* uart bases */
+const lpaddr_t
+uart_base[MAX_NUM_UARTS]= {
+    CN88XX_MAP_UART0_OFFSET,
+    CN88XX_MAP_UART1_OFFSET
+};
+
+/* uart sizes */
+const size_t
+uart_size[MAX_NUM_UARTS]= {
+    4096
+};
+
+
+errval_t serial_init(unsigned port, bool initialize_hw)
+{
+    lvaddr_t base = local_phys_to_mem(uart_base[port]);
+    pl011_init(port, base, initialize_hw);
+    return SYS_ERR_OK;
+};
+
+/*
+ * Return the address of the UART device.
+ */
+lpaddr_t platform_get_uart_address(unsigned port)
+{
+    return local_phys_to_mem(uart_base[port]);
+}
+
+/*
+ * Do any extra initialisation for this particular CPU (e.g. A9/A15).
+ */
+void platform_revision_init(void)
+{
+
+}
+
+/*
+ * Figure out how much RAM we have
+ */
+size_t platform_get_ram_size(void)
+{
+    return 0;
+}
+
+/*
+ * Boot secondary processors
+ */
+int platform_boot_aps(coreid_t core_id, genvaddr_t gen_entry)
+{
+    return 0;
+}
+
+void platform_notify_bsp(lpaddr_t *mailbox)
+{
+
+}
+
+
+/*
+ * Return the core count
+ */
+size_t platform_get_core_count(void)
+{
+    return 48;
+}
+
+/*
+ * Print system identification. MMU is NOT yet enabled.
+ */
+void platform_print_id(void)
+{
+    
+}
+
+/*
+ * Fill out provided `struct platform_info`
+ */
+void platform_get_info(struct platform_info *pi)
+{
+    pi->arch = PI_ARCH_ARMV8A;
+    pi->platform = PI_PLATFORM_FVP;
+}
+
+void armv8_get_info(struct arch_info_armv8 *ai)
+{
+
+}
+
+errval_t platform_gic_init(void) {
+    return gicv3_init();
+}
+
+errval_t platform_gic_cpu_interface_enable(void) {
+    return gicv3_cpu_interface_enable();
+}
+/**
+ * \file plat_a57mpcore.c
+ * \brief 
+ */
+
+
+/*
+ * Copyright (c) 2016 ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+/*
+ * The GIC registers are memory-mapped, with a physical base address specified by PERIPHBASE[43:18]. This input must be tied to a constant value. The PERIPHBASE value is sampled during reset into the Configuration Base Address Register (CBAR) for each processor in the MPCore device. See Configuration Base Address Register, EL1 and Configuration Base Address Register.
+ */
+
+#include <a57mpcore_map.h>
+#include <kernel.h>
+#include <platform.h>
+#include <paging_kernel_arch.h>
+
+static lpaddr_t periphbase = 0;
+
+/**
+ * @brief returns the private memory region
+ *
+ * @return physical address of the CBAR region
+ */
+lpaddr_t platform_get_private_region(void) {
+    if(periphbase == 0) return sysreg_read_cbar();
+    else                return periphbase;
+}
+
+/**
+ * @brief obtain the address of the GIC CPU interface
+ *
+ * @return physical address of the CBAR region
+ */
+lpaddr_t platform_get_gic_cpu_address(void) {
+    assert(paging_mmu_enabled());
+    return platform_gic_cpu_base;
+    }
+}
+
+/**
+ * @brief returns the size of the GIC cpu region
+ * @return
+ */
+size_t platform_get_gic_cpu_size(void) {
+    return CN88XX_MAP_GIC_CCS_SIZE;
+}
+
+lpaddr_t platform_get_distributor_address(void)
+{
+    return CN88XX_MAP_GIC_GICD_SIZE;
+}
+
+lpaddr_t platform_get_distributor_size(void)
+{
+    return CN88XX_MAP_GIC_GICD_OFFSET;
+}
index 261363d..28e0bbe 100644 (file)
@@ -490,6 +490,15 @@ let bin_rcce_lu = [ "/sbin/" ++ f | f <- [
     )
     "The APM XGene development board (Mustang)",
 
+    platform "ThunderX" [ "armv8" ]
+    ([ ("armv8", "/sbin/cpu_cn88xx") ]
+       ++
+       [ ("armv8", f) | f <- armv8_modules ]
+       ++
+       [ ("",       f) | f <- modules_generic]
+    )
+    "Cavium ThunderX-1 (CN88xx) boards",
+
     platform "PandaboardES" [ "armv7" ]
     ([ ("armv7", f) | f <- pandaModules ] ++
      [ ("root", "/armv7_omap44xx_image"),