"megaraid",
"vtd",
"vtd_iotlb",
- "zynq7000/zynq_uart",
- "zynq7000/zynq_slcr"
+ "zynq7/zynq_uart",
+ "zynq7/zynq_slcr"
], arch <- allArchitectures
] ++
};
register UART_CLK_CTRL addr(base, 0x154) "UART Reference Clock Control" {
- _ 18 rw;
+ _ 18;
DIVISOR 6 rw "Divisor for UART controller source clock";
- _ 2 rw;
+ _ 2;
SRCSEL 2 rw type(clksrc) "PLL whence the clock is sourced";
- _ 2 rw;
+ _ 2;
CLKACT1 1 rw "UART1 reference clock control";
CLKACT0 1 rw "UART0 reference clock control";
};
register UART_RST_CTRL addr(base, 0x228) "UART Software Reset Control" {
- _ 28 rw;
+ _ 28;
UART1_REF_RST 1 rw "UART1 soft reset";
UART0_REF_RST 1 rw "UART0 soft reset";
UART1_CPU1X_RST 1 rw "UART1 AMBA reset";
SUBFAMILY 4 ro "Subfamily code";
DEVICE_CODE 5 ro "Device code";
MANUFACTURED_ID 11 ro "Manufacturer ID";
- _ 1 ro;
+ _ 1;
};
constants mio_iotype "MIO Pin IO Standard" {
/* These registers control multiplexing on the MIO pins, which are not
* routed via the FPGA. */
regarray MIO_PIN addr(base, 0x700) [ 54 ] "MIO Pin Control" {
- _ 18 rsvd;
+ _ 18;
DisableRcvr 1 rw type(en_lo) "Disable HSTL input buffer when output-only";
PULLUP 1 rw "Enable pullup";
IO_Type 3 rw type(mio_iotype) "IO buffer type";
};
register MIO_LOOPBACK addr(base, 0x804) "MIO Pin Loopback" {
- _ 28 rw;
+ _ 28;
I2C0_LOOP_I2C1 1 rw "Loop I2C0 to I2C1";
CAN0_LOOP_CAN1 1 rw "Loop CAN0 to CAN1";
UA0_LOOP_UA1 1 rw "Loop UART0 to UART1";
};
register MIO_MST_TRI1 addr(base, 0x810) "MIO pin tri-state enables, 53:32" {
- _ 10 rsvd;
+ _ 10;
PIN_53_TRI 1 rw "Master tri-state for pin 53";
PIN_52_TRI 1 rw "Master tri-state for pin 52";
PIN_51_TRI 1 rw "Master tri-state for pin 51";
};
register CR addr (base, 0x0) "UART Control" {
- _ 23 rw;
+ _ 23;
stopbrk 1 rw "Stop transmitting break";
startbrk 1 rw "Start transmitting break";
torst 1 rw "Restart receiver timeout counter";
};
register MR addr (base, 0x4) "UART Mode" {
- _ 20 rw;
- _ 1 rsvd;
- _ 1 rsvd;
+ _ 20;
+ _ 1;
+ _ 1;
chmode 2 rw type(chmode) "Channel mode";
nbstop 2 rw type(stopbits) "Number of stop bits";
par 3 rw type(parity) "Parity type";
};
register IER addr (base, 0x8) "Interrupt Enable" {
- _ 19 rw;
+ _ 19;
tovr 1 wo "Transmitter FIFO overflow";
tnful 1 wo "Transmitter FIFO nearly full";
ttrig 1 wo "Transmitter FIFO trigger";
};
register IDR addr (base, 0xC) "Interrupt Disable" {
- _ 19 rw;
+ _ 19;
tovr 1 wo "Transmitter FIFO overflow";
tnful 1 wo "Transmitter FIFO nearly full";
ttrig 1 wo "Transmitter FIFO trigger";
};
register IMR addr (base, 0x10) "Interrupt Mask" {
- _ 19 ro;
+ _ 19;
tovr 1 ro "Transmitter FIFO overflow";
tnful 1 ro "Transmitter FIFO nearly full";
ttrig 1 ro "Transmitter FIFO trigger";
};
register ISR addr (base, 0x14) "Channel Interrupt Status" {
- _ 19 ro;
+ _ 19;
tovr 1 rw1c "Transmitter FIFO overflow";
tnful 1 rw1c "Transmitter FIFO nearly full";
ttrig 1 rw1c "Transmitter FIFO trigger";
};
register BAUDGEN addr (base, 0x18) "Baud Rate Generator" {
- _ 16 rw;
+ _ 16;
CD 16 rw "Baud rate clock divisor value";
};
register RXTOUT addr (base, 0x1C) "Receiver Timeout" {
- _ 24 rw;
+ _ 24;
RTO 8 rw "Receiver timeout value";
};
register RXWM addr (base, 0x20) "Receiver FIFO Trigger Level" {
- _ 26 rw;
+ _ 26;
RTRIG 6 rw "Receiver FIFO trigger level";
};
register MODEMCR addr (base, 0x24) "Modem Control" {
- _ 26 rw;
+ _ 26;
FCM 1 rw type(en_hi) "Automatic flow control";
- _ 3 rw;
+ _ 3;
RTS 1 rw type(en_lo) "Request to send software control";
DTR 1 rw type(en_lo) "Data terminal ready";
};
register MODEMSR addr (base, 0x28) "Modem Status" {
- _ 23 rw;
+ _ 23;
FCMS 1 rw type(en_hi) "Flow control mode";
DCD 1 ro type(en_lo) "Data carrier detect";
RI 1 ro type(en_lo) "Ring indicator";
};
register SR addr (base, 0x2C) "Channel Status" {
- _ 17 rw;
+ _ 17;
TNFUL 1 ro "Transmitter FIFO nearly full";
TTRIG 1 ro "Transmitter FIFO >= TTRIG";
FDELT 1 ro "Receiver FIFO >= FDEL";
TACTIVE 1 ro "Transmitter active";
RACTIVE 1 ro "Recevier active";
- _ 1 rsvd;
- _ 1 rsvd;
- _ 1 rsvd;
- _ 1 rsvd;
- _ 1 rsvd;
+ _ 1;
+ _ 1;
+ _ 1;
+ _ 1;
+ _ 1;
TXFULL 1 ro "Transmitter FIFO full";
TXEMPTY 1 ro "Transmitter FIFO empty";
RXFULL 1 ro "Receiver FIFO full";
};
register FIFO addr (base, 0x30) "Transmit and Receive FIFO" {
- _ 24 rw;
+ _ 24;
FIFO 8 rw;
};
register BDIV addr (base, 0x34) "Baud Rate Divider" {
- _ 24 rw;
+ _ 24;
BDIV 8 rw "Baud rate divider value";
};
register FDEL addr (base, 0x38) "Flow Control Delay" {
- _ 26 rw;
+ _ 26;
BDIV 6 rw "RxFIFO trigger level for RTS deassertion";
};
register TTRIG addr (base, 0x44) "Transmitter FIFO Trigger Level" {
- _ 26 rw;
+ _ 26;
TTRIG 6 rw "Transmitter FIFO Trigger Level";
};
};
Str "-D__ARM_CORTEX__",
Str "-D__ARM_ARCH_7A__",
Str "-Wno-unused-but-set-variable",
+ Str "-Wno-suggest-attribute=noreturn",
Str "-Wno-format"
]
--- /dev/null
+timeout 0
+
+#
+# This script is used to describe the commands to start at
+# boot-time and the arguments they should receive.
+#
+# Kernel arguments are not read from this script. On QEMU they can be
+# set using 'qemu-system-arm -append ...'.
+
+title Barrelfish
+kernel /armv7/sbin/cpu_zynq7 loglevel=4
+module /armv7/sbin/cpu_zynq7
+module /armv7/sbin/init
+
+# Domains spawned by init
+module /armv7/sbin/mem_serv
+module /armv7/sbin/monitor
+
+# Special boot time domains spawned by monitor
+module /armv7/sbin/ramfsd boot
+module /armv7/sbin/skb boot
+module /armv7/sbin/spawnd boot
+module /armv7/sbin/startd boot
+
+# General user domains
+#module /armv7/sbin/serial
+#module /armv7/sbin/fish
+
+module /armv7/sbin/memtest
+
+# start size id
+mmap map 0x00000000 0x40000000 1
// armv7 platforms
PI_PLATFORM_OMAP44XX,
PI_PLATFORM_VEXPRESS,
+ PI_PLATFORM_ZYNQ7,
// armv8 platforms
};
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* Copyright (c) 2016, ETH Zurich.
+* All rights reserved.
+*
+* This file is distributed under the terms in the attached LICENSE file.
+* If you do not find this file, copies can be found by writing to:
+* ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
+*
+*****************************************************************************
+*
+* @file zynq7000_map.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core in the Zynq7000-series SoCs.
+*
+* Derived from lib/bsp/standalone/src/cortexa9/xparameters_ps.h in the Xilinx
+* 'embeddedsw' package.
+*
+******************************************************************************/
+
+#ifndef _ZYNQ7000_MAP_H_
+#define _ZYNQ7000_MAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define ZYNQ7_DDR_MEM_BASEADDR 0x00000000U
+#define ZYNQ7_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for SLCR */
+#define ZINQ7_XSLCR_NUM_INSTANCES 1U
+#define ZINQ7_XSLCR_0_DEVICE_ID 0U
+#define ZINQ7_XSLCR_0_BASEADDR ZINQ7_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define ZINQ7_SCUGIC_NUM_INSTANCES 1U
+#define ZINQ7_SCUGIC_SINGLE_DEVICE_ID 0U
+#define ZINQ7_SCUGIC_CPU_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00000100U)
+#define ZINQ7_SCUGIC_DIST_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00001000U)
+#define ZINQ7_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define ZINQ7_GLOBAL_TMR_NUM_INSTANCES 1U
+#define ZINQ7_GLOBAL_TMR_DEVICE_ID 0U
+#define ZINQ7_GLOBAL_TMR_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00000200U)
+#define ZINQ7_GLOBAL_TMR_INTR ZINQ7_GLOBAL_TMR_INT_ID
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define ZINQ7_PERIPHERAL_BASEADDR 0xE0000000U
+#define ZINQ7_UART0_BASEADDR 0xE0000000U
+#define ZINQ7_UART1_BASEADDR 0xE0001000U
+#define ZINQ7_USB0_BASEADDR 0xE0002000U
+#define ZINQ7_USB1_BASEADDR 0xE0003000U
+#define ZINQ7_I2C0_BASEADDR 0xE0004000U
+#define ZINQ7_I2C1_BASEADDR 0xE0005000U
+#define ZINQ7_SPI0_BASEADDR 0xE0006000U
+#define ZINQ7_SPI1_BASEADDR 0xE0007000U
+#define ZINQ7_CAN0_BASEADDR 0xE0008000U
+#define ZINQ7_CAN1_BASEADDR 0xE0009000U
+#define ZINQ7_GPIO_BASEADDR 0xE000A000U
+#define ZINQ7_GEM0_BASEADDR 0xE000B000U
+#define ZINQ7_GEM1_BASEADDR 0xE000C000U
+#define ZINQ7_QSPI_BASEADDR 0xE000D000U
+#define ZINQ7_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define ZINQ7_SDIO0_BASEADDR 0xE0100000U
+#define ZINQ7_SDIO1_BASEADDR 0xE0101000U
+#define ZINQ7_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define ZINQ7_NAND_BASEADDR 0xE1000000U
+#define ZINQ7_PARPORT0_BASEADDR 0xE2000000U
+#define ZINQ7_PARPORT1_BASEADDR 0xE4000000U
+#define ZINQ7_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define ZINQ7_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define ZINQ7_TTC0_BASEADDR 0xF8001000U
+#define ZINQ7_TTC1_BASEADDR 0xF8002000U
+#define ZINQ7_DMAC0_SEC_BASEADDR 0xF8003000U
+#define ZINQ7_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define ZINQ7_WDT_BASEADDR 0xF8005000U
+#define ZINQ7_DDR_CTRL_BASEADDR 0xF8006000U
+#define ZINQ7_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define ZINQ7_AFI0_BASEADDR 0xF8008000U
+#define ZINQ7_AFI1_BASEADDR 0xF8009000U
+#define ZINQ7_AFI2_BASEADDR 0xF800A000U
+#define ZINQ7_AFI3_BASEADDR 0xF800B000U
+#define ZINQ7_OCM_BASEADDR 0xF800C000U
+#define ZINQ7_EFUSE_BASEADDR 0xF800D000U
+#define ZINQ7_CORESIGHT_BASEADDR 0xF8800000U
+#define ZINQ7_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define ZINQ7_SCU_PERIPH_BASE 0xF8F00000U
+#define ZINQ7_L2CC_BASEADDR 0xF8F02000U
+#define ZINQ7_SAM_RAM_BASEADDR 0xFFFC0000U
+#define ZINQ7_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define ZINQ7_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define ZINQ7_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define ZINQ7_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define ZINQ7_CORE_PARITY0_INT_ID 32U
+#define ZINQ7_CORE_PARITY1_INT_ID 33U
+#define ZINQ7_L2CC_INT_ID 34U
+#define ZINQ7_OCMINTR_INT_ID 35U
+#define ZINQ7_ECC_INT_ID 36U
+#define ZINQ7_PMU0_INT_ID 37U
+#define ZINQ7_PMU1_INT_ID 38U
+#define ZINQ7_SYSMON_INT_ID 39U
+#define ZINQ7_DVC_INT_ID 40U
+#define ZINQ7_WDT_INT_ID 41U
+#define ZINQ7_TTC0_0_INT_ID 42U
+#define ZINQ7_TTC0_1_INT_ID 43U
+#define ZINQ7_TTC0_2_INT_ID 44U
+#define ZINQ7_DMA0_ABORT_INT_ID 45U
+#define ZINQ7_DMA0_INT_ID 46U
+#define ZINQ7_DMA1_INT_ID 47U
+#define ZINQ7_DMA2_INT_ID 48U
+#define ZINQ7_DMA3_INT_ID 49U
+#define ZINQ7_SMC_INT_ID 50U
+#define ZINQ7_QSPI_INT_ID 51U
+#define ZINQ7_GPIO_INT_ID 52U
+#define ZINQ7_USB0_INT_ID 53U
+#define ZINQ7_GEM0_INT_ID 54U
+#define ZINQ7_GEM0_WAKE_INT_ID 55U
+#define ZINQ7_SDIO0_INT_ID 56U
+#define ZINQ7_I2C0_INT_ID 57U
+#define ZINQ7_SPI0_INT_ID 58U
+#define ZINQ7_UART0_INT_ID 59U
+#define ZINQ7_CAN0_INT_ID 60U
+#define ZINQ7_FPGA0_INT_ID 61U
+#define ZINQ7_FPGA1_INT_ID 62U
+#define ZINQ7_FPGA2_INT_ID 63U
+#define ZINQ7_FPGA3_INT_ID 64U
+#define ZINQ7_FPGA4_INT_ID 65U
+#define ZINQ7_FPGA5_INT_ID 66U
+#define ZINQ7_FPGA6_INT_ID 67U
+#define ZINQ7_FPGA7_INT_ID 68U
+#define ZINQ7_TTC1_0_INT_ID 69U
+#define ZINQ7_TTC1_1_INT_ID 70U
+#define ZINQ7_TTC1_2_INT_ID 71U
+#define ZINQ7_DMA4_INT_ID 72U
+#define ZINQ7_DMA5_INT_ID 73U
+#define ZINQ7_DMA6_INT_ID 74U
+#define ZINQ7_DMA7_INT_ID 75U
+#define ZINQ7_USB1_INT_ID 76U
+#define ZINQ7_GEM1_INT_ID 77U
+#define ZINQ7_GEM1_WAKE_INT_ID 78U
+#define ZINQ7_SDIO1_INT_ID 79U
+#define ZINQ7_I2C1_INT_ID 80U
+#define ZINQ7_SPI1_INT_ID 81U
+#define ZINQ7_UART1_INT_ID 82U
+#define ZINQ7_CAN1_INT_ID 83U
+#define ZINQ7_FPGA8_INT_ID 84U
+#define ZINQ7_FPGA9_INT_ID 85U
+#define ZINQ7_FPGA10_INT_ID 86U
+#define ZINQ7_FPGA11_INT_ID 87U
+#define ZINQ7_FPGA12_INT_ID 88U
+#define ZINQ7_FPGA13_INT_ID 89U
+#define ZINQ7_FPGA14_INT_ID 90U
+#define ZINQ7_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define ZINQ7_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define ZINQ7_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define ZINQ7_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define ZINQ7_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define ZINQ7_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+#define ZINQ7_SCUTIMER_DEVICE_ID 0U
+#define ZINQ7_SCUWDT_DEVICE_ID 0U
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ZYNQ7000_MAP_H_ */
--------------------------------------------------------------------------
--- Copyright (c) 2007-2015, ETH Zurich.
+-- Copyright (c) 2007-2016, ETH Zurich.
-- Copyright (c) 2015, Hewlett Packard Enterprise Development LP.
-- All rights reserved.
--
],
addLibraries = [ "elf", "cpio" ]
},
+ --
+ -- Xilinx Zynq7000-series dual-core Cortex-A9 SoC
+ --
+ cpuDriver {
+ target = "zynq7",
+ architectures = [ "armv7" ],
+ assemblyFiles = [ "arch/armv7/boot.S",
+ "arch/armv7/cp15.S",
+ "arch/armv7/exceptions.S" ],
+ cFiles = [
+ "arch/armv7/a9_gt.c",
+ "arch/armv7/a9_scu.c",
+ "arch/armv7/kludges.c",
+ "arch/armv7/init.c",
+ "arch/armv7/paging.c",
+ "arch/armv7/plat_a9mpcore.c",
+ "arch/armv7/plat_priv_cbar.c",
+ "arch/armv7/plat_zynq7.c",
+ "arch/armv7/startup_arch.c",
+ "arch/armv7/syscall.c",
+ "arch/arm/dispatch.c",
+ "arch/arm/exec.c",
+ "arch/arm/exn.c",
+ "arch/arm/gic.c",
+ "arch/arm/irq.c",
+ "arch/arm/kputchar.c",
+ "arch/arm/misc.c",
+ "arch/arm/multiboot.c",
+ "arch/arm/zynq_uart.c"
+ ],
+ mackerelDevices = [ "arm",
+ "cpuid_arm",
+ "pl130_gic",
+ "cortex_a9_pit",
+ "cortex_a9_gt",
+ "cortex_a9_scu",
+ "zynq7/zynq_uart",
+ "zynq7/zynq_slcr"
+ ],
+ addLibraries = [ "elf", "cpio" ]
+ },
--
-- Applied Micro APM88xxxx series SoC,
--- /dev/null
+/**
+ * \file
+ * \brief Kernel serial driver for the Xilinx Zynq7000-series UART
+ */
+
+/*
+ * Copyright (c) 2016, ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+#include <kernel.h>
+
+#include <arm.h>
+#include <dev/zynq7/zynq_uart_dev.h>
+#include <paging_kernel_arch.h>
+#include <zynq_uart.h>
+#include <zynq7_map.h>
+
+/* Serial console and debugger interfaces. */
+static zynq_uart_t ports[ZYNQ_UART_MAX_PORTS];
+static lpaddr_t port_addrs[ZYNQ_UART_MAX_PORTS];
+static bool port_inited[ZYNQ_UART_MAX_PORTS];
+
+static void zynq_uart_hw_init(zynq_uart_t *uart);
+
+#define MSG(port, format, ...) \
+ printk( LOG_NOTE, "ZYNQ serial[%d]: "format, port, ## __VA_ARGS__ )
+
+void
+zynq_uart_early_init(unsigned port, lpaddr_t base) {
+ assert(port < ZYNQ_UART_MAX_PORTS);
+ assert(ports[port].base == 0);
+
+ port_addrs[port] = base;
+ zynq_uart_initialize(&ports[port], (mackerel_addr_t)base);
+}
+
+void
+zynq_uart_init(unsigned port, bool initialize_hw) {
+ assert(port < ZYNQ_UART_MAX_PORTS);
+ /* Ensure port has already been through early_init. */
+ assert(port_addrs[port] != 0);
+
+ /* All devices seem to be 4k-aligned, which is nice. */
+ lvaddr_t base = paging_map_device(port_addrs[port], 0x1000);
+
+ MSG(port, "base = 0x%"PRIxLVADDR"\n", base);
+ zynq_uart_initialize(&ports[port], (mackerel_addr_t) base);
+ if(initialize_hw && !port_inited[port]) {
+ zynq_uart_hw_init(&ports[port]);
+ port_inited[port] = true;
+ }
+ MSG(port,"done.\n");
+}
+
+/*
+ * Initialise Zynq UART
+ * Zynq TRM S19.3.1
+ */
+static void
+zynq_uart_hw_init(zynq_uart_t *uart) {
+ panic("Unimplemented\n");
+}
+
+/**
+ * \brief Prints a single character to a serial port.
+ */
+void
+zynq_uart_putchar(unsigned port, char c) {
+ assert(port <= ZYNQ_UART_MAX_PORTS);
+ zynq_uart_t *uart = &ports[port];
+
+ /* Wait until FIFO can hold more characters. */
+ while(zynq_uart_SR_TXFULL_rdf(uart));
+
+ /* Write character. */
+ zynq_uart_FIFO_FIFO_wrf(uart, c);
+}
+
+/**
+ * \brief Reads a single character from the default serial port.
+ * This function spins waiting for a character to arrive.
+ */
+char
+zynq_uart_getchar(unsigned port) {
+ assert(port <= ZYNQ_UART_MAX_PORTS);
+ zynq_uart_t *uart = &ports[port];
+
+ /* Wait until there is at least one character in the FIFO. */
+ while(zynq_uart_SR_RXEMPTY_rdf(uart));
+
+ /* Return the character. */
+ return zynq_uart_FIFO_FIFO_rdf(uart);
+}
--- /dev/null
+/**
+ * \file
+ * \brief Platform code for the Xilinx Zynq7000-series SoCs
+ */
+
+/*
+ * Copyright (c) 2016 ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+#include <kernel.h>
+
+#include <a9_gt.h>
+#include <a9_scu.h>
+#include <a9mpcore_map.h>
+#include <assert.h>
+#include <cp15.h>
+#include <dev/cortex_a9_pit_dev.h>
+#include <errors/errno.h>
+#include <gic.h>
+#include <global.h>
+#include <init.h>
+#include <paging_kernel_arch.h>
+#include <platform.h>
+#include <serial.h>
+#include <zynq7_map.h>
+#include <zynq_uart.h>
+
+#define MSG(format, ...) printk( LOG_NOTE, "ZYNQ7: "format, ## __VA_ARGS__ )
+
+/*****************************************************************************
+ *
+ * Implementation of serial.h
+ *
+ *****************************************************************************/
+
+unsigned int serial_console_port = 1;
+unsigned int serial_debug_port = 1;
+unsigned int serial_num_physical_ports = 2;
+
+static lpaddr_t
+zynq_port_addrs[ZYNQ_UART_MAX_PORTS]= {
+ ZINQ7_UART0_BASEADDR,
+ ZINQ7_UART1_BASEADDR
+};
+
+/*
+ * Initialize the serial ports
+ */
+errval_t
+serial_early_init(unsigned port) {
+ spinlock_init(&global->locks.print);
+ zynq_uart_early_init(port, zynq_port_addrs[port]);
+ return SYS_ERR_OK;
+}
+
+errval_t
+serial_init(unsigned port, bool initialize_hw) {
+ assert(port < serial_num_physical_ports);
+ assert(mmu_is_enabled());
+ zynq_uart_init(port, initialize_hw);
+ return SYS_ERR_OK;
+};
+
+void
+serial_putchar(unsigned port, char c) {
+ assert(port < serial_num_physical_ports);
+ zynq_uart_putchar(port, c);
+}
+
+char
+serial_getchar(unsigned port) {
+ assert(port < serial_num_physical_ports);
+ return zynq_uart_getchar(port);
+}
+
+/*
+ * Print system identification. MMU is NOT yet enabled.
+ */
+void
+platform_print_id(void) {
+ panic("Unimplemented.\n");
+}
+
+void
+platform_get_info(struct platform_info *pi) {
+ pi->arch = PI_ARCH_ARMV7A;
+ pi->platform = PI_PLATFORM_ZYNQ7;
+}
+
+/* The zc706 has 2GB of RAM beginning at address 0. */
+size_t
+platform_get_ram_size(void) {
+ return (ZYNQ7_DDR_MEM_HIGHADDR - ZYNQ7_DDR_MEM_BASEADDR) + 1;
+}
+
+/**
+ * Notify the BSP that this AP has booted.
+ */
+
+/**
+ * \brief Boot an arm app core
+ *
+ * \param core_id ID of the core to try booting
+ * \param entry Entry address for new kernel in the destination
+ * architecture's lvaddr_t
+ *
+ * \returns Zero on successful boot, non-zero (error code) on failure
+ */
+int
+platform_boot_aps(coreid_t core_id, genvaddr_t gen_entry) {
+ panic("Unimplemented.\n");
+ return 0;
+}
+
+void
+platform_notify_bsp(void) {
+ panic("Unimplemented.\n");
+}
+
+uint32_t tsc_hz = 0;
+uint32_t sys_clk;
+
+void
+a9_probe_tsc(void) {
+ panic("Unimplemented.\n");
+}
--- /dev/null
+/*
+ * Copyright (c) 2016, ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+#ifndef __ZYNQ_UART_H__
+#define __ZYNQ_UART_H__
+
+#include <barrelfish_kpi/types.h>
+#include <stdbool.h>
+
+#define ZYNQ_UART_MAX_PORTS 2
+
+/*
+ * \brief Configure a port.
+ *
+ * This happens at system startup, and before the MMU is turned on.
+ * The hardware is not initialized by this call.
+ * After this, the UART is (hopefully) usable, but after the MMU is
+ * enabled the OS should then call zynq_uart_init below.
+ */
+extern void zynq_uart_early_init(unsigned port, lpaddr_t addr);
+
+/*
+ * \brief Initialize a UART, and a number to refer to it in the
+ * future.
+ *
+ * \param port : Physical address of the UART.
+ * \param hwinit : Also init the hardware itself if True
+ */
+extern void zynq_uart_init(unsigned port, bool hwinit);
+
+/*
+ * \brief Put a character to the port
+ */
+extern void zynq_uart_putchar(unsigned port, char c);
+
+/*
+ * \brief Read a character from a port
+ */
+extern char zynq_uart_getchar(unsigned port);
+
+#endif // __ZYNQ_UART_H__
"memtest"
] ]
+ -- ARMv7-A modules for the Xilinx Zynq7000
+ zynq7Modules = [ "/sbin/" ++ f | f <- [
+ "cpu_zynq7",
+ "init",
+ "mem_serv",
+ "monitor",
+ "ramfsd",
+ "spawnd",
+ "startd",
+ "corectrl",
+ "skb",
+ "memtest"
+ ] ]
+
-- ARMv8 modules for running under GEM5
armv8_gem5Modules = [ "/sbin/" ++ f | f <- [
"cpu_gem5",
[ ("root", "/arm_a9ve_image") ])
"VersatileExpress EMM board for ARMv7-A Fixed Virtual Platforms",
+ platform "Zynq7000" [ "armv7" ]
+ ([ ("armv7", f) | f <- zynq7Modules ] ++
+ [ ("root", "/arm_zynq7_image") ])
+ "Xilinx Zynq7000",
+
platform "Mustang" [ "armv8" ]
([ ("armv8", "/sbin/cpu_apm88xxxx") ])
"The APM XGene development board (Mustang)",
Dep BuildTree "tools" "/bin/arm_molly"
] ++ [ (Dep BuildTree "armv7" m) | m <- vExpressEMMModules_A9 ]),
+ -- Build the Zynq7000 image
+ Rule ([ In SrcTree "tools" "/tools/arm_molly/build_molly_image.sh",
+ Str "--srcdir", NoDep SrcTree "root" "/.",
+ Str "--builddir", NoDep BuildTree "root" "/.",
+ Str "--arch armv7-a",
+ Str "--menu", In BuildTree "root"
+ "/platforms/arm/menu.lst.zynq7",
+ Str "--baseaddr", Str "0x0",
+ Str "--image", Out "root" "/arm_zynq7_image",
+ Str "--gcc", Str Config.arm_cc,
+ Str "--objcopy", Str Config.arm_objcopy,
+ Dep BuildTree "tools" "/bin/arm_molly"
+ ] ++ [ (Dep BuildTree "armv7" m) | m <- zynq7Modules ]),
+
-- Build the ARMv8 GEM5 simulation image
Rule ([ In SrcTree "tools" "/tools/arm_molly/build_molly_image.sh",
Str "--srcdir", NoDep SrcTree "root" "/.",
| p <- [ "armv8_gem5",
"arm_a15ve",
"pandaboard",
- "arm_a9ve" ]],
+ "arm_a9ve",
+ "zynq7" ]],
Rules [ copyFile SrcTree "root" ("/hake/menu.lst." ++ p)
"root" ("/platforms/x86/menu.lst." ++ p)
| p <- [ "x86_32", "x86_64", "k1om" ] ],
projects / barrelfish / commitdiff