armv8: Start with all interrupts disabled
authorLukas Humbel <lukas.humbel@inf.ethz.ch>
Thu, 7 Nov 2019 14:21:16 +0000 (15:21 +0100)
committerLukas Humbel <lukas.humbel@inf.ethz.ch>
Thu, 7 Nov 2019 14:49:13 +0000 (15:49 +0100)
Signed-off-by: Lukas Humbel <lukas.humbel@inf.ethz.ch>

16 files changed:
kernel/arch/arm/gic_v3.c
kernel/arch/arm/lpuart.c
kernel/arch/armv7/plat_a15mpcore.c
kernel/arch/armv7/plat_a9mpcore.c
kernel/arch/armv8/boot/boot_generic.c
kernel/arch/armv8/exn.c
kernel/arch/armv8/plat_apm88xxxx.c
kernel/arch/armv8/plat_arm_vm.c
kernel/arch/armv8/plat_arm_vm_consts.c
kernel/arch/armv8/plat_cn88xx.c
kernel/arch/armv8/plat_imx8x.c
kernel/arch/armv8/plat_qemu.c
kernel/arch/armv8/plat_rpi3.c
kernel/arch/armv8/plat_tmas.c [deleted file]
kernel/arch/armv8/timers.c
kernel/include/arch/arm/platform.h

index 130f4f9..cb08ac1 100644 (file)
@@ -68,8 +68,8 @@ void gic_init(void)
     for (int i = 0; i * 32 < itlines; i++) {
         // Clear
         gic_v3_dist_GICD_ICACTIVER_wr(&gic_v3_dist_dev, i, MASK_32);
-        // Enable
-        gic_v3_dist_GICD_ISENABLER_wr(&gic_v3_dist_dev, i, MASK_32);
+        // Disable all interrupts
+        gic_v3_dist_GICD_ICENABLER_wr(&gic_v3_dist_dev, i, MASK_32);
         // And put in group 1
         gic_v3_dist_GICD_IGROUPR_rawwr(&gic_v3_dist_dev, i, MASK_32);
     }
@@ -150,7 +150,8 @@ void gic_cpu_interface_enable(void)
     printf("%s: GICR_TYPER: affinity:%x  cpu_no:%x\n", __func__, gic_v3_redist_GICR_TYPER_Affinity_Value_extract(gicr_typer), gic_v3_redist_GICR_TYPER_Processor_Number_extract(gicr_typer));
 
     gic_v3_redist_GICR_ICACTIVER0_rawwr(&gic_v3_redist_dev, MASK_32);
-    gic_v3_redist_GICR_ISENABLER0_rawwr(&gic_v3_redist_dev, MASK_32);
+    //Disable PPIs
+    gic_v3_redist_GICR_ICENABLER0_wr(&gic_v3_redist_dev, MASK_32);
 
     gic_v3_redist_GICR_IGROUPR0_rawwr(&gic_v3_redist_dev, MASK_32);
     gic_v3_redist_GICR_IGRPMODR0_rawwr(&gic_v3_redist_dev, 0);
@@ -175,6 +176,13 @@ void gic_cpu_interface_enable(void)
 errval_t platform_enable_interrupt(uint32_t int_id, uint16_t prio,
                           bool edge_triggered, bool one_to_n)
 {
+    if(int_id<32) {
+        gic_v3_redist_GICR_ISENABLER0_wr(&gic_v3_redist_dev, 1<<int_id );
+    }
+    else {  
+        gic_v3_dist_GICD_ISENABLER_wr(&gic_v3_dist_dev, int_id/32,
+            1<<(int_id % 32));
+    }
     return SYS_ERR_OK;
 }
 
index 77fddb8..8e13f99 100644 (file)
@@ -123,12 +123,7 @@ void serial_putchar(unsigned port, char c)
     assert(u->base != 0);
 
     while(lpuart_stat_tdre_rdf(u) == 0);
-
-    lpuart_txdata_t txdata = lpuart_txdata_default;
-    // We don't handle break/idle char currently
-    txdata = lpuart_txdata_tsc_insert(txdata, 0);
-    txdata = lpuart_txdata_buf_insert(txdata, c);
-    lpuart_txdata_wr(u, txdata);
+    lpuart_txdata_wr(u,c);
 }
 
 /*
index 60d691b..c2ec8e0 100644 (file)
@@ -106,6 +106,10 @@ bool platform_is_timer_interrupt(uint32_t irq)
     return 0;
 }
 
+uint32_t platform_get_timer_interrupt(void){
+    return timerirq;
+}
+
 systime_t systime_now(void)
 {
     return a15_gt_counter();
index 25c2252..3385c3d 100644 (file)
@@ -115,6 +115,10 @@ bool platform_is_timer_interrupt(uint32_t irq)
     return 0;
 }
 
+uint32_t platform_get_timer_interrupt(void){
+    return GLOBAL_TIMER_IRQ;
+}
+
 systime_t systime_now(void)
 {
     return a9_gt_read();
index c6dd833..e4d3ece 100644 (file)
@@ -102,7 +102,7 @@ static void debug_uart_initialize(void) {
 static void debug_serial_putc(char c)
 {
     while(lpuart_stat_tdre_rdf(&uart) == 0);
-    lpuart_data_buf_wrf(&uart, c);
+    lpuart_write_data_wr(&uart,c);
 }
 #endif
 
index fb7525f..9d7b337 100644 (file)
@@ -259,8 +259,13 @@ void handle_irq(arch_registers_state_t* save_area, uintptr_t fault_pc,
             dcb_current->disabled = false;
         }
     }
+    static int first_timer_interrupt_fired = 0;
     // Offer it to the timer
     if (platform_is_timer_interrupt(irq)) {
+        if(!first_timer_interrupt_fired){
+            printk(LOG_NOTE, "ARMv8-A: Timer interrupt received\n");
+            first_timer_interrupt_fired = 1;
+        }
         platform_acknowledge_irq(irq);
         wakeup_check(systime_now());
 #ifndef CONFIG_ONESHOT_TIMER
index 0f2ce20..4b6bbf7 100644 (file)
@@ -150,3 +150,8 @@ size_t platform_get_core_count(void)
 {
     return 0;
 }
+
+uint32_t platform_get_timer_interrupt(void){
+    // TODO (LH): Untested
+    return 30;
+}
index b96a886..6c513e2 100644 (file)
@@ -86,3 +86,8 @@ void armv8_get_info(struct arch_info_armv8 *ai)
 {
 
 }
+
+uint32_t platform_get_timer_interrupt(void){
+    // TODO (LH): Untested
+    return 30;
+}
index 62fa154..62012f2 100644 (file)
@@ -14,6 +14,7 @@
  */
 
 #include <kernel.h>
+#include <arch/arm/platform.h>
 
 /* RAM starts at 0, provided by the MMAP */
 lpaddr_t phys_memory_start= 0;
@@ -46,13 +47,15 @@ unsigned int serial_debug_port = 0;
 unsigned serial_num_physical_ports = 1;
 
 /* uart bases */
-const lpaddr_t
-platform_uart_base[MAX_NUM_UARTS]= {
+lpaddr_t platform_uart_base[MAX_NUM_UARTS]= {
         0x9000000
 };
 
 /* uart sizes */
-const size_t
-platform_uart_size[MAX_NUM_UARTS]= {
+size_t platform_uart_size[MAX_NUM_UARTS]= {
     4096
 };
+
+uint32_t platform_get_timer_interrupt(void){
+    return 30;
+}
index 3446fbd..74534db 100644 (file)
@@ -143,3 +143,7 @@ void armv8_get_info(struct arch_info_armv8 *ai)
 {
 
 }
+
+uint32_t platform_get_timer_interrupt(void){
+    return 30;
+}
index 9f15a90..80f87d2 100644 (file)
@@ -36,8 +36,8 @@ lpaddr_t phys_memory_start= 0;
  * ----------------------------------------------------------------------------
  */
 
-lpaddr_t platform_gic_distributor_base = 0x8000000;
-lpaddr_t platform_gic_redistributor_base = 0x80a0000;
+lpaddr_t platform_gic_distributor_base = 0x51a00000;
+lpaddr_t platform_gic_redistributor_base = 0x51b00000;
 
 /*
  * ----------------------------------------------------------------------------
@@ -45,6 +45,15 @@ lpaddr_t platform_gic_redistributor_base = 0x80a0000;
  * ----------------------------------------------------------------------------
  */
 
+
+/*
+ * ----------------------------------------------------------------------------
+ * Timer
+ * ----------------------------------------------------------------------------
+ */
+#define GLOBAL_TIMER_INTERRUPT 30
+
+
 /* the maximum number of UARTS supported */
 #define MAX_NUM_UARTS 1
 
@@ -138,6 +147,10 @@ void platform_get_info(struct platform_info *pi)
     pi->platform = PI_PLATFORM_IMX8X;
 }
 
+uint32_t platform_get_timer_interrupt(void){
+    return GLOBAL_TIMER_INTERRUPT;
+}
+
 void armv8_get_info(struct arch_info_armv8 *ai)
 {
 
index 36b8914..2107b21 100644 (file)
@@ -146,3 +146,7 @@ void armv8_get_info(struct arch_info_armv8 *ai)
 {
 
 }
+
+uint32_t platform_get_timer_interrupt(void){
+    return 30;
+}
index 0162d94..3e37c30 100644 (file)
@@ -149,3 +149,8 @@ errval_t platform_enable_interrupt(uint32_t int_id, uint16_t prio,
 {
     return SYS_ERR_OK;
 }
+
+uint32_t platform_get_timer_interrupt(void){
+    // TODO (LH): Untested
+    return 30;
+}
diff --git a/kernel/arch/armv8/plat_tmas.c b/kernel/arch/armv8/plat_tmas.c
deleted file mode 100644 (file)
index 25e337b..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-/**
- * \file plat_tmas.c
- * \brief 
- */
-
-
-/*
- * Copyright (c) 2016 ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
- */
-
-
index 72caec2..3d147e5 100644 (file)
@@ -66,6 +66,10 @@ void platform_timer_init(int timeslice)
     //pmcr = armv8_PMCR_EL0_N_insert(pmcr, 6);  /* N is RO ? */
     armv8_PMCR_EL0_wr(NULL, pmcr);
 
+    errval_t err;
+    err = platform_enable_interrupt(platform_get_timer_interrupt(), 0, 0, 0);
+    assert(err_is_ok(err));
+
 // AT: disable for now because it's not supported by QEMU version<2.6.0
 // AT: doesn't seem to break anything
 //    armv8_PMUSERENR_EL0_t pmu = 0;
index dc7500b..94b1d69 100644 (file)
@@ -104,5 +104,11 @@ void platform_timer_init(int timeslice);
 */
 bool platform_is_timer_interrupt(uint32_t irq);
 
+/**
+* @brief Return the IRQ to be used for the cpu driver timer
+* @return The IRQ number of the timer interrupt.
+*/
+uint32_t platform_get_timer_interrupt(void);
+
 
 #endif // __ARM_PLATFORM_H__