for (int i = 0; i * 32 < itlines; i++) {
// Clear
gic_v3_dist_GICD_ICACTIVER_wr(&gic_v3_dist_dev, i, MASK_32);
- // Enable
- gic_v3_dist_GICD_ISENABLER_wr(&gic_v3_dist_dev, i, MASK_32);
+ // Disable all interrupts
+ gic_v3_dist_GICD_ICENABLER_wr(&gic_v3_dist_dev, i, MASK_32);
// And put in group 1
gic_v3_dist_GICD_IGROUPR_rawwr(&gic_v3_dist_dev, i, MASK_32);
}
printf("%s: GICR_TYPER: affinity:%x cpu_no:%x\n", __func__, gic_v3_redist_GICR_TYPER_Affinity_Value_extract(gicr_typer), gic_v3_redist_GICR_TYPER_Processor_Number_extract(gicr_typer));
gic_v3_redist_GICR_ICACTIVER0_rawwr(&gic_v3_redist_dev, MASK_32);
- gic_v3_redist_GICR_ISENABLER0_rawwr(&gic_v3_redist_dev, MASK_32);
+ //Disable PPIs
+ gic_v3_redist_GICR_ICENABLER0_wr(&gic_v3_redist_dev, MASK_32);
gic_v3_redist_GICR_IGROUPR0_rawwr(&gic_v3_redist_dev, MASK_32);
gic_v3_redist_GICR_IGRPMODR0_rawwr(&gic_v3_redist_dev, 0);
errval_t platform_enable_interrupt(uint32_t int_id, uint16_t prio,
bool edge_triggered, bool one_to_n)
{
+ if(int_id<32) {
+ gic_v3_redist_GICR_ISENABLER0_wr(&gic_v3_redist_dev, 1<<int_id );
+ }
+ else {
+ gic_v3_dist_GICD_ISENABLER_wr(&gic_v3_dist_dev, int_id/32,
+ 1<<(int_id % 32));
+ }
return SYS_ERR_OK;
}
assert(u->base != 0);
while(lpuart_stat_tdre_rdf(u) == 0);
-
- lpuart_txdata_t txdata = lpuart_txdata_default;
- // We don't handle break/idle char currently
- txdata = lpuart_txdata_tsc_insert(txdata, 0);
- txdata = lpuart_txdata_buf_insert(txdata, c);
- lpuart_txdata_wr(u, txdata);
+ lpuart_txdata_wr(u,c);
}
/*
return 0;
}
+uint32_t platform_get_timer_interrupt(void){
+ return timerirq;
+}
+
systime_t systime_now(void)
{
return a15_gt_counter();
return 0;
}
+uint32_t platform_get_timer_interrupt(void){
+ return GLOBAL_TIMER_IRQ;
+}
+
systime_t systime_now(void)
{
return a9_gt_read();
static void debug_serial_putc(char c)
{
while(lpuart_stat_tdre_rdf(&uart) == 0);
- lpuart_data_buf_wrf(&uart, c);
+ lpuart_write_data_wr(&uart,c);
}
#endif
dcb_current->disabled = false;
}
}
+ static int first_timer_interrupt_fired = 0;
// Offer it to the timer
if (platform_is_timer_interrupt(irq)) {
+ if(!first_timer_interrupt_fired){
+ printk(LOG_NOTE, "ARMv8-A: Timer interrupt received\n");
+ first_timer_interrupt_fired = 1;
+ }
platform_acknowledge_irq(irq);
wakeup_check(systime_now());
#ifndef CONFIG_ONESHOT_TIMER
{
return 0;
}
+
+uint32_t platform_get_timer_interrupt(void){
+ // TODO (LH): Untested
+ return 30;
+}
{
}
+
+uint32_t platform_get_timer_interrupt(void){
+ // TODO (LH): Untested
+ return 30;
+}
*/
#include <kernel.h>
+#include <arch/arm/platform.h>
/* RAM starts at 0, provided by the MMAP */
lpaddr_t phys_memory_start= 0;
unsigned serial_num_physical_ports = 1;
/* uart bases */
-const lpaddr_t
-platform_uart_base[MAX_NUM_UARTS]= {
+lpaddr_t platform_uart_base[MAX_NUM_UARTS]= {
0x9000000
};
/* uart sizes */
-const size_t
-platform_uart_size[MAX_NUM_UARTS]= {
+size_t platform_uart_size[MAX_NUM_UARTS]= {
4096
};
+
+uint32_t platform_get_timer_interrupt(void){
+ return 30;
+}
{
}
+
+uint32_t platform_get_timer_interrupt(void){
+ return 30;
+}
* ----------------------------------------------------------------------------
*/
-lpaddr_t platform_gic_distributor_base = 0x8000000;
-lpaddr_t platform_gic_redistributor_base = 0x80a0000;
+lpaddr_t platform_gic_distributor_base = 0x51a00000;
+lpaddr_t platform_gic_redistributor_base = 0x51b00000;
/*
* ----------------------------------------------------------------------------
* ----------------------------------------------------------------------------
*/
+
+/*
+ * ----------------------------------------------------------------------------
+ * Timer
+ * ----------------------------------------------------------------------------
+ */
+#define GLOBAL_TIMER_INTERRUPT 30
+
+
/* the maximum number of UARTS supported */
#define MAX_NUM_UARTS 1
pi->platform = PI_PLATFORM_IMX8X;
}
+uint32_t platform_get_timer_interrupt(void){
+ return GLOBAL_TIMER_INTERRUPT;
+}
+
void armv8_get_info(struct arch_info_armv8 *ai)
{
{
}
+
+uint32_t platform_get_timer_interrupt(void){
+ return 30;
+}
{
return SYS_ERR_OK;
}
+
+uint32_t platform_get_timer_interrupt(void){
+ // TODO (LH): Untested
+ return 30;
+}
+++ /dev/null
-/**
- * \file plat_tmas.c
- * \brief
- */
-
-
-/*
- * Copyright (c) 2016 ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
- */
-
-
//pmcr = armv8_PMCR_EL0_N_insert(pmcr, 6); /* N is RO ? */
armv8_PMCR_EL0_wr(NULL, pmcr);
+ errval_t err;
+ err = platform_enable_interrupt(platform_get_timer_interrupt(), 0, 0, 0);
+ assert(err_is_ok(err));
+
// AT: disable for now because it's not supported by QEMU version<2.6.0
// AT: doesn't seem to break anything
// armv8_PMUSERENR_EL0_t pmu = 0;
*/
bool platform_is_timer_interrupt(uint32_t irq);
+/**
+* @brief Return the IRQ to be used for the cpu driver timer
+* @return The IRQ number of the timer interrupt.
+*/
+uint32_t platform_get_timer_interrupt(void);
+
#endif // __ARM_PLATFORM_H__