Initial ARMv8 device file with backing sysreg implementation
authorMoritz Hoffmann <moritz.hoffmann@inf.ethz.ch>
Tue, 6 Dec 2016 10:39:59 +0000 (11:39 +0100)
committerMoritz Hoffmann <moritz.hoffmann@inf.ethz.ch>
Tue, 6 Dec 2016 10:39:59 +0000 (11:39 +0100)
Signed-off-by: Moritz Hoffmann <moritz.hoffmann@inf.ethz.ch>

devices/Hakefile
devices/armv8.dev [new file with mode: 0644]
kernel/arch/armv8/sysreg.S

index 3926a1a..d62ed4b 100644 (file)
@@ -17,6 +17,7 @@
 [ mackerel2 (options arch) f
   | f <- [ "ac97_base_audio",
            "ac97_ext_audio",
+           "armv8",
            "cpuid_intel",
            "cpuid_amd",
            "cpuid_arm",
diff --git a/devices/armv8.dev b/devices/armv8.dev
new file mode 100644 (file)
index 0000000..3b8dd2c
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, ETH Zurich. All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group.
+ */
+
+/*
+ * armv8.dev
+ *
+ * DESCRIPTION: ARMv8 architecture definitions
+ * 
+ * See:
+ *   ARM Architecture Reference Manual
+ */
+
+device armv8 msbfirst () "ARMv8 architecture" {
+
+    space sysreg(name) registerwise "System registers";
+
+    register ICC_SRE_EL1 rw sysreg(ICC_SRE_EL1) "Interrupt Controller System Register Enable" {
+        _       29;
+        DIB     1;
+        DFB     1;
+        SRE     1;
+    };
+
+};
index 897e4e2..797a690 100644 (file)
@@ -163,3 +163,32 @@ sysreg_enable_mmu:
        isb
        
        ret x12
+
+.macro sysreg_read sz name reg
+.globl armv8_sysreg_read\()_\sz\()_\name
+armv8_sysreg_read\()_\sz\()_\name :
+    mov x12, x30
+    mrs x0, \reg
+    ret x12
+    nop
+.endm
+
+.macro sysreg_write sz name reg
+.globl armv8_sysreg_write\()_\sz\()_\name
+armv8_sysreg_write\()_\sz\()_\name :
+    mov x12, x30
+    msr \reg , x0
+    ret x12
+    nop
+.endm
+
+.macro sysreg_rw sz name reg
+sysreg_read \sz \name \reg
+sysreg_write \sz \name \reg
+.endm
+
+.macro sysreg_ro sz name reg
+sysreg read \sz \name \reg
+.endm
+
+sysreg_rw 32 ICC_SRE_EL1 S3_0_C12_C12_5