libcompiler-rt: update to newest version from github repo
authorReto Achermann <reto.achermann@inf.ethz.ch>
Mon, 19 Aug 2019 16:04:55 +0000 (18:04 +0200)
committerReto Achermann <reto.achermann@inf.ethz.ch>
Tue, 20 Aug 2019 17:43:07 +0000 (19:43 +0200)
Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>

533 files changed:
lib/compiler-rt/builtins/CMakeLists.txt [new file with mode: 0644]
lib/compiler-rt/builtins/Hakefile
lib/compiler-rt/builtins/README.txt
lib/compiler-rt/builtins/aarch64/chkstk.S [new file with mode: 0644]
lib/compiler-rt/builtins/absvdi2.c
lib/compiler-rt/builtins/absvsi2.c
lib/compiler-rt/builtins/absvti2.c
lib/compiler-rt/builtins/adddf3.c
lib/compiler-rt/builtins/addsf3.c
lib/compiler-rt/builtins/addtf3.c
lib/compiler-rt/builtins/addvdi3.c
lib/compiler-rt/builtins/addvsi3.c
lib/compiler-rt/builtins/addvti3.c
lib/compiler-rt/builtins/apple_versioning.c [new file with mode: 0644]
lib/compiler-rt/builtins/arm/adddf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/addsf3.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/addsf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/aeabi_cdcmp.S
lib/compiler-rt/builtins/arm/aeabi_cdcmpeq_check_nan.c
lib/compiler-rt/builtins/arm/aeabi_cfcmp.S
lib/compiler-rt/builtins/arm/aeabi_cfcmpeq_check_nan.c
lib/compiler-rt/builtins/arm/aeabi_dcmp.S
lib/compiler-rt/builtins/arm/aeabi_div0.c
lib/compiler-rt/builtins/arm/aeabi_drsub.c
lib/compiler-rt/builtins/arm/aeabi_fcmp.S
lib/compiler-rt/builtins/arm/aeabi_frsub.c
lib/compiler-rt/builtins/arm/aeabi_idivmod.S
lib/compiler-rt/builtins/arm/aeabi_ldivmod.S
lib/compiler-rt/builtins/arm/aeabi_memcmp.S
lib/compiler-rt/builtins/arm/aeabi_memcpy.S
lib/compiler-rt/builtins/arm/aeabi_memmove.S
lib/compiler-rt/builtins/arm/aeabi_memset.S
lib/compiler-rt/builtins/arm/aeabi_uidivmod.S
lib/compiler-rt/builtins/arm/aeabi_uldivmod.S
lib/compiler-rt/builtins/arm/bswapdi2.S
lib/compiler-rt/builtins/arm/bswapsi2.S
lib/compiler-rt/builtins/arm/chkstk.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/clzdi2.S
lib/compiler-rt/builtins/arm/clzsi2.S
lib/compiler-rt/builtins/arm/comparesf2.S
lib/compiler-rt/builtins/arm/divdf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/divmodsi4.S
lib/compiler-rt/builtins/arm/divsf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/divsi3.S
lib/compiler-rt/builtins/arm/eqdf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/eqsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/extendsfdf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/fixdfsivfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/fixsfsivfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/fixunsdfsivfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/fixunssfsivfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/floatsidfvfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/floatsisfvfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/floatunssidfvfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/floatunssisfvfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/gedf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/gesf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/gtdf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/gtsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/ledf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/lesf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/ltdf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/ltsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/modsi3.S
lib/compiler-rt/builtins/arm/muldf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/mulsf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/nedf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/negdf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/negsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/nesf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/restore_vfp_d8_d15_regs.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/save_vfp_d8_d15_regs.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/softfloat-alias.list
lib/compiler-rt/builtins/arm/subdf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/subsf3vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/switch16.S
lib/compiler-rt/builtins/arm/switch32.S
lib/compiler-rt/builtins/arm/switch8.S
lib/compiler-rt/builtins/arm/switchu8.S
lib/compiler-rt/builtins/arm/sync-ops.h
lib/compiler-rt/builtins/arm/sync_fetch_and_add_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_add_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_and_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_and_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_max_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_max_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_min_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_min_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_nand_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_nand_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_or_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_or_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_sub_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_sub_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_umax_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_umax_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_umin_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_umin_8.S
lib/compiler-rt/builtins/arm/sync_fetch_and_xor_4.S
lib/compiler-rt/builtins/arm/sync_fetch_and_xor_8.S
lib/compiler-rt/builtins/arm/sync_synchronize.S
lib/compiler-rt/builtins/arm/truncdfsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/udivmodsi4.S
lib/compiler-rt/builtins/arm/udivsi3.S
lib/compiler-rt/builtins/arm/umodsi3.S
lib/compiler-rt/builtins/arm/unorddf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/arm/unordsf2vfp.S [new file with mode: 0644]
lib/compiler-rt/builtins/ashldi3.c
lib/compiler-rt/builtins/ashlti3.c
lib/compiler-rt/builtins/ashrdi3.c
lib/compiler-rt/builtins/ashrti3.c
lib/compiler-rt/builtins/assembly.h
lib/compiler-rt/builtins/atomic.c
lib/compiler-rt/builtins/atomic_flag_clear.c
lib/compiler-rt/builtins/atomic_flag_clear_explicit.c
lib/compiler-rt/builtins/atomic_flag_test_and_set.c
lib/compiler-rt/builtins/atomic_flag_test_and_set_explicit.c
lib/compiler-rt/builtins/atomic_signal_fence.c
lib/compiler-rt/builtins/atomic_thread_fence.c
lib/compiler-rt/builtins/bswapdi2.c [new file with mode: 0644]
lib/compiler-rt/builtins/bswapsi2.c [new file with mode: 0644]
lib/compiler-rt/builtins/clear_cache.c
lib/compiler-rt/builtins/clzdi2.c
lib/compiler-rt/builtins/clzsi2.c
lib/compiler-rt/builtins/clzti2.c
lib/compiler-rt/builtins/cmpdi2.c
lib/compiler-rt/builtins/cmpti2.c
lib/compiler-rt/builtins/comparedf2.c
lib/compiler-rt/builtins/comparesf2.c
lib/compiler-rt/builtins/comparetf2.c
lib/compiler-rt/builtins/cpu_model.c [new file with mode: 0644]
lib/compiler-rt/builtins/ctzdi2.c
lib/compiler-rt/builtins/ctzsi2.c
lib/compiler-rt/builtins/ctzti2.c
lib/compiler-rt/builtins/divdc3.c
lib/compiler-rt/builtins/divdf3.c
lib/compiler-rt/builtins/divdi3.c
lib/compiler-rt/builtins/divmoddi4.c
lib/compiler-rt/builtins/divmodsi4.c
lib/compiler-rt/builtins/divsc3.c
lib/compiler-rt/builtins/divsf3.c
lib/compiler-rt/builtins/divsi3.c
lib/compiler-rt/builtins/divtc3.c
lib/compiler-rt/builtins/divtf3.c
lib/compiler-rt/builtins/divti3.c
lib/compiler-rt/builtins/divxc3.c
lib/compiler-rt/builtins/emutls.c
lib/compiler-rt/builtins/enable_execute_stack.c
lib/compiler-rt/builtins/eprintf.c [new file with mode: 0644]
lib/compiler-rt/builtins/extenddftf2.c
lib/compiler-rt/builtins/extendhfsf2.c
lib/compiler-rt/builtins/extendsfdf2.c
lib/compiler-rt/builtins/extendsftf2.c
lib/compiler-rt/builtins/ffsdi2.c
lib/compiler-rt/builtins/ffssi2.c [new file with mode: 0644]
lib/compiler-rt/builtins/ffsti2.c
lib/compiler-rt/builtins/fixdfdi.c
lib/compiler-rt/builtins/fixdfsi.c
lib/compiler-rt/builtins/fixdfti.c
lib/compiler-rt/builtins/fixsfdi.c
lib/compiler-rt/builtins/fixsfsi.c
lib/compiler-rt/builtins/fixsfti.c
lib/compiler-rt/builtins/fixtfdi.c
lib/compiler-rt/builtins/fixtfsi.c
lib/compiler-rt/builtins/fixtfti.c
lib/compiler-rt/builtins/fixunsdfdi.c
lib/compiler-rt/builtins/fixunsdfsi.c
lib/compiler-rt/builtins/fixunsdfti.c
lib/compiler-rt/builtins/fixunssfdi.c
lib/compiler-rt/builtins/fixunssfsi.c
lib/compiler-rt/builtins/fixunssfti.c
lib/compiler-rt/builtins/fixunstfdi.c
lib/compiler-rt/builtins/fixunstfsi.c
lib/compiler-rt/builtins/fixunstfti.c
lib/compiler-rt/builtins/fixunsxfdi.c
lib/compiler-rt/builtins/fixunsxfsi.c
lib/compiler-rt/builtins/fixunsxfti.c
lib/compiler-rt/builtins/fixxfdi.c
lib/compiler-rt/builtins/fixxfti.c
lib/compiler-rt/builtins/floatdidf.c
lib/compiler-rt/builtins/floatdisf.c
lib/compiler-rt/builtins/floatditf.c
lib/compiler-rt/builtins/floatdixf.c
lib/compiler-rt/builtins/floatsidf.c
lib/compiler-rt/builtins/floatsisf.c
lib/compiler-rt/builtins/floatsitf.c
lib/compiler-rt/builtins/floattidf.c
lib/compiler-rt/builtins/floattisf.c
lib/compiler-rt/builtins/floattitf.c [new file with mode: 0644]
lib/compiler-rt/builtins/floattixf.c
lib/compiler-rt/builtins/floatundidf.c
lib/compiler-rt/builtins/floatundisf.c
lib/compiler-rt/builtins/floatunditf.c
lib/compiler-rt/builtins/floatundixf.c
lib/compiler-rt/builtins/floatunsidf.c
lib/compiler-rt/builtins/floatunsisf.c
lib/compiler-rt/builtins/floatunsitf.c
lib/compiler-rt/builtins/floatuntidf.c
lib/compiler-rt/builtins/floatuntisf.c
lib/compiler-rt/builtins/floatuntitf.c [new file with mode: 0644]
lib/compiler-rt/builtins/floatuntixf.c
lib/compiler-rt/builtins/fp_add_impl.inc
lib/compiler-rt/builtins/fp_extend.h
lib/compiler-rt/builtins/fp_extend_impl.inc
lib/compiler-rt/builtins/fp_fixint_impl.inc
lib/compiler-rt/builtins/fp_fixuint_impl.inc
lib/compiler-rt/builtins/fp_lib.h
lib/compiler-rt/builtins/fp_mul_impl.inc
lib/compiler-rt/builtins/fp_trunc.h
lib/compiler-rt/builtins/fp_trunc_impl.inc
lib/compiler-rt/builtins/gcc_personality_v0.c
lib/compiler-rt/builtins/i386/ashldi3.S
lib/compiler-rt/builtins/i386/ashrdi3.S
lib/compiler-rt/builtins/i386/chkstk.S
lib/compiler-rt/builtins/i386/chkstk2.S
lib/compiler-rt/builtins/i386/divdi3.S
lib/compiler-rt/builtins/i386/floatdidf.S
lib/compiler-rt/builtins/i386/floatdisf.S
lib/compiler-rt/builtins/i386/floatdixf.S
lib/compiler-rt/builtins/i386/floatundidf.S
lib/compiler-rt/builtins/i386/floatundisf.S
lib/compiler-rt/builtins/i386/floatundixf.S
lib/compiler-rt/builtins/i386/lshrdi3.S
lib/compiler-rt/builtins/i386/moddi3.S
lib/compiler-rt/builtins/i386/muldi3.S
lib/compiler-rt/builtins/i386/udivdi3.S
lib/compiler-rt/builtins/i386/umoddi3.S
lib/compiler-rt/builtins/int_endianness.h
lib/compiler-rt/builtins/int_lib.h
lib/compiler-rt/builtins/int_math.h
lib/compiler-rt/builtins/int_types.h
lib/compiler-rt/builtins/int_util.c
lib/compiler-rt/builtins/int_util.h
lib/compiler-rt/builtins/lshrdi3.c
lib/compiler-rt/builtins/lshrti3.c
lib/compiler-rt/builtins/mingw_fixfloat.c [new file with mode: 0644]
lib/compiler-rt/builtins/moddi3.c
lib/compiler-rt/builtins/modsi3.c
lib/compiler-rt/builtins/modti3.c
lib/compiler-rt/builtins/muldc3.c
lib/compiler-rt/builtins/muldf3.c
lib/compiler-rt/builtins/muldi3.c
lib/compiler-rt/builtins/mulodi4.c
lib/compiler-rt/builtins/mulosi4.c
lib/compiler-rt/builtins/muloti4.c
lib/compiler-rt/builtins/mulsc3.c
lib/compiler-rt/builtins/mulsf3.c
lib/compiler-rt/builtins/multc3.c
lib/compiler-rt/builtins/multf3.c
lib/compiler-rt/builtins/multi3.c
lib/compiler-rt/builtins/mulvdi3.c
lib/compiler-rt/builtins/mulvsi3.c
lib/compiler-rt/builtins/mulvti3.c
lib/compiler-rt/builtins/mulxc3.c
lib/compiler-rt/builtins/negdf2.c
lib/compiler-rt/builtins/negdi2.c
lib/compiler-rt/builtins/negsf2.c
lib/compiler-rt/builtins/negti2.c
lib/compiler-rt/builtins/negvdi2.c
lib/compiler-rt/builtins/negvsi2.c
lib/compiler-rt/builtins/negvti2.c
lib/compiler-rt/builtins/os_version_check.c [new file with mode: 0644]
lib/compiler-rt/builtins/paritydi2.c
lib/compiler-rt/builtins/paritysi2.c
lib/compiler-rt/builtins/parityti2.c
lib/compiler-rt/builtins/popcountdi2.c
lib/compiler-rt/builtins/popcountsi2.c
lib/compiler-rt/builtins/popcountti2.c
lib/compiler-rt/builtins/powidf2.c
lib/compiler-rt/builtins/powisf2.c
lib/compiler-rt/builtins/powitf2.c
lib/compiler-rt/builtins/powixf2.c
lib/compiler-rt/builtins/riscv/mulsi3.S [new file with mode: 0644]
lib/compiler-rt/builtins/subdf3.c
lib/compiler-rt/builtins/subsf3.c
lib/compiler-rt/builtins/subtf3.c
lib/compiler-rt/builtins/subvdi3.c
lib/compiler-rt/builtins/subvsi3.c
lib/compiler-rt/builtins/subvti3.c
lib/compiler-rt/builtins/trampoline_setup.c
lib/compiler-rt/builtins/truncdfhf2.c
lib/compiler-rt/builtins/truncdfsf2.c
lib/compiler-rt/builtins/truncsfhf2.c
lib/compiler-rt/builtins/trunctfdf2.c
lib/compiler-rt/builtins/trunctfsf2.c
lib/compiler-rt/builtins/ucmpdi2.c
lib/compiler-rt/builtins/ucmpti2.c
lib/compiler-rt/builtins/udivdi3.c
lib/compiler-rt/builtins/udivmoddi4.c
lib/compiler-rt/builtins/udivmodsi4.c
lib/compiler-rt/builtins/udivmodti4.c
lib/compiler-rt/builtins/udivsi3.c
lib/compiler-rt/builtins/udivti3.c
lib/compiler-rt/builtins/umoddi3.c
lib/compiler-rt/builtins/umodsi3.c
lib/compiler-rt/builtins/umodti3.c
lib/compiler-rt/builtins/unwind-ehabi-helpers.h [new file with mode: 0644]
lib/compiler-rt/builtins/x86_64/chkstk.S
lib/compiler-rt/builtins/x86_64/chkstk2.S
lib/compiler-rt/builtins/x86_64/floatdidf.c
lib/compiler-rt/builtins/x86_64/floatdisf.c
lib/compiler-rt/builtins/x86_64/floatdixf.c
lib/compiler-rt/builtins/x86_64/floatundidf.S
lib/compiler-rt/builtins/x86_64/floatundisf.S
lib/compiler-rt/builtins/x86_64/floatundixf.S
lib/compiler-rt/test/CMakeLists.txt [new file with mode: 0644]
lib/compiler-rt/test/Hakefile
lib/compiler-rt/test/absvdi2_test.c
lib/compiler-rt/test/absvsi2_test.c
lib/compiler-rt/test/absvti2_test.c
lib/compiler-rt/test/adddf3vfp_test.c
lib/compiler-rt/test/addsf3vfp_test.c
lib/compiler-rt/test/addtf3_test.c
lib/compiler-rt/test/addvdi3_test.c
lib/compiler-rt/test/addvsi3_test.c
lib/compiler-rt/test/addvti3_test.c
lib/compiler-rt/test/arm/aeabi_cdcmpeq_test.c
lib/compiler-rt/test/arm/aeabi_cdcmple_test.c
lib/compiler-rt/test/arm/aeabi_cfcmpeq_test.c
lib/compiler-rt/test/arm/aeabi_cfcmple_test.c
lib/compiler-rt/test/arm/aeabi_drsub_test.c
lib/compiler-rt/test/arm/aeabi_frsub_test.c
lib/compiler-rt/test/arm/aeabi_idivmod_test.c [new file with mode: 0644]
lib/compiler-rt/test/arm/aeabi_uidivmod_test.c [new file with mode: 0644]
lib/compiler-rt/test/arm/aeabi_uldivmod_test.c [new file with mode: 0644]
lib/compiler-rt/test/arm/call_apsr.S
lib/compiler-rt/test/arm/call_apsr.h
lib/compiler-rt/test/ashldi3_test.c
lib/compiler-rt/test/ashlti3_test.c
lib/compiler-rt/test/ashrdi3_test.c
lib/compiler-rt/test/ashrti3_test.c
lib/compiler-rt/test/bswapdi2_test.c
lib/compiler-rt/test/bswapsi2_test.c
lib/compiler-rt/test/clear_cache_test.c [new file with mode: 0644]
lib/compiler-rt/test/clzdi2_test.c
lib/compiler-rt/test/clzsi2_test.c
lib/compiler-rt/test/clzti2_test.c
lib/compiler-rt/test/cmpdi2_test.c
lib/compiler-rt/test/cmpti2_test.c
lib/compiler-rt/test/comparedf2_test.c
lib/compiler-rt/test/comparesf2_test.c
lib/compiler-rt/test/compiler_rt_logb_test.c [new file with mode: 0644]
lib/compiler-rt/test/compiler_rt_logbf_test.c [new file with mode: 0644]
lib/compiler-rt/test/compiler_rt_logbl_test.c [new file with mode: 0644]
lib/compiler-rt/test/cpu_model_test.c [new file with mode: 0644]
lib/compiler-rt/test/ctzdi2_test.c
lib/compiler-rt/test/ctzsi2_test.c
lib/compiler-rt/test/ctzti2_test.c
lib/compiler-rt/test/divdc3_test.c
lib/compiler-rt/test/divdf3_test.c [new file with mode: 0644]
lib/compiler-rt/test/divdf3vfp_test.c
lib/compiler-rt/test/divdi3_test.c
lib/compiler-rt/test/divmodsi4_test.c
lib/compiler-rt/test/divsc3_test.c
lib/compiler-rt/test/divsf3_test.c [new file with mode: 0644]
lib/compiler-rt/test/divsf3vfp_test.c
lib/compiler-rt/test/divsi3_test.c
lib/compiler-rt/test/divtc3_test.c [new file with mode: 0644]
lib/compiler-rt/test/divtf3_test.c
lib/compiler-rt/test/divti3_test.c
lib/compiler-rt/test/divxc3_test.c
lib/compiler-rt/test/enable_execute_stack_test.c [new file with mode: 0644]
lib/compiler-rt/test/endianness.h
lib/compiler-rt/test/eqdf2vfp_test.c
lib/compiler-rt/test/eqsf2vfp_test.c
lib/compiler-rt/test/eqtf2_test.c
lib/compiler-rt/test/extebdsfdf2vfp_test.c
lib/compiler-rt/test/extenddftf2_test.c
lib/compiler-rt/test/extendhfsf2_test.c [new file with mode: 0644]
lib/compiler-rt/test/extendsftf2_test.c
lib/compiler-rt/test/ffsdi2_test.c
lib/compiler-rt/test/ffssi2_test.c [new file with mode: 0644]
lib/compiler-rt/test/ffsti2_test.c
lib/compiler-rt/test/fixdfdi_test.c
lib/compiler-rt/test/fixdfsivfp_test.c
lib/compiler-rt/test/fixdfti_test.c
lib/compiler-rt/test/fixsfdi_test.c
lib/compiler-rt/test/fixsfsivfp_test.c
lib/compiler-rt/test/fixsfti_test.c
lib/compiler-rt/test/fixtfdi_test.c
lib/compiler-rt/test/fixtfsi_test.c
lib/compiler-rt/test/fixtfti_test.c
lib/compiler-rt/test/fixunsdfdi_test.c
lib/compiler-rt/test/fixunsdfsi_test.c
lib/compiler-rt/test/fixunsdfsivfp_test.c
lib/compiler-rt/test/fixunsdfti_test.c
lib/compiler-rt/test/fixunssfdi_test.c
lib/compiler-rt/test/fixunssfsi_test.c
lib/compiler-rt/test/fixunssfsivfp_test.c
lib/compiler-rt/test/fixunssfti_test.c
lib/compiler-rt/test/fixunstfdi_test.c
lib/compiler-rt/test/fixunstfsi_test.c
lib/compiler-rt/test/fixunstfti_test.c
lib/compiler-rt/test/fixunsxfdi_test.c
lib/compiler-rt/test/fixunsxfsi_test.c
lib/compiler-rt/test/fixunsxfti_test.c
lib/compiler-rt/test/fixxfdi_test.c
lib/compiler-rt/test/fixxfti_test.c
lib/compiler-rt/test/floatdidf_test.c
lib/compiler-rt/test/floatdisf_test.c
lib/compiler-rt/test/floatditf_test.c
lib/compiler-rt/test/floatdixf_test.c
lib/compiler-rt/test/floatsidfvfp_test.c
lib/compiler-rt/test/floatsisfvfp_test.c
lib/compiler-rt/test/floatsitf_test.c
lib/compiler-rt/test/floattidf_test.c
lib/compiler-rt/test/floattisf_test.c
lib/compiler-rt/test/floattitf_test.c [new file with mode: 0644]
lib/compiler-rt/test/floattixf_test.c
lib/compiler-rt/test/floatundidf_test.c
lib/compiler-rt/test/floatundisf_test.c
lib/compiler-rt/test/floatunditf_test.c
lib/compiler-rt/test/floatundixf_test.c
lib/compiler-rt/test/floatunsitf_test.c
lib/compiler-rt/test/floatunssidfvfp_test.c
lib/compiler-rt/test/floatunssisfvfp_test.c
lib/compiler-rt/test/floatuntidf_test.c
lib/compiler-rt/test/floatuntisf_test.c
lib/compiler-rt/test/floatuntitf_test.c [new file with mode: 0644]
lib/compiler-rt/test/floatuntixf_test.c
lib/compiler-rt/test/fp_test.h
lib/compiler-rt/test/gcc_personality_test.c
lib/compiler-rt/test/gcc_personality_test_helper.cxx
lib/compiler-rt/test/gedf2vfp_test.c
lib/compiler-rt/test/gesf2vfp_test.c
lib/compiler-rt/test/getf2_test.c
lib/compiler-rt/test/gtdf2vfp_test.c
lib/compiler-rt/test/gtsf2vfp_test.c
lib/compiler-rt/test/gttf2_test.c
lib/compiler-rt/test/ledf2vfp_test.c
lib/compiler-rt/test/lesf2vfp_test.c
lib/compiler-rt/test/letf2_test.c
lib/compiler-rt/test/lshrdi3_test.c
lib/compiler-rt/test/lshrti3_test.c
lib/compiler-rt/test/ltdf2vfp_test.c
lib/compiler-rt/test/ltsf2vfp_test.c
lib/compiler-rt/test/lttf2_test.c
lib/compiler-rt/test/moddi3_test.c
lib/compiler-rt/test/modsi3_test.c
lib/compiler-rt/test/modti3_test.c
lib/compiler-rt/test/muldc3_test.c
lib/compiler-rt/test/muldf3vfp_test.c
lib/compiler-rt/test/muldi3_test.c
lib/compiler-rt/test/mulodi4_test.c
lib/compiler-rt/test/mulosi4_test.c
lib/compiler-rt/test/muloti4_test.c
lib/compiler-rt/test/mulsc3_test.c
lib/compiler-rt/test/mulsf3vfp_test.c
lib/compiler-rt/test/multc3_test.c
lib/compiler-rt/test/multf3_test.c
lib/compiler-rt/test/multi3_test.c
lib/compiler-rt/test/mulvdi3_test.c
lib/compiler-rt/test/mulvsi3_test.c
lib/compiler-rt/test/mulvti3_test.c
lib/compiler-rt/test/mulxc3_test.c
lib/compiler-rt/test/nedf2vfp_test.c
lib/compiler-rt/test/negdf2vfp_test.c
lib/compiler-rt/test/negdi2_test.c
lib/compiler-rt/test/negsf2vfp_test.c
lib/compiler-rt/test/negti2_test.c
lib/compiler-rt/test/negvdi2_test.c
lib/compiler-rt/test/negvsi2_test.c
lib/compiler-rt/test/negvti2_test.c
lib/compiler-rt/test/nesf2vfp_test.c
lib/compiler-rt/test/netf2_test.c
lib/compiler-rt/test/paritydi2_test.c
lib/compiler-rt/test/paritysi2_test.c
lib/compiler-rt/test/parityti2_test.c
lib/compiler-rt/test/popcountdi2_test.c
lib/compiler-rt/test/popcountsi2_test.c
lib/compiler-rt/test/popcountti2_test.c
lib/compiler-rt/test/powidf2_test.c
lib/compiler-rt/test/powisf2_test.c
lib/compiler-rt/test/powitf2_test.c
lib/compiler-rt/test/powixf2_test.c
lib/compiler-rt/test/ppc/DD.h [deleted file]
lib/compiler-rt/test/ppc/fixtfdi_test.c [deleted file]
lib/compiler-rt/test/ppc/floatditf_test.c [deleted file]
lib/compiler-rt/test/ppc/floatditf_test.h [deleted file]
lib/compiler-rt/test/ppc/floatunditf_test.c [deleted file]
lib/compiler-rt/test/ppc/floatunditf_test.h [deleted file]
lib/compiler-rt/test/ppc/qadd_test.c [deleted file]
lib/compiler-rt/test/ppc/qdiv_test.c [deleted file]
lib/compiler-rt/test/ppc/qmul_test.c [deleted file]
lib/compiler-rt/test/ppc/qsub_test.c [deleted file]
lib/compiler-rt/test/ppc/test [deleted file]
lib/compiler-rt/test/riscv/mulsi3_test.c [new file with mode: 0644]
lib/compiler-rt/test/subdf3vfp_test.c
lib/compiler-rt/test/subsf3vfp_test.c
lib/compiler-rt/test/subtf3_test.c
lib/compiler-rt/test/subvdi3_test.c
lib/compiler-rt/test/subvsi3_test.c
lib/compiler-rt/test/subvti3_test.c
lib/compiler-rt/test/test [deleted file]
lib/compiler-rt/test/timing/ashldi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/ashrdi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/divdi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatdidf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatdisf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatdixf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatundidf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatundisf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/floatundixf.c [new file with mode: 0644]
lib/compiler-rt/test/timing/lshrdi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/moddi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/modsi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/muldi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/negdi2.c [new file with mode: 0644]
lib/compiler-rt/test/timing/time [new file with mode: 0755]
lib/compiler-rt/test/timing/timing.h [new file with mode: 0644]
lib/compiler-rt/test/timing/udivdi3.c [new file with mode: 0644]
lib/compiler-rt/test/timing/umoddi3.c [new file with mode: 0644]
lib/compiler-rt/test/trampoline_setup_test.c [new file with mode: 0644]
lib/compiler-rt/test/truncdfhf2_test.c [new file with mode: 0644]
lib/compiler-rt/test/truncdfsf2_test.c
lib/compiler-rt/test/truncdfsf2vfp_test.c
lib/compiler-rt/test/truncsfhf2_test.c [new file with mode: 0644]
lib/compiler-rt/test/trunctfdf2_test.c
lib/compiler-rt/test/trunctfsf2_test.c
lib/compiler-rt/test/ucmpdi2_test.c
lib/compiler-rt/test/ucmpti2_test.c
lib/compiler-rt/test/udivdi3_test.c
lib/compiler-rt/test/udivmoddi4_test.c
lib/compiler-rt/test/udivmodsi4_test.c
lib/compiler-rt/test/udivmodti4_test.c
lib/compiler-rt/test/udivsi3_test.c
lib/compiler-rt/test/udivti3_test.c
lib/compiler-rt/test/umoddi3_test.c
lib/compiler-rt/test/umodsi3_test.c
lib/compiler-rt/test/umodti3_test.c
lib/compiler-rt/test/unorddf2vfp_test.c
lib/compiler-rt/test/unordsf2vfp_test.c
lib/compiler-rt/test/unordtf2_test.c

diff --git a/lib/compiler-rt/builtins/CMakeLists.txt b/lib/compiler-rt/builtins/CMakeLists.txt
new file mode 100644 (file)
index 0000000..4062efc
--- /dev/null
@@ -0,0 +1,638 @@
+# This directory contains a large amount of C code which provides
+# generic implementations of the core runtime library along with optimized
+# architecture-specific code in various subdirectories.
+
+if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
+  cmake_minimum_required(VERSION 3.4.3)
+
+  project(CompilerRTBuiltins C ASM)
+  set(COMPILER_RT_STANDALONE_BUILD TRUE)
+  set(COMPILER_RT_BUILTINS_STANDALONE_BUILD TRUE)
+  list(INSERT CMAKE_MODULE_PATH 0
+    "${CMAKE_SOURCE_DIR}/../../cmake"
+    "${CMAKE_SOURCE_DIR}/../../cmake/Modules")
+  include(base-config-ix)
+  include(CompilerRTUtils)
+
+  load_llvm_config()
+  construct_compiler_rt_default_triple()
+
+  if(APPLE)
+    include(CompilerRTDarwinUtils)
+  endif()
+  if(CMAKE_HOST_APPLE AND APPLE)
+    include(UseLibtool)
+  endif()
+  include(AddCompilerRT)
+endif()
+
+include(builtin-config-ix)
+
+# TODO: Need to add a mechanism for logging errors when builtin source files are
+# added to a sub-directory and not this CMakeLists file.
+set(GENERIC_SOURCES
+  absvdi2.c
+  absvsi2.c
+  absvti2.c
+  adddf3.c
+  addsf3.c
+  addtf3.c
+  addvdi3.c
+  addvsi3.c
+  addvti3.c
+  apple_versioning.c
+  ashldi3.c
+  ashlti3.c
+  ashrdi3.c
+  ashrti3.c
+  bswapdi2.c
+  bswapsi2.c
+  clzdi2.c
+  clzsi2.c
+  clzti2.c
+  cmpdi2.c
+  cmpti2.c
+  comparedf2.c
+  comparesf2.c
+  ctzdi2.c
+  ctzsi2.c
+  ctzti2.c
+  divdc3.c
+  divdf3.c
+  divdi3.c
+  divmoddi4.c
+  divmodsi4.c
+  divsc3.c
+  divsf3.c
+  divsi3.c
+  divtc3.c
+  divti3.c
+  divtf3.c
+  extendsfdf2.c
+  extendhfsf2.c
+  ffsdi2.c
+  ffssi2.c
+  ffsti2.c
+  fixdfdi.c
+  fixdfsi.c
+  fixdfti.c
+  fixsfdi.c
+  fixsfsi.c
+  fixsfti.c
+  fixunsdfdi.c
+  fixunsdfsi.c
+  fixunsdfti.c
+  fixunssfdi.c
+  fixunssfsi.c
+  fixunssfti.c
+  floatdidf.c
+  floatdisf.c
+  floatsidf.c
+  floatsisf.c
+  floattidf.c
+  floattisf.c
+  floatundidf.c
+  floatundisf.c
+  floatunsidf.c
+  floatunsisf.c
+  floatuntidf.c
+  floatuntisf.c
+  int_util.c
+  lshrdi3.c
+  lshrti3.c
+  moddi3.c
+  modsi3.c
+  modti3.c
+  muldc3.c
+  muldf3.c
+  muldi3.c
+  mulodi4.c
+  mulosi4.c
+  muloti4.c
+  mulsc3.c
+  mulsf3.c
+  multi3.c
+  multf3.c
+  mulvdi3.c
+  mulvsi3.c
+  mulvti3.c
+  negdf2.c
+  negdi2.c
+  negsf2.c
+  negti2.c
+  negvdi2.c
+  negvsi2.c
+  negvti2.c
+  os_version_check.c
+  paritydi2.c
+  paritysi2.c
+  parityti2.c
+  popcountdi2.c
+  popcountsi2.c
+  popcountti2.c
+  powidf2.c
+  powisf2.c
+  powitf2.c
+  subdf3.c
+  subsf3.c
+  subvdi3.c
+  subvsi3.c
+  subvti3.c
+  subtf3.c
+  trampoline_setup.c
+  truncdfhf2.c
+  truncdfsf2.c
+  truncsfhf2.c
+  ucmpdi2.c
+  ucmpti2.c
+  udivdi3.c
+  udivmoddi4.c
+  udivmodsi4.c
+  udivmodti4.c
+  udivsi3.c
+  udivti3.c
+  umoddi3.c
+  umodsi3.c
+  umodti3.c
+)
+
+set(GENERIC_TF_SOURCES
+  comparetf2.c
+  extenddftf2.c
+  extendsftf2.c
+  fixtfdi.c
+  fixtfsi.c
+  fixtfti.c
+  fixunstfdi.c
+  fixunstfsi.c
+  fixunstfti.c
+  floatditf.c
+  floatsitf.c
+  floattitf.c
+  floatunditf.c
+  floatunsitf.c
+  floatuntitf.c
+  multc3.c
+  trunctfdf2.c
+  trunctfsf2.c
+)
+
+option(COMPILER_RT_EXCLUDE_ATOMIC_BUILTIN
+  "Skip the atomic builtin (these should normally be provided by a shared library)"
+  On)
+
+if(NOT FUCHSIA AND NOT COMPILER_RT_BAREMETAL_BUILD)
+  set(GENERIC_SOURCES
+    ${GENERIC_SOURCES}
+    emutls.c
+    enable_execute_stack.c
+    eprintf.c
+  )
+endif()
+
+if(COMPILER_RT_HAS_ATOMIC_KEYWORD AND NOT COMPILER_RT_EXCLUDE_ATOMIC_BUILTIN)
+  set(GENERIC_SOURCES
+    ${GENERIC_SOURCES}
+    atomic.c
+  )
+endif()
+
+if(APPLE)
+  set(GENERIC_SOURCES
+    ${GENERIC_SOURCES}
+    atomic_flag_clear.c
+    atomic_flag_clear_explicit.c
+    atomic_flag_test_and_set.c
+    atomic_flag_test_and_set_explicit.c
+    atomic_signal_fence.c
+    atomic_thread_fence.c
+  )
+endif()
+
+if (HAVE_UNWIND_H)
+  set(GENERIC_SOURCES
+    ${GENERIC_SOURCES}
+    gcc_personality_v0.c
+  )
+endif ()
+
+if (NOT FUCHSIA)
+  set(GENERIC_SOURCES
+    ${GENERIC_SOURCES}
+    clear_cache.c
+  )
+endif()
+
+# These sources work on all x86 variants, but only x86 variants.
+set(x86_ARCH_SOURCES
+  cpu_model.c
+  divxc3.c
+  fixxfdi.c
+  fixxfti.c
+  fixunsxfdi.c
+  fixunsxfsi.c
+  fixunsxfti.c
+  floatdixf.c
+  floattixf.c
+  floatundixf.c
+  floatuntixf.c
+  mulxc3.c
+  powixf2.c
+)
+
+if (NOT MSVC)
+  set(x86_64_SOURCES
+    ${GENERIC_TF_SOURCES}
+    x86_64/floatdidf.c
+    x86_64/floatdisf.c
+    x86_64/floatdixf.c
+    x86_64/floatundidf.S
+    x86_64/floatundisf.S
+    x86_64/floatundixf.S
+  )
+  filter_builtin_sources(x86_64_SOURCES EXCLUDE x86_64_SOURCES "${x86_64_SOURCES};${GENERIC_SOURCES}")
+  set(x86_64h_SOURCES ${x86_64_SOURCES})
+
+  if (WIN32)
+    set(x86_64_SOURCES
+      ${x86_64_SOURCES}
+      x86_64/chkstk.S
+      x86_64/chkstk2.S
+    )
+  endif()
+
+  set(i386_SOURCES
+    i386/ashldi3.S
+    i386/ashrdi3.S
+    i386/divdi3.S
+    i386/floatdidf.S
+    i386/floatdisf.S
+    i386/floatdixf.S
+    i386/floatundidf.S
+    i386/floatundisf.S
+    i386/floatundixf.S
+    i386/lshrdi3.S
+    i386/moddi3.S
+    i386/muldi3.S
+    i386/udivdi3.S
+    i386/umoddi3.S
+  )
+  filter_builtin_sources(i386_SOURCES EXCLUDE i386_SOURCES "${i386_SOURCES};${GENERIC_SOURCES}")
+
+  if (WIN32)
+    set(i386_SOURCES
+      ${i386_SOURCES}
+      i386/chkstk.S
+      i386/chkstk2.S
+    )
+  endif()
+else () # MSVC
+  # Use C versions of functions when building on MSVC
+  # MSVC's assembler takes Intel syntax, not AT&T syntax.
+  # Also use only MSVC compilable builtin implementations.
+  set(x86_64_SOURCES
+    x86_64/floatdidf.c
+    x86_64/floatdisf.c
+    x86_64/floatdixf.c
+    ${GENERIC_SOURCES}
+  )
+  set(x86_64h_SOURCES ${x86_64_SOURCES})
+  set(i386_SOURCES ${GENERIC_SOURCES})
+endif () # if (NOT MSVC)
+
+set(x86_64h_SOURCES ${x86_64h_SOURCES} ${x86_ARCH_SOURCES})
+set(x86_64_SOURCES ${x86_64_SOURCES} ${x86_ARCH_SOURCES})
+set(i386_SOURCES ${i386_SOURCES} ${x86_ARCH_SOURCES})
+set(i686_SOURCES ${i686_SOURCES} ${x86_ARCH_SOURCES})
+
+set(arm_SOURCES
+  arm/bswapdi2.S
+  arm/bswapsi2.S
+  arm/clzdi2.S
+  arm/clzsi2.S
+  arm/comparesf2.S
+  arm/divmodsi4.S
+  arm/divsi3.S
+  arm/modsi3.S
+  arm/sync_fetch_and_add_4.S
+  arm/sync_fetch_and_add_8.S
+  arm/sync_fetch_and_and_4.S
+  arm/sync_fetch_and_and_8.S
+  arm/sync_fetch_and_max_4.S
+  arm/sync_fetch_and_max_8.S
+  arm/sync_fetch_and_min_4.S
+  arm/sync_fetch_and_min_8.S
+  arm/sync_fetch_and_nand_4.S
+  arm/sync_fetch_and_nand_8.S
+  arm/sync_fetch_and_or_4.S
+  arm/sync_fetch_and_or_8.S
+  arm/sync_fetch_and_sub_4.S
+  arm/sync_fetch_and_sub_8.S
+  arm/sync_fetch_and_umax_4.S
+  arm/sync_fetch_and_umax_8.S
+  arm/sync_fetch_and_umin_4.S
+  arm/sync_fetch_and_umin_8.S
+  arm/sync_fetch_and_xor_4.S
+  arm/sync_fetch_and_xor_8.S
+  arm/udivmodsi4.S
+  arm/udivsi3.S
+  arm/umodsi3.S
+)
+filter_builtin_sources(arm_SOURCES EXCLUDE arm_SOURCES "${arm_SOURCES};${GENERIC_SOURCES}")
+
+set(thumb1_SOURCES
+  arm/divsi3.S
+  arm/udivsi3.S
+  arm/comparesf2.S
+  arm/addsf3.S
+  ${GENERIC_SOURCES}
+)
+
+set(arm_EABI_SOURCES
+  arm/aeabi_cdcmp.S
+  arm/aeabi_cdcmpeq_check_nan.c
+  arm/aeabi_cfcmp.S
+  arm/aeabi_cfcmpeq_check_nan.c
+  arm/aeabi_dcmp.S
+  arm/aeabi_div0.c
+  arm/aeabi_drsub.c
+  arm/aeabi_fcmp.S
+  arm/aeabi_frsub.c
+  arm/aeabi_idivmod.S
+  arm/aeabi_ldivmod.S
+  arm/aeabi_memcmp.S
+  arm/aeabi_memcpy.S
+  arm/aeabi_memmove.S
+  arm/aeabi_memset.S
+  arm/aeabi_uidivmod.S
+  arm/aeabi_uldivmod.S
+)
+
+set(arm_Thumb1_JT_SOURCES
+  arm/switch16.S
+  arm/switch32.S
+  arm/switch8.S
+  arm/switchu8.S
+)
+set(arm_Thumb1_SjLj_EH_SOURCES
+  arm/restore_vfp_d8_d15_regs.S
+  arm/save_vfp_d8_d15_regs.S
+)
+set(arm_Thumb1_VFPv2_SOURCES
+  arm/adddf3vfp.S
+  arm/addsf3vfp.S
+  arm/divdf3vfp.S
+  arm/divsf3vfp.S
+  arm/eqdf2vfp.S
+  arm/eqsf2vfp.S
+  arm/extendsfdf2vfp.S
+  arm/fixdfsivfp.S
+  arm/fixsfsivfp.S
+  arm/fixunsdfsivfp.S
+  arm/fixunssfsivfp.S
+  arm/floatsidfvfp.S
+  arm/floatsisfvfp.S
+  arm/floatunssidfvfp.S
+  arm/floatunssisfvfp.S
+  arm/gedf2vfp.S
+  arm/gesf2vfp.S
+  arm/gtdf2vfp.S
+  arm/gtsf2vfp.S
+  arm/ledf2vfp.S
+  arm/lesf2vfp.S
+  arm/ltdf2vfp.S
+  arm/ltsf2vfp.S
+  arm/muldf3vfp.S
+  arm/mulsf3vfp.S
+  arm/nedf2vfp.S
+  arm/negdf2vfp.S
+  arm/negsf2vfp.S
+  arm/nesf2vfp.S
+  arm/subdf3vfp.S
+  arm/subsf3vfp.S
+  arm/truncdfsf2vfp.S
+  arm/unorddf2vfp.S
+  arm/unordsf2vfp.S
+)
+set(arm_Thumb1_icache_SOURCES
+  arm/sync_synchronize.S
+)
+set(arm_Thumb1_SOURCES
+  ${arm_Thumb1_JT_SOURCES}
+  ${arm_Thumb1_SjLj_EH_SOURCES}
+  ${arm_Thumb1_VFPv2_SOURCES}
+  ${arm_Thumb1_icache_SOURCES}
+)
+
+if(MINGW)
+  set(arm_SOURCES
+    arm/aeabi_idivmod.S
+    arm/aeabi_ldivmod.S
+    arm/aeabi_uidivmod.S
+    arm/aeabi_uldivmod.S
+    arm/chkstk.S
+    mingw_fixfloat.c
+  )
+  filter_builtin_sources(arm_SOURCES EXCLUDE arm_SOURCES "${arm_SOURCES};${GENERIC_SOURCES}")
+elseif(NOT WIN32)
+  # TODO the EABI sources should only be added to EABI targets
+  set(arm_SOURCES
+    ${arm_SOURCES}
+    ${arm_EABI_SOURCES}
+    ${arm_Thumb1_SOURCES}
+  )
+
+  set(thumb1_SOURCES
+    ${thumb1_SOURCES}
+    ${arm_EABI_SOURCES}
+  )
+endif()
+
+set(aarch64_SOURCES
+  ${GENERIC_TF_SOURCES}
+  ${GENERIC_SOURCES}
+)
+
+if (MINGW)
+  set(aarch64_SOURCES
+    ${aarch64_SOURCES}
+    aarch64/chkstk.S
+  )
+endif()
+
+set(armhf_SOURCES ${arm_SOURCES})
+set(armv7_SOURCES ${arm_SOURCES})
+set(armv7s_SOURCES ${arm_SOURCES})
+set(armv7k_SOURCES ${arm_SOURCES})
+set(arm64_SOURCES ${aarch64_SOURCES})
+
+# macho_embedded archs
+set(armv6m_SOURCES ${thumb1_SOURCES})
+set(armv7m_SOURCES ${arm_SOURCES})
+set(armv7em_SOURCES ${arm_SOURCES})
+
+# hexagon arch
+set(hexagon_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+set(hexagon_SOURCES
+  hexagon/common_entry_exit_abi1.S
+  hexagon/common_entry_exit_abi2.S
+  hexagon/common_entry_exit_legacy.S
+  hexagon/dfaddsub.S
+  hexagon/dfdiv.S
+  hexagon/dffma.S
+  hexagon/dfminmax.S
+  hexagon/dfmul.S
+  hexagon/dfsqrt.S
+  hexagon/divdi3.S
+  hexagon/divsi3.S
+  hexagon/fabs_opt.S
+  hexagon/fastmath2_dlib_asm.S
+  hexagon/fastmath2_ldlib_asm.S
+  hexagon/fastmath_dlib_asm.S
+  hexagon/fma_opt.S
+  hexagon/fmax_opt.S
+  hexagon/fmin_opt.S
+  hexagon/memcpy_forward_vp4cp4n2.S
+  hexagon/memcpy_likely_aligned.S
+  hexagon/moddi3.S
+  hexagon/modsi3.S
+  hexagon/sfdiv_opt.S
+  hexagon/sfsqrt_opt.S
+  hexagon/udivdi3.S
+  hexagon/udivmoddi4.S
+  hexagon/udivmodsi4.S
+  hexagon/udivsi3.S
+  hexagon/umoddi3.S
+  hexagon/umodsi3.S
+)
+
+
+set(mips_SOURCES ${GENERIC_SOURCES})
+set(mipsel_SOURCES ${mips_SOURCES})
+set(mips64_SOURCES ${GENERIC_TF_SOURCES}
+                   ${mips_SOURCES})
+set(mips64el_SOURCES ${GENERIC_TF_SOURCES}
+                     ${mips_SOURCES})
+
+set(powerpc64_SOURCES
+  ppc/divtc3.c
+  ppc/fixtfdi.c
+  ppc/fixunstfti.c
+  ppc/fixunstfdi.c
+  ppc/floattitf.c
+  ppc/floatditf.c
+  ppc/floatunditf.c
+  ppc/gcc_qadd.c
+  ppc/gcc_qdiv.c
+  ppc/gcc_qmul.c
+  ppc/gcc_qsub.c
+  ppc/multc3.c
+  ${GENERIC_SOURCES}
+)
+set(powerpc64le_SOURCES ${powerpc64_SOURCES})
+
+set(riscv_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+set(riscv32_SOURCES
+  riscv/mulsi3.S
+  ${riscv_SOURCES}
+)
+set(riscv64_SOURCES ${riscv_SOURCES})
+
+set(sparc_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+set(sparcv9_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+
+set(wasm32_SOURCES
+  ${GENERIC_TF_SOURCES}
+  ${GENERIC_SOURCES}
+)
+set(wasm64_SOURCES
+  ${GENERIC_TF_SOURCES}
+  ${GENERIC_SOURCES}
+)
+
+add_custom_target(builtins)
+set_target_properties(builtins PROPERTIES FOLDER "Compiler-RT Misc")
+
+if (APPLE)
+  add_subdirectory(Darwin-excludes)
+  add_subdirectory(macho_embedded)
+  darwin_add_builtin_libraries(${BUILTIN_SUPPORTED_OS})
+else ()
+  set(BUILTIN_CFLAGS "")
+
+  append_list_if(COMPILER_RT_HAS_STD_C11_FLAG -std=c11 BUILTIN_CFLAGS)
+
+  # These flags would normally be added to CMAKE_C_FLAGS by the llvm
+  # cmake step. Add them manually if this is a standalone build.
+  if(COMPILER_RT_STANDALONE_BUILD)
+    append_list_if(COMPILER_RT_HAS_FPIC_FLAG -fPIC BUILTIN_CFLAGS)
+    append_list_if(COMPILER_RT_HAS_FNO_BUILTIN_FLAG -fno-builtin BUILTIN_CFLAGS)
+    if(NOT ANDROID)
+      append_list_if(COMPILER_RT_HAS_VISIBILITY_HIDDEN_FLAG -fvisibility=hidden BUILTIN_CFLAGS)
+    endif()
+    if(NOT COMPILER_RT_DEBUG)
+      append_list_if(COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG -fomit-frame-pointer BUILTIN_CFLAGS)
+    endif()
+  endif()
+
+  set(BUILTIN_DEFS "")
+
+  if(NOT ANDROID)
+    append_list_if(COMPILER_RT_HAS_VISIBILITY_HIDDEN_FLAG VISIBILITY_HIDDEN BUILTIN_DEFS)
+  endif()
+
+  foreach (arch ${BUILTIN_SUPPORTED_ARCH})
+    if (CAN_TARGET_${arch})
+      # NOTE: some architectures (e.g. i386) have multiple names.  Ensure that
+      # we catch them all.
+      set(_arch ${arch})
+      if("${arch}" STREQUAL "armv6m")
+        set(_arch "arm|armv6m")
+      elseif("${arch}" MATCHES "^(armhf|armv7|armv7s|armv7k|armv7m|armv7em)$")
+        set(_arch "arm")
+      endif()
+
+      # For ARM archs, exclude any VFP builtins if VFP is not supported
+      if (${arch} MATCHES "^(arm|armhf|armv7|armv7s|armv7k|armv7m|armv7em)$")
+        string(REPLACE ";" " " _TARGET_${arch}_CFLAGS "${TARGET_${arch}_CFLAGS}")
+        check_compile_definition(__VFP_FP__ "${CMAKE_C_FLAGS} ${_TARGET_${arch}_CFLAGS}" COMPILER_RT_HAS_${arch}_VFP)
+        if(NOT COMPILER_RT_HAS_${arch}_VFP)
+          list(REMOVE_ITEM ${arch}_SOURCES ${arm_Thumb1_VFPv2_SOURCES} ${arm_Thumb1_SjLj_EH_SOURCES})
+        endif()
+      endif()
+
+      # Filter out generic versions of routines that are re-implemented in
+      # architecture specific manner.  This prevents multiple definitions of the
+      # same symbols, making the symbol selection non-deterministic.
+      foreach (_file ${${arch}_SOURCES})
+        if (${_file} MATCHES ${_arch}/*)
+          get_filename_component(_name ${_file} NAME)
+          string(REPLACE ".S" ".c" _cname "${_name}")
+          list(REMOVE_ITEM ${arch}_SOURCES ${_cname})
+        endif ()
+      endforeach ()
+
+      # Needed for clear_cache on debug mode, due to r7's usage in inline asm.
+      # Release mode already sets it via -O2/3, Debug mode doesn't.
+      if (${arch} STREQUAL "armhf")
+        list(APPEND BUILTIN_CFLAGS -fomit-frame-pointer -DCOMPILER_RT_ARMHF_TARGET)
+      endif()
+
+      # For RISCV32, we must force enable int128 for compiling long
+      # double routines.
+      if("${arch}" STREQUAL "riscv32")
+        list(APPEND BUILTIN_CFLAGS -fforce-enable-int128)
+      endif()
+
+      add_compiler_rt_runtime(clang_rt.builtins
+                              STATIC
+                              ARCHS ${arch}
+                              SOURCES ${${arch}_SOURCES}
+                              DEFS ${BUILTIN_DEFS}
+                              CFLAGS ${BUILTIN_CFLAGS}
+                              PARENT_TARGET builtins)
+    endif ()
+  endforeach ()
+endif ()
+
+add_dependencies(compiler-rt builtins)
index 2d0261b..1b2d050 100644 (file)
@@ -21,12 +21,20 @@ let
     "addvdi3.c",
     "addvsi3.c",
     "addvti3.c",
+    "apple_versioning.c",
     "ashldi3.c",
     "ashlti3.c",
     "ashrdi3.c",
     "ashrti3.c",
-    -- FIXME: This requires C11 _Atomic
-    -- atomic.c
+    --"atomic.c",
+    --"atomic_flag_clear.c",
+    --"atomic_flag_clear_explicit.c",
+    --"atomic_flag_test_and_set.c",
+    --"atomic_flag_test_and_set_explicit.c",
+    --"atomic_signal_fence.c",
+    --"atomic_thread_fence.c",
+    "bswapdi2.c",
+    "bswapsi2.c",
     "clear_cache.c",
     "clzdi2.c",
     "clzsi2.c",
@@ -35,6 +43,8 @@ let
     "cmpti2.c",
     "comparedf2.c",
     "comparesf2.c",
+    "comparetf2.c",
+    "cpu_model.c",
     "ctzdi2.c",
     "ctzsi2.c",
     "ctzti2.c",
@@ -46,15 +56,19 @@ let
     "divsc3.c",
     "divsf3.c",
     "divsi3.c",
-    -- GCC has conflicting types with built-in __divtc3
-    -- "divtc3.c",
-    "divti3.c",
+    -- "divtc3.c",   // error: conflicting types for built-in function '__divtc3' [-Werror=builtin-declaration-mismatch]
     "divtf3.c",
+    "divti3.c",
     "divxc3.c",
-    "enable_execute_stack.c",
-    "extendsfdf2.c",
+    "emutls.c",
+    -- "enable_execute_stack.c",
+    "eprintf.c",
+    "extenddftf2.c",
     "extendhfsf2.c",
+    "extendsfdf2.c",
+    "extendsftf2.c",
     "ffsdi2.c",
+    "ffssi2.c",
     "ffsti2.c",
     "fixdfdi.c",
     "fixdfsi.c",
@@ -62,12 +76,18 @@ let
     "fixsfdi.c",
     "fixsfsi.c",
     "fixsfti.c",
+    "fixtfdi.c",
+    "fixtfsi.c",
+    "fixtfti.c",
     "fixunsdfdi.c",
     "fixunsdfsi.c",
     "fixunsdfti.c",
     "fixunssfdi.c",
     "fixunssfsi.c",
     "fixunssfti.c",
+    "fixunstfdi.c",
+    "fixunstfsi.c",
+    "fixunstfti.c",
     "fixunsxfdi.c",
     "fixunsxfsi.c",
     "fixunsxfti.c",
@@ -75,23 +95,31 @@ let
     "fixxfti.c",
     "floatdidf.c",
     "floatdisf.c",
+    "floatditf.c",
     "floatdixf.c",
     "floatsidf.c",
     "floatsisf.c",
+    "floatsitf.c",
     "floattidf.c",
     "floattisf.c",
+    "floattitf.c",
     "floattixf.c",
     "floatundidf.c",
     "floatundisf.c",
+    "floatunditf.c",
     "floatundixf.c",
     "floatunsidf.c",
     "floatunsisf.c",
+    "floatunsitf.c",
     "floatuntidf.c",
     "floatuntisf.c",
+    "floatuntitf.c",
     "floatuntixf.c",
+    -- "gcc_personality_v0.c",
     "int_util.c",
     "lshrdi3.c",
     "lshrti3.c",
+    "mingw_fixfloat.c",
     "moddi3.c",
     "modsi3.c",
     "modti3.c",
@@ -103,8 +131,9 @@ let
     "muloti4.c",
     "mulsc3.c",
     "mulsf3.c",
-    "multi3.c",
+    -- "multc3.c",  error: conflicting types for built-in function '__multc3' [-Werror=builtin-declaration-mismatch]
     "multf3.c",
+    "multi3.c",
     "mulvdi3.c",
     "mulvsi3.c",
     "mulvti3.c",
@@ -116,6 +145,7 @@ let
     "negvdi2.c",
     "negvsi2.c",
     "negvti2.c",
+    "os_version_check.c",
     "paritydi2.c",
     "paritysi2.c",
     "parityti2.c",
@@ -128,14 +158,16 @@ let
     "powixf2.c",
     "subdf3.c",
     "subsf3.c",
+    "subtf3.c",
     "subvdi3.c",
     "subvsi3.c",
     "subvti3.c",
-    "subtf3.c",
     "trampoline_setup.c",
     "truncdfhf2.c",
     "truncdfsf2.c",
     "truncsfhf2.c",
+    "trunctfdf2.c",
+    "trunctfsf2.c",
     "ucmpdi2.c",
     "ucmpti2.c",
     "udivdi3.c",
@@ -223,7 +255,9 @@ let
         "arm/sync_fetch_and_xor_4.S",
         "arm/sync_fetch_and_xor_8.S"
         ]
-    "armv8" -> [ ]
+    "armv8" -> [
+        "aarch64/chkstk.S"
+        ]
     x -> error ("Unknown architecture for compiler-rt: " ++ x)
 
   builtins_c_arch arch = case arch of
@@ -238,24 +272,13 @@ let
         "arm/aeabi_cfcmpeq_check_nan.c",
         "arm/aeabi_div0.c",
         "arm/aeabi_drsub.c",
-        "arm/aeabi_frsub.c" ]
+        "arm/aeabi_frsub.c",
+        "divtc3.c",
+        "multc3.c" ]
     "armv8" -> [
-        "comparetf2.c",
-        "extenddftf2.c",
-        "extendsftf2.c",
-        "fixtfdi.c",
-        "fixtfsi.c",
-        "fixtfti.c",
-        "fixunstfdi.c",
-        "fixunstfsi.c",
-        "fixunstfti.c",
-        "floatditf.c",
-        "floatsitf.c",
-        "floatunditf.c",
-        "floatunsitf.c",
-        "multc3.c",
-        "trunctfdf2.c",
-        "trunctfsf2.c" ]
+        "divtc3.c",
+        "multc3.c"
+     ]
     x -> error ("Unknown architecture for compiler-rt: " ++ x)
 
   common_cFlags = [
index ad36e4e..e603dfa 100644 (file)
@@ -45,6 +45,7 @@ si_int __ctzsi2(si_int a);  // count trailing zeros
 si_int __ctzdi2(di_int a);  // count trailing zeros
 si_int __ctzti2(ti_int a);  // count trailing zeros
 
+si_int __ffssi2(si_int a);  // find least significant 1 bit
 si_int __ffsdi2(di_int a);  // find least significant 1 bit
 si_int __ffsti2(ti_int a);  // find least significant 1 bit
 
@@ -56,8 +57,8 @@ si_int __popcountsi2(si_int a);  // bit population
 si_int __popcountdi2(di_int a);  // bit population
 si_int __popcountti2(ti_int a);  // bit population
 
-uint32_t __bswapsi2(uint32_t a);   // a byteswapped, arm only
-uint64_t __bswapdi2(uint64_t a);   // a byteswapped, arm only
+uint32_t __bswapsi2(uint32_t a);   // a byteswapped
+uint64_t __bswapdi2(uint64_t a);   // a byteswapped
 
 // Integral arithmetic
 
diff --git a/lib/compiler-rt/builtins/aarch64/chkstk.S b/lib/compiler-rt/builtins/aarch64/chkstk.S
new file mode 100644 (file)
index 0000000..01f9036
--- /dev/null
@@ -0,0 +1,35 @@
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+#include "../assembly.h"
+
+// __chkstk routine
+// This routine is windows specific.
+// http://msdn.microsoft.com/en-us/library/ms648426.aspx
+
+// This clobbers registers x16 and x17.
+// Does not modify any memory or the stack pointer.
+
+//      mov     x15, #256 // Number of bytes of stack, in units of 16 byte
+//      bl      __chkstk
+//      sub     sp, sp, x15, lsl #4
+
+#ifdef __aarch64__
+
+#define PAGE_SIZE 4096
+
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__chkstk)
+        lsl    x16, x15, #4
+        mov    x17, sp
+1:
+        sub    x17, x17, #PAGE_SIZE
+        subs   x16, x16, #PAGE_SIZE
+        ldr    xzr, [x17]
+        b.gt   1b
+
+        ret
+END_COMPILERRT_FUNCTION(__chkstk)
+
+#endif // __aarch64__
index 682c235..b9566cd 100644 (file)
@@ -1,29 +1,25 @@
-/*===-- absvdi2.c - Implement __absvdi2 -----------------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===
- *
- * This file implements __absvdi2 for the compiler_rt library.
- *
- *===----------------------------------------------------------------------===
- */
+//===-- absvdi2.c - Implement __absvdi2 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __absvdi2 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
-/* Returns: absolute value */
+// Returns: absolute value
 
-/* Effects: aborts if abs(x) < 0 */
+// Effects: aborts if abs(x) < 0
 
-COMPILER_RT_ABI di_int
-__absvdi2(di_int a)
-{
-    const int N = (int)(sizeof(di_int) * CHAR_BIT);
-    if (a == ((di_int)1 << (N-1)))
-        compilerrt_abort();
-    const di_int t = a >> (N - 1);
-    return (a ^ t) - t;
+COMPILER_RT_ABI di_int __absvdi2(di_int a) {
+  const int N = (int)(sizeof(di_int) * CHAR_BIT);
+  if (a == ((di_int)1 << (N - 1)))
+    compilerrt_abort();
+  const di_int t = a >> (N - 1);
+  return (a ^ t) - t;
 }
index 4812af8..44ada16 100644 (file)
@@ -1,29 +1,25 @@
-/* ===-- absvsi2.c - Implement __absvsi2 -----------------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __absvsi2 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- absvsi2.c - Implement __absvsi2 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __absvsi2 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
-/* Returns: absolute value */
+// Returns: absolute value
 
-/* Effects: aborts if abs(x) < 0 */
+// Effects: aborts if abs(x) < 0
 
-COMPILER_RT_ABI si_int
-__absvsi2(si_int a)
-{
-    const int N = (int)(sizeof(si_int) * CHAR_BIT);
-    if (a == (1 << (N-1)))
-        compilerrt_abort();
-    const si_int t = a >> (N - 1);
-    return (a ^ t) - t;
+COMPILER_RT_ABI si_int __absvsi2(si_int a) {
+  const int N = (int)(sizeof(si_int) * CHAR_BIT);
+  if (a == (1 << (N - 1)))
+    compilerrt_abort();
+  const si_int t = a >> (N - 1);
+  return (a ^ t) - t;
 }
index 7927770..491d99d 100644 (file)
@@ -1,34 +1,29 @@
-/* ===-- absvti2.c - Implement __absvdi2 -----------------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __absvti2 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- absvti2.c - Implement __absvdi2 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __absvti2 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
 #ifdef CRT_HAS_128BIT
 
-/* Returns: absolute value */
+// Returns: absolute value
 
-/* Effects: aborts if abs(x) < 0 */
+// Effects: aborts if abs(x) < 0
 
-COMPILER_RT_ABI ti_int
-__absvti2(ti_int a)
-{
-    const int N = (int)(sizeof(ti_int) * CHAR_BIT);
-    if (a == ((ti_int)1 << (N-1)))
-        compilerrt_abort();
-    const ti_int s = a >> (N - 1);
-    return (a ^ s) - s;
+COMPILER_RT_ABI ti_int __absvti2(ti_int a) {
+  const int N = (int)(sizeof(ti_int) * CHAR_BIT);
+  if (a == ((ti_int)1 << (N - 1)))
+    compilerrt_abort();
+  const ti_int s = a >> (N - 1);
+  return (a ^ s) - s;
 }
 
-#endif /* CRT_HAS_128BIT */
-
+#endif // CRT_HAS_128BIT
index 8b7aae0..f2727fa 100644 (file)
@@ -1,9 +1,8 @@
 //===-- lib/adddf3.c - Double-precision addition ------------------*- C -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 #define DOUBLE_PRECISION
 #include "fp_add_impl.inc"
 
-ARM_EABI_FNALIAS(dadd, adddf3)
+COMPILER_RT_ABI double __adddf3(double a, double b) { return __addXf3__(a, b); }
 
-COMPILER_RT_ABI double __adddf3(double a, double b){
-    return __addXf3__(a, b);
-}
+#if defined(__ARM_EABI__)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+AEABI_RTABI double __aeabi_dadd(double a, double b) { return __adddf3(a, b); }
+#else
+COMPILER_RT_ALIAS(__adddf3, __aeabi_dadd)
+#endif
+#endif
index 0f5d6ea..8fe8622 100644 (file)
@@ -1,9 +1,8 @@
 //===-- lib/addsf3.c - Single-precision addition ------------------*- C -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 #define SINGLE_PRECISION
 #include "fp_add_impl.inc"
 
-ARM_EABI_FNALIAS(fadd, addsf3)
+COMPILER_RT_ABI float __addsf3(float a, float b) { return __addXf3__(a, b); }
 
-COMPILER_RT_ABI float __addsf3(float a, float b) {
-    return __addXf3__(a, b);
-}
+#if defined(__ARM_EABI__)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+AEABI_RTABI float __aeabi_fadd(float a, float b) { return __addsf3(a, b); }
+#else
+COMPILER_RT_ALIAS(__addsf3, __aeabi_fadd)
+#endif
+#endif
index e4bbe02..570472a 100644 (file)
@@ -1,9 +1,8 @@
 //===-- lib/addtf3.c - Quad-precision addition --------------------*- C -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
@@ -18,8 +17,8 @@
 #if defined(CRT_HAS_128BIT) && defined(CRT_LDBL_128BIT)
 #include "fp_add_impl.inc"
 
-COMPILER_RT_ABI long double __addtf3(long double a, long double b){
-    return __addXf3__(a, b);
+COMPILER_RT_ABI long double __addtf3(long double a, long double b) {
+  return __addXf3__(a, b);
 }
 
 #endif
index 0da3894..28661fd 100644 (file)
@@ -1,36 +1,29 @@
-/* ===-- addvdi3.c - Implement __addvdi3 -----------------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __addvdi3 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- addvdi3.c - Implement __addvdi3 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __addvdi3 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
-/* Returns: a + b */
+// Returns: a + b
 
-/* Effects: aborts if a + b overflows */
+// Effects: aborts if a + b overflows
 
-COMPILER_RT_ABI di_int
-__addvdi3(di_int a, di_int b)
-{
-    di_int s = (du_int) a + (du_int) b;
-    if (b >= 0)
-    {
-        if (s < a)
-            compilerrt_abort();
-    }
-    else
-    {
-        if (s >= a)
-            compilerrt_abort();
-    }
-    return s;
+COMPILER_RT_ABI di_int __addvdi3(di_int a, di_int b) {
+  di_int s = (du_int)a + (du_int)b;
+  if (b >= 0) {
+    if (s < a)
+      compilerrt_abort();
+  } else {
+    if (s >= a)
+      compilerrt_abort();
+  }
+  return s;
 }
index 94ca726..4040023 100644 (file)
@@ -1,36 +1,29 @@
-/* ===-- addvsi3.c - Implement __addvsi3 -----------------------------------===
- *
- *                    The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __addvsi3 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- addvsi3.c - Implement __addvsi3 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __addvsi3 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
-/* Returns: a + b */
+// Returns: a + b
 
-/* Effects: aborts if a + b overflows */
+// Effects: aborts if a + b overflows
 
-COMPILER_RT_ABI si_int
-__addvsi3(si_int a, si_int b)
-{
-    si_int s = (su_int) a + (su_int) b;
-    if (b >= 0)
-    {
-        if (s < a)
-            compilerrt_abort();
-    }
-    else
-    {
-        if (s >= a)
-            compilerrt_abort();
-    }
-    return s;
+COMPILER_RT_ABI si_int __addvsi3(si_int a, si_int b) {
+  si_int s = (su_int)a + (su_int)b;
+  if (b >= 0) {
+    if (s < a)
+      compilerrt_abort();
+  } else {
+    if (s >= a)
+      compilerrt_abort();
+  }
+  return s;
 }
index c224de6..aa70987 100644 (file)
@@ -1,40 +1,33 @@
-/* ===-- addvti3.c - Implement __addvti3 -----------------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __addvti3 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- addvti3.c - Implement __addvti3 -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements __addvti3 for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 
 #ifdef CRT_HAS_128BIT
 
-/* Returns: a + b */
+// Returns: a + b
 
-/* Effects: aborts if a + b overflows */
+// Effects: aborts if a + b overflows
 
-COMPILER_RT_ABI ti_int
-__addvti3(ti_int a, ti_int b)
-{
-    ti_int s = (tu_int) a + (tu_int) b;
-    if (b >= 0)
-    {
-        if (s < a)
-            compilerrt_abort();
-    }
-    else
-    {
-        if (s >= a)
-            compilerrt_abort();
-    }
-    return s;
+COMPILER_RT_ABI ti_int __addvti3(ti_int a, ti_int b) {
+  ti_int s = (tu_int)a + (tu_int)b;
+  if (b >= 0) {
+    if (s < a)
+      compilerrt_abort();
+  } else {
+    if (s >= a)
+      compilerrt_abort();
+  }
+  return s;
 }
 
-#endif /* CRT_HAS_128BIT */
+#endif // CRT_HAS_128BIT
diff --git a/lib/compiler-rt/builtins/apple_versioning.c b/lib/compiler-rt/builtins/apple_versioning.c
new file mode 100644 (file)
index 0000000..f87b428
--- /dev/null
@@ -0,0 +1,339 @@
+//===-- apple_versioning.c - Adds versioning symbols for ld ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#if __APPLE__
+#include <Availability.h>
+
+#if __IPHONE_OS_VERSION_MIN_REQUIRED
+#define NOT_HERE_BEFORE_10_6(sym)
+#define NOT_HERE_IN_10_8_AND_EARLIER(sym)                                      \
+  extern const char sym##_tmp61 __asm("$ld$hide$os6.1$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp61 = 0;           \
+  extern const char sym##_tmp60 __asm("$ld$hide$os6.0$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp60 = 0;           \
+  extern const char sym##_tmp51 __asm("$ld$hide$os5.1$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp51 = 0;           \
+  extern const char sym##_tmp50 __asm("$ld$hide$os5.0$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp50 = 0;
+#else
+#define NOT_HERE_BEFORE_10_6(sym)                                              \
+  extern const char sym##_tmp4 __asm("$ld$hide$os10.4$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp4 = 0;            \
+  extern const char sym##_tmp5 __asm("$ld$hide$os10.5$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp5 = 0;
+#define NOT_HERE_IN_10_8_AND_EARLIER(sym)                                      \
+  extern const char sym##_tmp8 __asm("$ld$hide$os10.8$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp8 = 0;            \
+  extern const char sym##_tmp7 __asm("$ld$hide$os10.7$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp7 = 0;            \
+  extern const char sym##_tmp6 __asm("$ld$hide$os10.6$_" #sym);                \
+  __attribute__((visibility("default"))) const char sym##_tmp6 = 0;
+#endif
+
+// Symbols in libSystem.dylib in 10.6 and later,
+//  but are in libgcc_s.dylib in earlier versions
+
+NOT_HERE_BEFORE_10_6(__absvdi2)
+NOT_HERE_BEFORE_10_6(__absvsi2)
+NOT_HERE_BEFORE_10_6(__absvti2)
+NOT_HERE_BEFORE_10_6(__addvdi3)
+NOT_HERE_BEFORE_10_6(__addvsi3)
+NOT_HERE_BEFORE_10_6(__addvti3)
+NOT_HERE_BEFORE_10_6(__ashldi3)
+NOT_HERE_BEFORE_10_6(__ashlti3)
+NOT_HERE_BEFORE_10_6(__ashrdi3)
+NOT_HERE_BEFORE_10_6(__ashrti3)
+NOT_HERE_BEFORE_10_6(__clear_cache)
+NOT_HERE_BEFORE_10_6(__clzdi2)
+NOT_HERE_BEFORE_10_6(__clzsi2)
+NOT_HERE_BEFORE_10_6(__clzti2)
+NOT_HERE_BEFORE_10_6(__cmpdi2)
+NOT_HERE_BEFORE_10_6(__cmpti2)
+NOT_HERE_BEFORE_10_6(__ctzdi2)
+NOT_HERE_BEFORE_10_6(__ctzsi2)
+NOT_HERE_BEFORE_10_6(__ctzti2)
+NOT_HERE_BEFORE_10_6(__divdc3)
+NOT_HERE_BEFORE_10_6(__divdi3)
+NOT_HERE_BEFORE_10_6(__divsc3)
+NOT_HERE_BEFORE_10_6(__divtc3)
+NOT_HERE_BEFORE_10_6(__divti3)
+NOT_HERE_BEFORE_10_6(__divxc3)
+NOT_HERE_BEFORE_10_6(__enable_execute_stack)
+NOT_HERE_BEFORE_10_6(__ffsdi2)
+NOT_HERE_BEFORE_10_6(__ffsti2)
+NOT_HERE_BEFORE_10_6(__fixdfdi)
+NOT_HERE_BEFORE_10_6(__fixdfti)
+NOT_HERE_BEFORE_10_6(__fixsfdi)
+NOT_HERE_BEFORE_10_6(__fixsfti)
+NOT_HERE_BEFORE_10_6(__fixtfdi)
+NOT_HERE_BEFORE_10_6(__fixunsdfdi)
+NOT_HERE_BEFORE_10_6(__fixunsdfsi)
+NOT_HERE_BEFORE_10_6(__fixunsdfti)
+NOT_HERE_BEFORE_10_6(__fixunssfdi)
+NOT_HERE_BEFORE_10_6(__fixunssfsi)
+NOT_HERE_BEFORE_10_6(__fixunssfti)
+NOT_HERE_BEFORE_10_6(__fixunstfdi)
+NOT_HERE_BEFORE_10_6(__fixunsxfdi)
+NOT_HERE_BEFORE_10_6(__fixunsxfsi)
+NOT_HERE_BEFORE_10_6(__fixunsxfti)
+NOT_HERE_BEFORE_10_6(__fixxfdi)
+NOT_HERE_BEFORE_10_6(__fixxfti)
+NOT_HERE_BEFORE_10_6(__floatdidf)
+NOT_HERE_BEFORE_10_6(__floatdisf)
+NOT_HERE_BEFORE_10_6(__floatditf)
+NOT_HERE_BEFORE_10_6(__floatdixf)
+NOT_HERE_BEFORE_10_6(__floattidf)
+NOT_HERE_BEFORE_10_6(__floattisf)
+NOT_HERE_BEFORE_10_6(__floattixf)
+NOT_HERE_BEFORE_10_6(__floatundidf)
+NOT_HERE_BEFORE_10_6(__floatundisf)
+NOT_HERE_BEFORE_10_6(__floatunditf)
+NOT_HERE_BEFORE_10_6(__floatundixf)
+NOT_HERE_BEFORE_10_6(__floatuntidf)
+NOT_HERE_BEFORE_10_6(__floatuntisf)
+NOT_HERE_BEFORE_10_6(__floatuntixf)
+NOT_HERE_BEFORE_10_6(__gcc_personality_v0)
+NOT_HERE_BEFORE_10_6(__lshrdi3)
+NOT_HERE_BEFORE_10_6(__lshrti3)
+NOT_HERE_BEFORE_10_6(__moddi3)
+NOT_HERE_BEFORE_10_6(__modti3)
+NOT_HERE_BEFORE_10_6(__muldc3)
+NOT_HERE_BEFORE_10_6(__muldi3)
+NOT_HERE_BEFORE_10_6(__mulsc3)
+NOT_HERE_BEFORE_10_6(__multc3)
+NOT_HERE_BEFORE_10_6(__multi3)
+NOT_HERE_BEFORE_10_6(__mulvdi3)
+NOT_HERE_BEFORE_10_6(__mulvsi3)
+NOT_HERE_BEFORE_10_6(__mulvti3)
+NOT_HERE_BEFORE_10_6(__mulxc3)
+NOT_HERE_BEFORE_10_6(__negdi2)
+NOT_HERE_BEFORE_10_6(__negti2)
+NOT_HERE_BEFORE_10_6(__negvdi2)
+NOT_HERE_BEFORE_10_6(__negvsi2)
+NOT_HERE_BEFORE_10_6(__negvti2)
+NOT_HERE_BEFORE_10_6(__paritydi2)
+NOT_HERE_BEFORE_10_6(__paritysi2)
+NOT_HERE_BEFORE_10_6(__parityti2)
+NOT_HERE_BEFORE_10_6(__popcountdi2)
+NOT_HERE_BEFORE_10_6(__popcountsi2)
+NOT_HERE_BEFORE_10_6(__popcountti2)
+NOT_HERE_BEFORE_10_6(__powidf2)
+NOT_HERE_BEFORE_10_6(__powisf2)
+NOT_HERE_BEFORE_10_6(__powitf2)
+NOT_HERE_BEFORE_10_6(__powixf2)
+NOT_HERE_BEFORE_10_6(__subvdi3)
+NOT_HERE_BEFORE_10_6(__subvsi3)
+NOT_HERE_BEFORE_10_6(__subvti3)
+NOT_HERE_BEFORE_10_6(__ucmpdi2)
+NOT_HERE_BEFORE_10_6(__ucmpti2)
+NOT_HERE_BEFORE_10_6(__udivdi3)
+NOT_HERE_BEFORE_10_6(__udivmoddi4)
+NOT_HERE_BEFORE_10_6(__udivmodti4)
+NOT_HERE_BEFORE_10_6(__udivti3)
+NOT_HERE_BEFORE_10_6(__umoddi3)
+NOT_HERE_BEFORE_10_6(__umodti3)
+
+#if __ppc__
+NOT_HERE_BEFORE_10_6(__gcc_qadd)
+NOT_HERE_BEFORE_10_6(__gcc_qdiv)
+NOT_HERE_BEFORE_10_6(__gcc_qmul)
+NOT_HERE_BEFORE_10_6(__gcc_qsub)
+NOT_HERE_BEFORE_10_6(__trampoline_setup)
+#endif // __ppc__
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_compare_exchange)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_compare_exchange_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_compare_exchange_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_compare_exchange_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_compare_exchange_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_exchange)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_exchange_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_exchange_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_exchange_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_exchange_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_add_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_add_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_add_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_add_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_and_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_and_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_and_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_and_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_or_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_or_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_or_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_or_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_sub_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_sub_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_sub_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_sub_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_xor_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_xor_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_xor_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_fetch_xor_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_load)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_load_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_load_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_load_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_load_8)
+
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_store)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_store_1)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_store_2)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_store_4)
+NOT_HERE_IN_10_8_AND_EARLIER(__atomic_store_8)
+
+#if __arm__ && __DYNAMIC__
+#define NOT_HERE_UNTIL_AFTER_4_3(sym)                                          \
+  extern const char sym##_tmp1 __asm("$ld$hide$os3.0$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp1 = 0;            \
+  extern const char sym##_tmp2 __asm("$ld$hide$os3.1$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp2 = 0;            \
+  extern const char sym##_tmp3 __asm("$ld$hide$os3.2$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp3 = 0;            \
+  extern const char sym##_tmp4 __asm("$ld$hide$os4.0$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp4 = 0;            \
+  extern const char sym##_tmp5 __asm("$ld$hide$os4.1$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp5 = 0;            \
+  extern const char sym##_tmp6 __asm("$ld$hide$os4.2$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp6 = 0;            \
+  extern const char sym##_tmp7 __asm("$ld$hide$os4.3$_" #sym);                 \
+  __attribute__((visibility("default"))) const char sym##_tmp7 = 0;
+
+NOT_HERE_UNTIL_AFTER_4_3(__absvdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__absvsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__adddf3)
+NOT_HERE_UNTIL_AFTER_4_3(__adddf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__addsf3)
+NOT_HERE_UNTIL_AFTER_4_3(__addsf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__addvdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__addvsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__ashldi3)
+NOT_HERE_UNTIL_AFTER_4_3(__ashrdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__bswapdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__bswapsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__clzdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__clzsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__cmpdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__ctzdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__ctzsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__divdc3)
+NOT_HERE_UNTIL_AFTER_4_3(__divdf3)
+NOT_HERE_UNTIL_AFTER_4_3(__divdf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__divdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__divsc3)
+NOT_HERE_UNTIL_AFTER_4_3(__divsf3)
+NOT_HERE_UNTIL_AFTER_4_3(__divsf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__divsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__eqdf2)
+NOT_HERE_UNTIL_AFTER_4_3(__eqdf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__eqsf2)
+NOT_HERE_UNTIL_AFTER_4_3(__eqsf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__extendsfdf2)
+NOT_HERE_UNTIL_AFTER_4_3(__extendsfdf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__ffsdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__fixdfdi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixdfsi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixdfsivfp)
+NOT_HERE_UNTIL_AFTER_4_3(__fixsfdi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixsfsi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixsfsivfp)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunsdfdi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunsdfsi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunsdfsivfp)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunssfdi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunssfsi)
+NOT_HERE_UNTIL_AFTER_4_3(__fixunssfsivfp)
+NOT_HERE_UNTIL_AFTER_4_3(__floatdidf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatdisf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatsidf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatsidfvfp)
+NOT_HERE_UNTIL_AFTER_4_3(__floatsisf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatsisfvfp)
+NOT_HERE_UNTIL_AFTER_4_3(__floatundidf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatundisf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatunsidf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatunsisf)
+NOT_HERE_UNTIL_AFTER_4_3(__floatunssidfvfp)
+NOT_HERE_UNTIL_AFTER_4_3(__floatunssisfvfp)
+NOT_HERE_UNTIL_AFTER_4_3(__gedf2)
+NOT_HERE_UNTIL_AFTER_4_3(__gedf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__gesf2)
+NOT_HERE_UNTIL_AFTER_4_3(__gesf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__gtdf2)
+NOT_HERE_UNTIL_AFTER_4_3(__gtdf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__gtsf2)
+NOT_HERE_UNTIL_AFTER_4_3(__gtsf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__ledf2)
+NOT_HERE_UNTIL_AFTER_4_3(__ledf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__lesf2)
+NOT_HERE_UNTIL_AFTER_4_3(__lesf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__lshrdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__ltdf2)
+NOT_HERE_UNTIL_AFTER_4_3(__ltdf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__ltsf2)
+NOT_HERE_UNTIL_AFTER_4_3(__ltsf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__moddi3)
+NOT_HERE_UNTIL_AFTER_4_3(__modsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__muldc3)
+NOT_HERE_UNTIL_AFTER_4_3(__muldf3)
+NOT_HERE_UNTIL_AFTER_4_3(__muldf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__muldi3)
+NOT_HERE_UNTIL_AFTER_4_3(__mulsc3)
+NOT_HERE_UNTIL_AFTER_4_3(__mulsf3)
+NOT_HERE_UNTIL_AFTER_4_3(__mulsf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__mulvdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__mulvsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__nedf2)
+NOT_HERE_UNTIL_AFTER_4_3(__nedf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__negdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__negvdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__negvsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__nesf2)
+NOT_HERE_UNTIL_AFTER_4_3(__nesf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__paritydi2)
+NOT_HERE_UNTIL_AFTER_4_3(__paritysi2)
+NOT_HERE_UNTIL_AFTER_4_3(__popcountdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__popcountsi2)
+NOT_HERE_UNTIL_AFTER_4_3(__powidf2)
+NOT_HERE_UNTIL_AFTER_4_3(__powisf2)
+NOT_HERE_UNTIL_AFTER_4_3(__subdf3)
+NOT_HERE_UNTIL_AFTER_4_3(__subdf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__subsf3)
+NOT_HERE_UNTIL_AFTER_4_3(__subsf3vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__subvdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__subvsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__truncdfsf2)
+NOT_HERE_UNTIL_AFTER_4_3(__truncdfsf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__ucmpdi2)
+NOT_HERE_UNTIL_AFTER_4_3(__udivdi3)
+NOT_HERE_UNTIL_AFTER_4_3(__udivmoddi4)
+NOT_HERE_UNTIL_AFTER_4_3(__udivsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__umoddi3)
+NOT_HERE_UNTIL_AFTER_4_3(__umodsi3)
+NOT_HERE_UNTIL_AFTER_4_3(__unorddf2)
+NOT_HERE_UNTIL_AFTER_4_3(__unorddf2vfp)
+NOT_HERE_UNTIL_AFTER_4_3(__unordsf2)
+NOT_HERE_UNTIL_AFTER_4_3(__unordsf2vfp)
+
+NOT_HERE_UNTIL_AFTER_4_3(__divmodsi4)
+NOT_HERE_UNTIL_AFTER_4_3(__udivmodsi4)
+#endif // __arm__ && __DYNAMIC__
+
+#else // !__APPLE__
+
+extern int avoid_empty_file;
+
+#endif // !__APPLE__
diff --git a/lib/compiler-rt/builtins/arm/adddf3vfp.S b/lib/compiler-rt/builtins/arm/adddf3vfp.S
new file mode 100644 (file)
index 0000000..1a271db
--- /dev/null
@@ -0,0 +1,31 @@
+//===-- adddf3vfp.S - Implement adddf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+// double __adddf3vfp(double a, double b) { return a + b; }
+//
+// Adds two double precision floating point numbers using the Darwin
+// calling convention where double arguments are passsed in GPR pairs
+
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__adddf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vadd.f64 d0, d0, d1
+#else
+       vmov    d6, r0, r1              // move first param from r0/r1 pair into d6
+       vmov    d7, r2, r3              // move second param from r2/r3 pair into d7
+       vadd.f64 d6, d6, d7
+       vmov    r0, r1, d6              // move result back to r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__adddf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/addsf3.S b/lib/compiler-rt/builtins/arm/addsf3.S
new file mode 100644 (file)
index 0000000..aa4d404
--- /dev/null
@@ -0,0 +1,276 @@
+//===-- addsf3.S - Adds two single precision floating pointer numbers-----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __addsf3 (single precision floating pointer number
+// addition with the IEEE-754 default rounding (to nearest, ties to even)
+// function for the ARM Thumb1 ISA.
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+#define significandBits 23
+#define typeWidth 32
+
+       .syntax unified
+       .text
+  .thumb
+  .p2align 2
+
+DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_fadd, __addsf3)
+
+DEFINE_COMPILERRT_THUMB_FUNCTION(__addsf3)
+  push {r4, r5, r6, r7, lr}
+  // Get the absolute value of a and b.
+  lsls r2, r0, #1
+  lsls r3, r1, #1
+  lsrs r2, r2, #1  // aAbs
+  beq  LOCAL_LABEL(a_zero_nan_inf)
+  lsrs r3, r3, #1  // bAbs
+  beq  LOCAL_LABEL(zero_nan_inf)
+
+  // Detect if a or b is infinity or Nan.
+  lsrs r6, r2, #(significandBits)
+  lsrs r7, r3, #(significandBits)
+  cmp  r6, #0xFF
+  beq  LOCAL_LABEL(zero_nan_inf)
+  cmp  r7, #0xFF
+  beq  LOCAL_LABEL(zero_nan_inf)
+
+  // Swap Rep and Abs so that a and aAbs has the larger absolute value.
+  cmp r2, r3
+  bhs LOCAL_LABEL(no_swap)
+  movs r4, r0
+  movs r5, r2
+  movs r0, r1
+  movs r2, r3
+  movs r1, r4
+  movs r3, r5
+LOCAL_LABEL(no_swap):
+
+  // Get the significands and shift them to give us round, guard and sticky.
+  lsls r4, r0, #(typeWidth - significandBits)
+  lsrs r4, r4, #(typeWidth - significandBits - 3) // aSignificand << 3
+  lsls r5, r1, #(typeWidth - significandBits)
+  lsrs r5, r5, #(typeWidth - significandBits - 3) // bSignificand << 3
+
+  // Get the implicitBit.
+  movs r6, #1
+  lsls r6, r6, #(significandBits + 3)
+
+  // Get aExponent and set implicit bit if necessary.
+  lsrs r2, r2, #(significandBits)
+  beq LOCAL_LABEL(a_done_implicit_bit)
+  orrs r4, r6
+LOCAL_LABEL(a_done_implicit_bit):
+
+  // Get bExponent and set implicit bit if necessary.
+  lsrs r3, r3, #(significandBits)
+  beq LOCAL_LABEL(b_done_implicit_bit)
+  orrs r5, r6
+LOCAL_LABEL(b_done_implicit_bit):
+
+  // Get the difference in exponents.
+  subs r6, r2, r3
+  beq LOCAL_LABEL(done_align)
+
+  // If b is denormal, then a must be normal as align > 0, and we only need to
+  // right shift bSignificand by (align - 1) bits.
+  cmp  r3, #0
+  bne  1f
+  subs r6, r6, #1
+1:
+
+  // No longer needs bExponent. r3 is dead here.
+  // Set sticky bits of b: sticky = bSignificand << (typeWidth - align).
+  movs r3, #(typeWidth)
+  subs r3, r3, r6
+  movs r7, r5
+  lsls r7, r3
+  beq 1f
+  movs r7, #1
+1:
+
+  // bSignificand = bSignificand >> align | sticky;
+  lsrs r5, r6
+  orrs r5, r7
+  bne LOCAL_LABEL(done_align)
+  movs r5, #1 //  sticky; b is known to be non-zero.
+
+LOCAL_LABEL(done_align):
+  // isSubtraction = (aRep ^ bRep) >> 31;
+  movs r7, r0
+  eors r7, r1
+  lsrs r7, #31
+  bne LOCAL_LABEL(do_substraction)
+
+  // Same sign, do Addition.
+
+  // aSignificand += bSignificand;
+  adds r4, r4, r5
+
+  // Check carry bit.
+  movs r6, #1
+  lsls r6, r6, #(significandBits + 3 + 1)
+  movs r7, r4
+  ands r7, r6
+  beq LOCAL_LABEL(form_result)
+  // If the addition carried up, we need to right-shift the result and
+  // adjust the exponent.
+  movs r7, r4
+  movs r6, #1
+  ands r7, r6 // sticky = aSignificand & 1;
+  lsrs r4, #1
+  orrs r4, r7  // result Significand
+  adds r2, #1  // result Exponent
+  // If we have overflowed the type, return +/- infinity.
+  cmp  r2, 0xFF
+  beq  LOCAL_LABEL(ret_inf)
+
+LOCAL_LABEL(form_result):
+  // Shift the sign, exponent and significand into place.
+  lsrs r0, #(typeWidth - 1)
+  lsls r0, #(typeWidth - 1) // Get Sign.
+  lsls r2, #(significandBits)
+  orrs r0, r2
+  movs r1, r4
+  lsls r4, #(typeWidth - significandBits - 3)
+  lsrs r4, #(typeWidth - significandBits)
+  orrs r0, r4
+
+  // Final rounding.  The result may overflow to infinity, but that is the
+  // correct result in that case.
+  // roundGuardSticky = aSignificand & 0x7;
+  movs r2, #0x7
+  ands r1, r2
+  // if (roundGuardSticky > 0x4) result++;
+
+  cmp r1, #0x4
+  blt LOCAL_LABEL(done_round)
+  beq 1f
+  adds r0, #1
+  pop {r4, r5, r6, r7, pc}
+1:
+
+  // if (roundGuardSticky == 0x4) result += result & 1;
+  movs r1, r0
+  lsrs r1, #1
+  bcc  LOCAL_LABEL(done_round)
+  adds r0, r0, #1
+LOCAL_LABEL(done_round):
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(do_substraction):
+  subs r4, r4, r5 // aSignificand -= bSignificand;
+  beq  LOCAL_LABEL(ret_zero)
+  movs r6, r4
+  cmp  r2, 0
+  beq  LOCAL_LABEL(form_result) // if a's exp is 0, no need to normalize.
+  // If partial cancellation occured, we need to left-shift the result
+  // and adjust the exponent:
+  lsrs r6, r6, #(significandBits + 3)
+  bne LOCAL_LABEL(form_result)
+
+  push {r0, r1, r2, r3}
+  movs r0, r4
+  bl   SYMBOL_NAME(__clzsi2)
+  movs r5, r0
+  pop {r0, r1, r2, r3}
+  // shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);
+  subs r5, r5, #(typeWidth - significandBits - 3 - 1)
+  // aSignificand <<= shift; aExponent -= shift;
+  lsls r4, r5
+  subs  r2, r2, r5
+  bgt LOCAL_LABEL(form_result)
+
+  // Do normalization if aExponent <= 0.
+  movs r6, #1
+  subs r6, r6, r2 // 1 - aExponent;
+  movs r2, #0 // aExponent = 0;
+  movs r3, #(typeWidth) // bExponent is dead.
+  subs r3, r3, r6
+  movs r7, r4
+  lsls r7, r3  // stickyBit = (bool)(aSignificant << (typeWidth - align))
+  beq 1f
+  movs r7, #1
+1:
+  lsrs r4, r6 // aSignificand >> shift
+  orrs r4, r7
+  b LOCAL_LABEL(form_result)
+
+LOCAL_LABEL(ret_zero):
+  movs r0, #0
+  pop {r4, r5, r6, r7, pc}
+
+
+LOCAL_LABEL(a_zero_nan_inf):
+  lsrs r3, r3, #1
+
+LOCAL_LABEL(zero_nan_inf):
+  // Here  r2 has aAbs, r3 has bAbs
+  movs r4, #0xFF
+  lsls r4, r4, #(significandBits) // Make +inf.
+
+  cmp r2, r4
+  bhi LOCAL_LABEL(a_is_nan)
+  cmp r3, r4
+  bhi LOCAL_LABEL(b_is_nan)
+
+  cmp r2, r4
+  bne LOCAL_LABEL(a_is_rational)
+  // aAbs is INF.
+  eors r1, r0 // aRep ^ bRep.
+  movs r6, #1
+  lsls r6, r6, #(typeWidth - 1) // get sign mask.
+  cmp r1, r6 // if they only differ on sign bit, it's -INF + INF
+  beq LOCAL_LABEL(a_is_nan)
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(a_is_rational):
+  cmp r3, r4
+  bne LOCAL_LABEL(b_is_rational)
+  movs r0, r1
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(b_is_rational):
+  // either a or b or both are zero.
+  adds r4, r2, r3
+  beq  LOCAL_LABEL(both_zero)
+  cmp r2, #0 // is absA 0 ?
+  beq LOCAL_LABEL(ret_b)
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(both_zero):
+  ands r0, r1 // +0 + -0 = +0
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(ret_b):
+  movs r0, r1
+
+LOCAL_LABEL(ret):
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(b_is_nan):
+  movs r0, r1
+LOCAL_LABEL(a_is_nan):
+  movs r1, #1
+  lsls r1, r1, #(significandBits -1) // r1 is quiet bit.
+  orrs r0, r1
+  pop {r4, r5, r6, r7, pc}
+
+LOCAL_LABEL(ret_inf):
+  movs r4, #0xFF
+  lsls r4, r4, #(significandBits)
+  orrs r0, r4
+  lsrs r0, r0, #(significandBits)
+  lsls r0, r0, #(significandBits)
+  pop {r4, r5, r6, r7, pc}
+
+
+END_COMPILERRT_FUNCTION(__addsf3)
+
+NO_EXEC_STACK_DIRECTIVE
diff --git a/lib/compiler-rt/builtins/arm/addsf3vfp.S b/lib/compiler-rt/builtins/arm/addsf3vfp.S
new file mode 100644 (file)
index 0000000..c9d1fd1
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- addsf3vfp.S - Implement addsf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __addsf3vfp(float a, float b);
+//
+// Adds two single precision floating point numbers using the Darwin
+// calling convention where single arguments are passsed in GPRs
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__addsf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vadd.f32 s0, s0, s1
+#else
+       vmov    s14, r0         // move first param from r0 into float register
+       vmov    s15, r1         // move second param from r1 into float register
+       vadd.f32 s14, s14, s15
+       vmov    r0, s14         // move result back to r0
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__addsf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 036a6f5..bd039a0 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_cdcmp.S - EABI cdcmp* implementation ------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -30,13 +29,35 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
         push {r0-r3, lr}
         bl __aeabi_cdcmpeq_check_nan
         cmp r0, #1
+#if defined(USE_THUMB_1)
+        beq 1f
+        // NaN has been ruled out, so __aeabi_cdcmple can't trap
+        mov r0, sp
+        ldm r0, {r0-r3}
+        bl __aeabi_cdcmple
+        pop {r0-r3, pc}
+1:
+        // Z = 0, C = 1
+        movs r0, #0xF
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+#else
         pop {r0-r3, lr}
 
         // NaN has been ruled out, so __aeabi_cdcmple can't trap
+        // Use "it ne" + unconditional branch to guarantee a supported relocation if
+        // __aeabi_cdcmple is in a different section for some builds.
+        IT(ne)
         bne __aeabi_cdcmple
 
-        msr CPSR_f, #APSR_C
+#if defined(USE_THUMB_2)
+        mov ip, #APSR_C
+        msr APSR_nzcvq, ip
+#else
+        msr APSR_nzcvq, #APSR_C
+#endif
         JMP(lr)
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
 
 
@@ -59,19 +80,44 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple)
 
         bl __aeabi_dcmplt
         cmp r0, #1
+#if defined(USE_THUMB_1)
+        bne 1f
+        // Z = 0, C = 0
+        movs r0, #1
+        lsls r0, r0, #1
+        pop {r0-r3, pc}
+1:
+        mov r0, sp
+        ldm r0, {r0-r3}
+        bl __aeabi_dcmpeq
+        cmp r0, #1
+        bne 2f
+        // Z = 1, C = 1
+        movs r0, #2
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+2:
+        // Z = 0, C = 1
+        movs r0, #0xF
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+#else
+        ITT(eq)
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_dcmpeq
         cmp r0, #1
+        ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
-        msr CPSR_f, ip
+        msr APSR_nzcvq, ip
         pop {r0-r3}
         POP_PC()
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
 
 // int __aeabi_cdrcmple(double a, double b) {
@@ -94,3 +140,5 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdrcmple)
         b __aeabi_cdcmple
 END_COMPILERRT_FUNCTION(__aeabi_cdrcmple)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 577f6b2..7bae874 100644 (file)
@@ -1,16 +1,15 @@
 //===-- lib/arm/aeabi_cdcmpeq_helper.c - Helper for cdcmpeq ---------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
+#include "../int_lib.h"
 #include <stdint.h>
 
-__attribute__((pcs("aapcs")))
-__attribute__((visibility("hidden")))
-int __aeabi_cdcmpeq_check_nan(double a, double b) {
-    return __builtin_isnan(a) || __builtin_isnan(b);
+AEABI_RTABI __attribute__((visibility("hidden"))) int
+__aeabi_cdcmpeq_check_nan(double a, double b) {
+  return __builtin_isnan(a) || __builtin_isnan(b);
 }
index 43594e5..a26cb2a 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_cfcmp.S - EABI cfcmp* implementation ------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -30,13 +29,35 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
         push {r0-r3, lr}
         bl __aeabi_cfcmpeq_check_nan
         cmp r0, #1
+#if defined(USE_THUMB_1)
+        beq 1f
+        // NaN has been ruled out, so __aeabi_cfcmple can't trap
+        mov r0, sp
+        ldm r0, {r0-r3}
+        bl __aeabi_cfcmple
+        pop {r0-r3, pc}
+1:
+        // Z = 0, C = 1
+        movs r0, #0xF
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+#else
         pop {r0-r3, lr}
 
         // NaN has been ruled out, so __aeabi_cfcmple can't trap
+        // Use "it ne" + unconditional branch to guarantee a supported relocation if
+        // __aeabi_cfcmple is in a different section for some builds.
+        IT(ne)
         bne __aeabi_cfcmple
 
-        msr CPSR_f, #APSR_C
+#if defined(USE_THUMB_2)
+        mov ip, #APSR_C
+        msr APSR_nzcvq, ip
+#else
+        msr APSR_nzcvq, #APSR_C
+#endif
         JMP(lr)
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
 
 
@@ -59,19 +80,44 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
 
         bl __aeabi_fcmplt
         cmp r0, #1
+#if defined(USE_THUMB_1)
+        bne 1f
+        // Z = 0, C = 0
+        movs r0, #1
+        lsls r0, r0, #1
+        pop {r0-r3, pc}
+1:
+        mov r0, sp
+        ldm r0, {r0-r3}
+        bl __aeabi_fcmpeq
+        cmp r0, #1
+        bne 2f
+        // Z = 1, C = 1
+        movs r0, #2
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+2:
+        // Z = 0, C = 1
+        movs r0, #0xF
+        lsls r0, r0, #31
+        pop {r0-r3, pc}
+#else
+        ITT(eq)
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_fcmpeq
         cmp r0, #1
+        ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
-        msr CPSR_f, ip
+        msr APSR_nzcvq, ip
         pop {r0-r3}
         POP_PC()
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
 
 // int __aeabi_cfrcmple(float a, float b) {
@@ -89,3 +135,5 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
         b __aeabi_cfcmple
 END_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 992e31f..2540733 100644 (file)
@@ -1,16 +1,15 @@
 //===-- lib/arm/aeabi_cfcmpeq_helper.c - Helper for cdcmpeq ---------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
+#include "../int_lib.h"
 #include <stdint.h>
 
-__attribute__((pcs("aapcs")))
-__attribute__((visibility("hidden")))
-int __aeabi_cfcmpeq_check_nan(float a, float b) {
-    return __builtin_isnan(a) || __builtin_isnan(b);
+AEABI_RTABI __attribute__((visibility("hidden"))) int
+__aeabi_cfcmpeq_check_nan(float a, float b) {
+  return __builtin_isnan(a) || __builtin_isnan(b);
 }
index 310c35b..5f72067 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_dcmp.S - EABI dcmp* implementation ---------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   }
 // }
 
+#if defined(COMPILER_RT_ARMHF_TARGET)
+#  define CONVERT_DCMP_ARGS_TO_DF2_ARGS                    \
+        vmov      d0, r0, r1                     SEPARATOR \
+        vmov      d1, r2, r3
+#else
+#  define CONVERT_DCMP_ARGS_TO_DF2_ARGS
+#endif
+
 #define DEFINE_AEABI_DCMP(cond)                            \
         .syntax unified                          SEPARATOR \
         .p2align 2                               SEPARATOR \
 DEFINE_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond)           \
         push      { r4, lr }                     SEPARATOR \
+        CONVERT_DCMP_ARGS_TO_DF2_ARGS            SEPARATOR \
         bl        SYMBOL_NAME(__ ## cond ## df2) SEPARATOR \
         cmp       r0, #0                         SEPARATOR \
         b ## cond 1f                             SEPARATOR \
-        mov       r0, #0                         SEPARATOR \
+        movs      r0, #0                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 1:                                               SEPARATOR \
-        mov       r0, #1                         SEPARATOR \
+        movs      r0, #1                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 END_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond)
 
@@ -38,3 +46,6 @@ DEFINE_AEABI_DCMP(lt)
 DEFINE_AEABI_DCMP(le)
 DEFINE_AEABI_DCMP(ge)
 DEFINE_AEABI_DCMP(gt)
+
+NO_EXEC_STACK_DIRECTIVE
+
index ccc95fa..7e88623 100644 (file)
@@ -1,43 +1,40 @@
-/* ===-- aeabi_div0.c - ARM Runtime ABI support routines for compiler-rt ---===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements the division by zero helper routines as specified by the
- * Run-time ABI for the ARM Architecture.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- aeabi_div0.c - ARM Runtime ABI support routines for compiler-rt ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the division by zero helper routines as specified by the
+// Run-time ABI for the ARM Architecture.
+//
+//===----------------------------------------------------------------------===//
 
-/*
- * RTABI 4.3.2 - Division by zero
- *
- * The *div0 functions:
- * - Return the value passed to them as a parameter
- * - Or, return a fixed value defined by the execution environment (such as 0)
- * - Or, raise a signal (often SIGFPE) or throw an exception, and do not return
- *
- * An application may provide its own implementations of the *div0 functions to
- * for a particular behaviour from the *div and *divmod functions called out of
- * line.
- */
+// RTABI 4.3.2 - Division by zero
+//
+// The *div0 functions:
+// - Return the value passed to them as a parameter
+// - Or, return a fixed value defined by the execution environment (such as 0)
+// - Or, raise a signal (often SIGFPE) or throw an exception, and do not return
+//
+// An application may provide its own implementations of the *div0 functions to
+// for a particular behaviour from the *div and *divmod functions called out of
+// line.
 
-/* provide an unused declaration to pacify pendantic compilation */
+#include "../int_lib.h"
+
+// provide an unused declaration to pacify pendantic compilation
 extern unsigned char declaration;
 
 #if defined(__ARM_EABI__)
-int __attribute__((weak)) __attribute__((visibility("hidden")))
+AEABI_RTABI int __attribute__((weak)) __attribute__((visibility("hidden")))
 __aeabi_idiv0(int return_value) {
   return return_value;
 }
 
-long long __attribute__((weak)) __attribute__((visibility("hidden")))
-__aeabi_ldiv0(long long return_value) {
+AEABI_RTABI long long __attribute__((weak))
+__attribute__((visibility("hidden"))) __aeabi_ldiv0(long long return_value) {
   return return_value;
 }
 #endif
-
index fc17d5a..e4e8dc0 100644 (file)
@@ -1,19 +1,14 @@
 //===-- lib/arm/aeabi_drsub.c - Double-precision subtraction --------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #define DOUBLE_PRECISION
 #include "../fp_lib.h"
 
-COMPILER_RT_ABI fp_t
-__aeabi_dsub(fp_t, fp_t);
+AEABI_RTABI fp_t __aeabi_dsub(fp_t, fp_t);
 
-COMPILER_RT_ABI fp_t
-__aeabi_drsub(fp_t a, fp_t b) {
-    return __aeabi_dsub(b, a);
-}
+AEABI_RTABI fp_t __aeabi_drsub(fp_t a, fp_t b) { return __aeabi_dsub(b, a); }
index 55f49a2..cd311b4 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_fcmp.S - EABI fcmp* implementation ---------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   }
 // }
 
+#if defined(COMPILER_RT_ARMHF_TARGET)
+#  define CONVERT_FCMP_ARGS_TO_SF2_ARGS                    \
+        vmov      s0, r0                         SEPARATOR \
+        vmov      s1, r1
+#else
+#  define CONVERT_FCMP_ARGS_TO_SF2_ARGS
+#endif
+
 #define DEFINE_AEABI_FCMP(cond)                            \
         .syntax unified                          SEPARATOR \
         .p2align 2                               SEPARATOR \
 DEFINE_COMPILERRT_FUNCTION(__aeabi_fcmp ## cond)           \
         push      { r4, lr }                     SEPARATOR \
+        CONVERT_FCMP_ARGS_TO_SF2_ARGS            SEPARATOR \
         bl        SYMBOL_NAME(__ ## cond ## sf2) SEPARATOR \
         cmp       r0, #0                         SEPARATOR \
         b ## cond 1f                             SEPARATOR \
-        mov       r0, #0                         SEPARATOR \
+        movs      r0, #0                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 1:                                               SEPARATOR \
-        mov       r0, #1                         SEPARATOR \
+        movs      r0, #1                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 END_COMPILERRT_FUNCTION(__aeabi_fcmp ## cond)
 
@@ -38,3 +46,6 @@ DEFINE_AEABI_FCMP(lt)
 DEFINE_AEABI_FCMP(le)
 DEFINE_AEABI_FCMP(ge)
 DEFINE_AEABI_FCMP(gt)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 64258dc..9a36324 100644 (file)
@@ -1,19 +1,14 @@
 //===-- lib/arm/aeabi_frsub.c - Single-precision subtraction --------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #define SINGLE_PRECISION
 #include "../fp_lib.h"
 
-COMPILER_RT_ABI fp_t
-__aeabi_fsub(fp_t, fp_t);
+AEABI_RTABI fp_t __aeabi_fsub(fp_t, fp_t);
 
-COMPILER_RT_ABI fp_t
-__aeabi_frsub(fp_t a, fp_t b) {
-    return __aeabi_fsub(b, a);
-}
+AEABI_RTABI fp_t __aeabi_frsub(fp_t a, fp_t b) { return __aeabi_fsub(b, a); }
index 384add3..bb80e4b 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_idivmod.S - EABI idivmod implementation ---------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   return {quot, rem};
 // }
 
+#if defined(__MINGW32__)
+#define __aeabi_idivmod __rt_sdiv
+#endif
+
         .syntax unified
+        .text
+        DEFINE_CODE_STATE
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_idivmod)
+#if defined(USE_THUMB_1)
+        push    {r0, r1, lr}
+        bl      SYMBOL_NAME(__divsi3)
+        pop     {r1, r2, r3} // now r0 = quot, r1 = num, r2 = denom
+        muls    r2, r0, r2   // r2 = quot * denom
+        subs    r1, r1, r2
+        JMP     (r3)
+#else  // defined(USE_THUMB_1)
         push    { lr }
         sub     sp, sp, #4
         mov     r2, sp
+#if defined(__MINGW32__)
+        mov     r3, r0
+        mov     r0, r1
+        mov     r1, r3
+#endif
         bl      SYMBOL_NAME(__divmodsi4)
         ldr     r1, [sp]
         add     sp, sp, #4
         pop     { pc }
+#endif //  defined(USE_THUMB_1)
 END_COMPILERRT_FUNCTION(__aeabi_idivmod)
+
+NO_EXEC_STACK_DIRECTIVE
+
index ad06f1d..d0d06be 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_ldivmod.S - EABI ldivmod implementation ---------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   return {quot, rem};
 // }
 
+#if defined(__MINGW32__)
+#define __aeabi_ldivmod __rt_sdiv64
+#endif
+
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_ldivmod)
-        push    {r11, lr}
+        push    {r6, lr}
         sub     sp, sp, #16
-        add     r12, sp, #8
-        str     r12, [sp]
+        add     r6, sp, #8
+        str     r6, [sp]
+#if defined(__MINGW32__)
+        movs    r6, r0
+        movs    r0, r2
+        movs    r2, r6
+        movs    r6, r1
+        movs    r1, r3
+        movs    r3, r6
+#endif
         bl      SYMBOL_NAME(__divmoddi4)
         ldr     r2, [sp, #8]
         ldr     r3, [sp, #12]
         add     sp, sp, #16
-        pop     {r11, pc}
+        pop     {r6, pc}
 END_COMPILERRT_FUNCTION(__aeabi_ldivmod)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 051ce43..4163728 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_memcmp.S - EABI memcmp implementation -----------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 
 //  void __aeabi_memcmp(void *dest, void *src, size_t n) { memcmp(dest, src, n); }
 
+        .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_memcmp)
+#ifdef USE_THUMB_1
+        push    {r7, lr}
+        bl      memcmp
+        pop     {r7, pc}
+#else
         b       memcmp
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_memcmp)
 
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcmp4, __aeabi_memcmp)
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcmp8, __aeabi_memcmp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index cf02332..93e1b05 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_memcpy.S - EABI memcpy implementation -----------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 
 //  void __aeabi_memcpy(void *dest, void *src, size_t n) { memcpy(dest, src, n); }
 
+        .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_memcpy)
+#ifdef USE_THUMB_1
+        push    {r7, lr}
+        bl      memcpy
+        pop     {r7, pc}
+#else
         b       memcpy
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_memcpy)
 
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcpy4, __aeabi_memcpy)
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcpy8, __aeabi_memcpy)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 4dda06f..c2f0fa4 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_memmove.S - EABI memmove implementation --------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===---------------------------------------------------------------------===//
 
 
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_memmove)
+#ifdef USE_THUMB_1
+        push    {r7, lr}
+        bl      memmove
+        pop     {r7, pc}
+#else
         b       memmove
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_memmove)
 
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memmove4, __aeabi_memmove)
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memmove8, __aeabi_memmove)
+
+NO_EXEC_STACK_DIRECTIVE
+
index c8b49c7..2aa8ec0 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_memset.S - EABI memset implementation -----------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //  void __aeabi_memset(void *dest, size_t n, int c) { memset(dest, c, n); }
 //  void __aeabi_memclr(void *dest, size_t n) { __aeabi_memset(dest, n, 0); }
 
+        .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_memset)
         mov     r3, r1
         mov     r1, r2
         mov     r2, r3
+#ifdef USE_THUMB_1
+        push    {r7, lr}
+        bl      memset
+        pop     {r7, pc}
+#else
         b       memset
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_memset)
 
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memset4, __aeabi_memset)
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memset8, __aeabi_memset)
 
+        .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_memclr)
         mov     r2, r1
-        mov     r1, #0
+        movs    r1, #0
+#ifdef USE_THUMB_1
+        push    {r7, lr}
+        bl      memset
+        pop     {r7, pc}
+#else
         b       memset
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_memclr)
 
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memclr4, __aeabi_memclr)
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memclr8, __aeabi_memclr)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 8ea474d..df03076 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_uidivmod.S - EABI uidivmod implementation -------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   return {quot, rem};
 // }
 
+#if defined(__MINGW32__)
+#define __aeabi_uidivmod __rt_udiv
+#endif
+
         .syntax unified
+        .text
+        DEFINE_CODE_STATE
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_uidivmod)
+#if defined(USE_THUMB_1)
+        cmp     r0, r1
+        bcc     LOCAL_LABEL(case_denom_larger)
+        push    {r0, r1, lr}
+        bl      SYMBOL_NAME(__aeabi_uidiv)
+        pop     {r1, r2, r3}
+        muls    r2, r0, r2 // r2 = quot * denom
+        subs    r1, r1, r2
+        JMP     (r3)
+LOCAL_LABEL(case_denom_larger):
+        movs    r1, r0
+        movs    r0, #0
+        JMP     (lr)
+#else // defined(USE_THUMB_1)
         push    { lr }
         sub     sp, sp, #4
         mov     r2, sp
+#if defined(__MINGW32__)
+        mov     r3, r0
+        mov     r0, r1
+        mov     r1, r3
+#endif
         bl      SYMBOL_NAME(__udivmodsi4)
         ldr     r1, [sp]
         add     sp, sp, #4
         pop     { pc }
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_uidivmod)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 4e1f8e2..4fc9770 100644 (file)
@@ -1,9 +1,8 @@
 //===-- aeabi_uldivmod.S - EABI uldivmod implementation -------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //   return {quot, rem};
 // }
 
+#if defined(__MINGW32__)
+#define __aeabi_uldivmod __rt_udiv64
+#endif
+
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_uldivmod)
-        push   {r11, lr}
+        push   {r6, lr}
         sub    sp, sp, #16
-        add    r12, sp, #8
-        str    r12, [sp]
+        add    r6, sp, #8
+        str    r6, [sp]
+#if defined(__MINGW32__)
+        movs    r6, r0
+        movs    r0, r2
+        movs    r2, r6
+        movs    r6, r1
+        movs    r1, r3
+        movs    r3, r6
+#endif
         bl     SYMBOL_NAME(__udivmoddi4)
         ldr    r2, [sp, #8]
         ldr    r3, [sp, #12]
         add    sp, sp, #16
-        pop    {r11, pc}
+        pop    {r6, pc}
 END_COMPILERRT_FUNCTION(__aeabi_uldivmod)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 8b9ad43..271df8b 100644 (file)
@@ -1,9 +1,8 @@
 //===------- bswapdi2 - Implement bswapdi2 --------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -11,6 +10,7 @@
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
 //
 // extern uint64_t __bswapdi2(uint64_t);
 //
        .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapdi2)
+#if __ARM_ARCH < 6
+    // before armv6 does not have "rev" instruction
+    // r2 = rev(r0)
+    eor r2, r0, r0, ror #16
+    bic r2, r2, #0xff0000
+    mov r2, r2, lsr #8
+    eor r2, r2, r0, ror #8
+    // r0 = rev(r1)
+    eor r0, r1, r1, ror #16
+    bic r0, r0, #0xff0000
+    mov r0, r0, lsr #8
+    eor r0, r0, r1, ror #8
+#else
     rev r2, r0  // r2 = rev(r0)
     rev r0, r1  // r0 = rev(r1)
+#endif
     mov r1, r2  // r1 = r2 = rev(r0)
     JMP(lr)
 END_COMPILERRT_FUNCTION(__bswapdi2)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 9e8259f..07cc3d8 100644 (file)
@@ -1,9 +1,8 @@
 //===------- bswapsi2 - Implement bswapsi2 --------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -11,6 +10,7 @@
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
 //
 // extern uint32_t __bswapsi2(uint32_t);
 //
        .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapsi2)
+#if __ARM_ARCH < 6
+    // before armv6 does not have "rev" instruction
+       eor     r1, r0, r0, ror #16
+       bic     r1, r1, #0xff0000
+       mov     r1, r1, lsr #8
+       eor     r0, r1, r0, ror #8
+#else
     rev r0, r0
+#endif
     JMP(lr)
 END_COMPILERRT_FUNCTION(__bswapsi2)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/chkstk.S b/lib/compiler-rt/builtins/arm/chkstk.S
new file mode 100644 (file)
index 0000000..c5c9ebe
--- /dev/null
@@ -0,0 +1,35 @@
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+#include "../assembly.h"
+
+// __chkstk routine
+// This routine is windows specific.
+// http://msdn.microsoft.com/en-us/library/ms648426.aspx
+
+// This clobbers the register r12, and the condition codes, and uses r5 and r6
+// as temporaries by backing them up and restoring them afterwards.
+// Does not modify any memory or the stack pointer.
+
+//      movw    r4,  #256 // Number of bytes of stack, in units of 4 byte
+//      bl      __chkstk
+//      sub.w   sp, sp, r4
+
+#define PAGE_SIZE 4096
+
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__chkstk)
+        lsl    r4,  r4,  #2
+        mov    r12, sp
+        push   {r5, r6}
+        mov    r5,  r4
+1:
+        sub    r12, r12, #PAGE_SIZE
+        subs   r5,  r5,  #PAGE_SIZE
+        ldr    r6,  [r12]
+        bgt    1b
+
+        pop    {r5, r6}
+        bx     lr
+END_COMPILERRT_FUNCTION(__chkstk)
index 08a18f7..685668b 100644 (file)
@@ -1,20 +1,20 @@
-/* ===-- clzdi2.c - Implement __clzdi2 -------------------------------------===
- *
- *               The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements count leading zeros for 64bit arguments.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- clzdi2.c - Implement __clzdi2 -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements count leading zeros for 64bit arguments.
+//
+//===----------------------------------------------------------------------===//
+
 #include "../assembly.h"
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
        .p2align        2
 DEFINE_COMPILERRT_FUNCTION(__clzdi2)
@@ -34,14 +34,12 @@ DEFINE_COMPILERRT_FUNCTION(__clzdi2)
 #endif
        JMP(lr)
 #else
-       /* Assumption: n != 0 */
+       // Assumption: n != 0
 
-       /*
-        * r0: n
-        * r1: upper half of n, overwritten after check
-        * r1: count of leading zeros in n + 1
-        * r2: scratch register for shifted r0
-        */
+       // r0: n
+       // r1: upper half of n, overwritten after check
+       // r1: count of leading zeros in n + 1
+       // r2: scratch register for shifted r0
 #ifdef __ARMEB__
        cmp     r0, 0
        moveq   r0, r1
@@ -52,14 +50,12 @@ DEFINE_COMPILERRT_FUNCTION(__clzdi2)
        movne   r1, 1
        moveq   r1, 33
 
-       /*
-        * Basic block:
-        * if ((r0 >> SHIFT) == 0)
-        *   r1 += SHIFT;
-        * else
-        *   r0 >>= SHIFT;
-        * for descending powers of two as SHIFT.
-        */
+       // Basic block:
+       // if ((r0 >> SHIFT) == 0)
+       //   r1 += SHIFT;
+       // else
+       //   r0 >>= SHIFT;
+       // for descending powers of two as SHIFT.
 #define BLOCK(shift) \
        lsrs    r2, r0, shift; \
        movne   r0, r2; \
@@ -70,20 +66,21 @@ DEFINE_COMPILERRT_FUNCTION(__clzdi2)
        BLOCK(4)
        BLOCK(2)
 
-       /*
-        * The basic block invariants at this point are (r0 >> 2) == 0 and
-        * r0 != 0. This means 1 <= r0 <= 3 and 0 <= (r0 >> 1) <= 1.
-        *
-        * r0 | (r0 >> 1) == 0 | (r0 >> 1) == 1 | -(r0 >> 1) | 1 - (r0 >> 1)
-        * ---+----------------+----------------+------------+--------------
-        * 1  | 1              | 0              | 0          | 1
-        * 2  | 0              | 1              | -1         | 0
-        * 3  | 0              | 1              | -1         | 0
-        *
-        * The r1's initial value of 1 compensates for the 1 here.
-        */
+       // The basic block invariants at this point are (r0 >> 2) == 0 and
+       // r0 != 0. This means 1 <= r0 <= 3 and 0 <= (r0 >> 1) <= 1.
+       //
+       // r0 | (r0 >> 1) == 0 | (r0 >> 1) == 1 | -(r0 >> 1) | 1 - (r0 >> 1)
+       // ---+----------------+----------------+------------+--------------
+       // 1  | 1              | 0              | 0          | 1
+       // 2  | 0              | 1              | -1         | 0
+       // 3  | 0              | 1              | -1         | 0
+       //
+       // The r1's initial value of 1 compensates for the 1 here.
        sub     r0, r1, r0, lsr #1
 
        JMP(lr)
 #endif // __ARM_FEATURE_CLZ
 END_COMPILERRT_FUNCTION(__clzdi2)
+
+NO_EXEC_STACK_DIRECTIVE
+
index d177b72..5d86fe4 100644 (file)
@@ -1,20 +1,20 @@
-/* ===-- clzsi2.c - Implement __clzsi2 -------------------------------------===
- *
- *               The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements count leading zeros for 32bit arguments.
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- clzsi2.c - Implement __clzsi2 -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements count leading zeros for 32bit arguments.
+//
+//===----------------------------------------------------------------------===//
+
 #include "../assembly.h"
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
        .p2align        2
 DEFINE_COMPILERRT_FUNCTION(__clzsi2)
@@ -22,23 +22,19 @@ DEFINE_COMPILERRT_FUNCTION(__clzsi2)
        clz     r0, r0
        JMP(lr)
 #else
-       /* Assumption: n != 0 */
+       // Assumption: n != 0
 
-       /*
-        * r0: n
-        * r1: count of leading zeros in n + 1
-        * r2: scratch register for shifted r0
-        */
+       // r0: n
+       // r1: count of leading zeros in n + 1
+       // r2: scratch register for shifted r0
        mov     r1, 1
 
-       /*
-        * Basic block:
-        * if ((r0 >> SHIFT) == 0)
-        *   r1 += SHIFT;
-        * else
-        *   r0 >>= SHIFT;
-        * for descending powers of two as SHIFT.
-        */
+       // Basic block:
+       // if ((r0 >> SHIFT) == 0)
+       //   r1 += SHIFT;
+       // else
+       //   r0 >>= SHIFT;
+       // for descending powers of two as SHIFT.
 
 #define BLOCK(shift) \
        lsrs    r2, r0, shift; \
@@ -50,20 +46,21 @@ DEFINE_COMPILERRT_FUNCTION(__clzsi2)
        BLOCK(4)
        BLOCK(2)
 
-       /*
-        * The basic block invariants at this point are (r0 >> 2) == 0 and
-        * r0 != 0. This means 1 <= r0 <= 3 and 0 <= (r0 >> 1) <= 1.
-        *
-        * r0 | (r0 >> 1) == 0 | (r0 >> 1) == 1 | -(r0 >> 1) | 1 - (r0 >> 1)
-        * ---+----------------+----------------+------------+--------------
-        * 1  | 1              | 0              | 0          | 1
-        * 2  | 0              | 1              | -1         | 0
-        * 3  | 0              | 1              | -1         | 0
-        *
-        * The r1's initial value of 1 compensates for the 1 here.
-        */
+       // The basic block invariants at this point are (r0 >> 2) == 0 and
+       // r0 != 0. This means 1 <= r0 <= 3 and 0 <= (r0 >> 1) <= 1.
+       //
+       // r0 | (r0 >> 1) == 0 | (r0 >> 1) == 1 | -(r0 >> 1) | 1 - (r0 >> 1)
+       // ---+----------------+----------------+------------+--------------
+       // 1  | 1              | 0              | 0          | 1
+       // 2  | 0              | 1              | -1         | 0
+       // 3  | 0              | 1              | -1         | 0
+       //
+       // The r1's initial value of 1 compensates for the 1 here.
        sub     r0, r1, r0, lsr #1
 
        JMP(lr)
 #endif // __ARM_FEATURE_CLZ
 END_COMPILERRT_FUNCTION(__clzsi2)
+
+NO_EXEC_STACK_DIRECTIVE
+
index cf71d36..24b85d2 100644 (file)
@@ -1,9 +1,8 @@
 //===-- comparesf2.S - Implement single-precision soft-float comparisons --===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 //===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
-.syntax unified
 
-.p2align 2
-DEFINE_COMPILERRT_FUNCTION(__eqsf2)
+    .syntax unified
+    .text
+    DEFINE_CODE_STATE
+
+    .macro COMPARESF2_FUNCTION_BODY handle_nan:req
+#if defined(COMPILER_RT_ARMHF_TARGET)
+    vmov r0, s0
+    vmov r1, s1
+#endif
     // Make copies of a and b with the sign bit shifted off the top.  These will
     // be used to detect zeros and NaNs.
+#if defined(USE_THUMB_1)
+    push    {r6, lr}
+    lsls    r2,         r0, #1
+    lsls    r3,         r1, #1
+#else
     mov     r2,         r0, lsl #1
     mov     r3,         r1, lsl #1
+#endif
 
     // We do the comparison in three stages (ignoring NaN values for the time
     // being).  First, we orr the absolute values of a and b; this sets the Z
     // flag if both a and b are zero (of either sign).  The shift of r3 doesn't
     // effect this at all, but it *does* make sure that the C flag is clear for
     // the subsequent operations.
+#if defined(USE_THUMB_1)
+    lsrs    r6,     r3, #1
+    orrs    r6,     r2
+#else
     orrs    r12,    r2, r3, lsr #1
-
+#endif
     // Next, we check if a and b have the same or different signs.  If they have
     // opposite signs, this eor will set the N flag.
+#if defined(USE_THUMB_1)
+    beq     1f
+    movs    r6,     r0
+    eors    r6,     r1
+1:
+#else
     it ne
     eorsne  r12,    r0, r1
+#endif
 
     // If a and b are equal (either both zeros or bit identical; again, we're
     // ignoring NaNs for now), this subtract will zero out r0.  If they have the
     // same sign, the flags are updated as they would be for a comparison of the
     // absolute values of a and b.
+#if defined(USE_THUMB_1)
+    bmi     1f
+    subs    r0,     r2, r3
+1:
+#else
     it pl
     subspl  r0,     r2, r3
+#endif
 
     // If a is smaller in magnitude than b and both have the same sign, place
     // the negation of the sign of b in r0.  Thus, if both are negative and
@@ -76,73 +104,158 @@ DEFINE_COMPILERRT_FUNCTION(__eqsf2)
     // still clear from the shift argument in orrs; if a is positive and b
     // negative, this places 0 in r0; if a is negative and b positive, -1 is
     // placed in r0.
+#if defined(USE_THUMB_1)
+    bhs     1f
+    // Here if a and b have the same sign and absA < absB, the result is thus
+    // b < 0 ? 1 : -1. Same if a and b have the opposite sign (ignoring Nan).
+    movs    r0,         #1
+    lsrs    r1,         #31
+    bne     LOCAL_LABEL(CHECK_NAN\@)
+    negs    r0,         r0
+    b       LOCAL_LABEL(CHECK_NAN\@)
+1:
+#else
     it lo
     mvnlo   r0,         r1, asr #31
+#endif
 
     // If a is greater in magnitude than b and both have the same sign, place
     // the sign of b in r0.  Thus, if both are negative and a < b, -1 is placed
     // in r0, which is the desired result.  Conversely, if both are positive
     // and a > b, zero is placed in r0.
+#if defined(USE_THUMB_1)
+    bls     1f
+    // Here both have the same sign and absA > absB.
+    movs    r0,         #1
+    lsrs    r1,         #31
+    beq     LOCAL_LABEL(CHECK_NAN\@)
+    negs    r0, r0
+1:
+#else
     it hi
     movhi   r0,         r1, asr #31
+#endif
 
     // If you've been keeping track, at this point r0 contains -1 if a < b and
     // 0 if a >= b.  All that remains to be done is to set it to 1 if a > b.
     // If a == b, then the Z flag is set, so we can get the correct final value
     // into r0 by simply or'ing with 1 if Z is clear.
+    // For Thumb-1, r0 contains -1 if a < b, 0 if a > b and 0 if a == b.
+#if !defined(USE_THUMB_1)
     it ne
     orrne   r0,     r0, #1
+#endif
 
     // Finally, we need to deal with NaNs.  If either argument is NaN, replace
     // the value in r0 with 1.
+#if defined(USE_THUMB_1)
+LOCAL_LABEL(CHECK_NAN\@):
+    movs    r6,         #0xff
+    lsls    r6,         #24
+    cmp     r2,         r6
+    bhi     1f
+    cmp     r3,         r6
+1:
+    bls     2f
+    \handle_nan
+2:
+    pop     {r6, pc}
+#else
     cmp     r2,         #0xff000000
     ite ls
     cmpls   r3,         #0xff000000
-    movhi   r0,         #1
+    \handle_nan
     JMP(lr)
+#endif
+    .endm
+
+@ int __eqsf2(float a, float b)
+
+    .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__eqsf2)
+
+    .macro __eqsf2_handle_nan
+#if defined(USE_THUMB_1)
+    movs    r0,         #1
+#else
+    movhi   r0,         #1
+#endif
+    .endm
+
+COMPARESF2_FUNCTION_BODY __eqsf2_handle_nan
+
 END_COMPILERRT_FUNCTION(__eqsf2)
+
 DEFINE_COMPILERRT_FUNCTION_ALIAS(__lesf2, __eqsf2)
 DEFINE_COMPILERRT_FUNCTION_ALIAS(__ltsf2, __eqsf2)
 DEFINE_COMPILERRT_FUNCTION_ALIAS(__nesf2, __eqsf2)
 
-.p2align 2
+#if defined(__ELF__)
+// Alias for libgcc compatibility
+DEFINE_COMPILERRT_FUNCTION_ALIAS(__cmpsf2, __lesf2)
+#endif
+
+@ int __gtsf2(float a, float b)
+
+    .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__gtsf2)
-    // Identical to the preceding except in that we return -1 for NaN values.
-    // Given that the two paths share so much code, one might be tempted to 
-    // unify them; however, the extra code needed to do so makes the code size
-    // to performance tradeoff very hard to justify for such small functions.
-    mov     r2,         r0, lsl #1
-    mov     r3,         r1, lsl #1
-    orrs    r12,    r2, r3, lsr #1
-    it ne
-    eorsne  r12,    r0, r1
-    it pl
-    subspl  r0,     r2, r3
-    it lo
-    mvnlo   r0,         r1, asr #31
-    it hi
-    movhi   r0,         r1, asr #31
-    it ne
-    orrne   r0,     r0, #1
-    cmp     r2,         #0xff000000
-    ite ls
-    cmpls   r3,         #0xff000000
+
+    .macro __gtsf2_handle_nan
+#if defined(USE_THUMB_1)
+    movs    r0,         #1
+    negs    r0,         r0
+#else
     movhi   r0,         #-1
-    JMP(lr)
+#endif
+    .endm
+
+COMPARESF2_FUNCTION_BODY __gtsf2_handle_nan
+
 END_COMPILERRT_FUNCTION(__gtsf2)
+
 DEFINE_COMPILERRT_FUNCTION_ALIAS(__gesf2, __gtsf2)
 
-.p2align 2
+@ int __unordsf2(float a, float b)
+
+    .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__unordsf2)
+
+#if defined(COMPILER_RT_ARMHF_TARGET)
+    vmov    r0,         s0
+    vmov    r1,         s1
+#endif
     // Return 1 for NaN values, 0 otherwise.
-    mov     r2,         r0, lsl #1
-    mov     r3,         r1, lsl #1
-    mov     r0,         #0
+    lsls    r2,         r0, #1
+    lsls    r3,         r1, #1
+    movs    r0,         #0
+#if defined(USE_THUMB_1)
+    movs    r1,         #0xff
+    lsls    r1,         #24
+    cmp     r2,         r1
+    bhi     1f
+    cmp     r3,         r1
+1:
+    bls     2f
+    movs    r0,         #1
+2:
+#else
     cmp     r2,         #0xff000000
     ite ls
     cmpls   r3,         #0xff000000
     movhi   r0,         #1
+#endif
     JMP(lr)
 END_COMPILERRT_FUNCTION(__unordsf2)
 
+#if defined(COMPILER_RT_ARMHF_TARGET)
+DEFINE_COMPILERRT_FUNCTION(__aeabi_fcmpun)
+       vmov s0, r0
+       vmov s1, r1
+       b SYMBOL_NAME(__unordsf2)
+END_COMPILERRT_FUNCTION(__aeabi_fcmpun)
+#else
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_fcmpun, __unordsf2)
+#endif
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/divdf3vfp.S b/lib/compiler-rt/builtins/arm/divdf3vfp.S
new file mode 100644 (file)
index 0000000..ad50b57
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- divdf3vfp.S - Implement divdf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __divdf3vfp(double a, double b);
+//
+// Divides two double precision floating point numbers using the Darwin
+// calling convention where double arguments are passsed in GPR pairs
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__divdf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vdiv.f64 d0, d0, d1
+#else
+       vmov    d6, r0, r1              // move first param from r0/r1 pair into d6
+       vmov    d7, r2, r3              // move second param from r2/r3 pair into d7
+       vdiv.f64 d5, d6, d7
+       vmov    r0, r1, d5              // move result back to r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__divdf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index d1c6d6c..f94438d 100644 (file)
@@ -1,17 +1,16 @@
-/*===-- divmodsi4.S - 32-bit signed integer divide and modulus ------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __divmodsi4 (32-bit signed integer divide and
- * modulus) function for the ARM architecture.  A naive digit-by-digit
- * computation is employed for simplicity.
- *
- *===----------------------------------------------------------------------===*/
+//===-- divmodsi4.S - 32-bit signed integer divide and modulus ------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __divmodsi4 (32-bit signed integer divide and
+// modulus) function for the ARM architecture.  A naive digit-by-digit
+// computation is employed for simplicity.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
@@ -23,6 +22,7 @@
 
        .syntax unified
        .text
+  DEFINE_CODE_STATE
 
 @ int __divmodsi4(int divident, int divisor, int *remainder)
 @   Calculate the quotient and remainder of the (signed) division.  The return
@@ -65,3 +65,6 @@ LOCAL_LABEL(divzero):
     CLEAR_FRAME_AND_RETURN
 #endif
 END_COMPILERRT_FUNCTION(__divmodsi4)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/divsf3vfp.S b/lib/compiler-rt/builtins/arm/divsf3vfp.S
new file mode 100644 (file)
index 0000000..958a672
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- divsf3vfp.S - Implement divsf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __divsf3vfp(float a, float b);
+//
+// Divides two single precision floating point numbers using the Darwin
+// calling convention where single arguments are passsed like 32-bit ints.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__divsf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vdiv.f32 s0, s0, s1
+#else
+       vmov    s14, r0         // move first param from r0 into float register
+       vmov    s15, r1         // move second param from r1 into float register
+       vdiv.f32 s13, s14, s15
+       vmov    r0, s13         // move result back to r0
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__divsf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 23a428d..761bf49 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- divsi3.S - 32-bit signed integer divide ---------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __divsi3 (32-bit signed integer divide) function
- * for the ARM architecture as a wrapper around the unsigned routine.
- *
- *===----------------------------------------------------------------------===*/
+//===-- divsi3.S - 32-bit signed integer divide ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __divsi3 (32-bit signed integer divide) function
+// for the ARM architecture as a wrapper around the unsigned routine.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
@@ -20,8 +19,9 @@
 #define CLEAR_FRAME_AND_RETURN \
     pop    {r4, r7, pc}
 
-       .syntax unified
-       .text
+   .syntax unified
+   .text
+   DEFINE_CODE_STATE
 
        .p2align 3
 // Ok, APCS and AAPCS agree on 32 bit args, so it's safe to use the same routine.
@@ -42,17 +42,40 @@ LOCAL_LABEL(divzero):
 #else
 ESTABLISH_FRAME
 //  Set aside the sign of the quotient.
+#  if defined(USE_THUMB_1)
+    movs    r4,     r0
+    eors    r4,     r1
+#  else
     eor     r4,     r0, r1
+#  endif
 //  Take absolute value of a and b via abs(x) = (x^(x >> 31)) - (x >> 31).
+#  if defined(USE_THUMB_1)
+    asrs    r2,     r0, #31
+    asrs    r3,     r1, #31
+    eors    r0,     r2
+    eors    r1,     r3
+    subs    r0,     r0, r2
+    subs    r1,     r1, r3
+#  else
     eor     r2,     r0, r0, asr #31
     eor     r3,     r1, r1, asr #31
     sub     r0,     r2, r0, asr #31
     sub     r1,     r3, r1, asr #31
+#  endif
 //  abs(a) / abs(b)
     bl      SYMBOL_NAME(__udivsi3)
 //  Apply sign of quotient to result and return.
+#  if defined(USE_THUMB_1)
+    asrs    r4,     #31
+    eors    r0,     r4
+    subs    r0,     r0, r4
+#  else
     eor     r0,     r0, r4, asr #31
     sub     r0,     r0, r4, asr #31
+#  endif
     CLEAR_FRAME_AND_RETURN
 #endif
 END_COMPILERRT_FUNCTION(__divsi3)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/eqdf2vfp.S b/lib/compiler-rt/builtins/arm/eqdf2vfp.S
new file mode 100644 (file)
index 0000000..2a0a64b
--- /dev/null
@@ -0,0 +1,35 @@
+//===-- eqdf2vfp.S - Implement eqdf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+// extern int __eqdf2vfp(double a, double b);
+//
+// Returns one iff a == b and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(eq)
+       moveq   r0, #1          // set result register to 1 if equal
+       movne   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__eqdf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/eqsf2vfp.S b/lib/compiler-rt/builtins/arm/eqsf2vfp.S
new file mode 100644 (file)
index 0000000..5fefe7b
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- eqsf2vfp.S - Implement eqsf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __eqsf2vfp(float a, float b);
+//
+// Returns one iff a == b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__eqsf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0     // move from GPR 0 to float register
+       vmov    s15, r1     // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(eq)
+       moveq   r0, #1      // set result register to 1 if equal
+       movne   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__eqsf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/extendsfdf2vfp.S b/lib/compiler-rt/builtins/arm/extendsfdf2vfp.S
new file mode 100644 (file)
index 0000000..37c8be8
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- extendsfdf2vfp.S - Implement extendsfdf2vfp -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __extendsfdf2vfp(float a);
+//
+// Converts single precision float to double precision result.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR and a double precision result is returned in R0/R1 pair.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.f64.f32 d0, s0
+#else
+       vmov    s15, r0      // load float register from R0
+       vcvt.f64.f32 d7, s15 // convert single to double
+       vmov    r0, r1, d7   // return result in r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__extendsfdf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/fixdfsivfp.S b/lib/compiler-rt/builtins/arm/fixdfsivfp.S
new file mode 100644 (file)
index 0000000..af1d4f4
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- fixdfsivfp.S - Implement fixdfsivfp -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __fixdfsivfp(double a);
+//
+// Converts double precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in GPR register pair.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.s32.f64 s0, d0
+       vmov r0, s0
+#else
+       vmov    d7, r0, r1    // load double register from R0/R1
+       vcvt.s32.f64 s15, d7  // convert double to 32-bit int into s15
+       vmov    r0, s15       // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__fixdfsivfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/fixsfsivfp.S b/lib/compiler-rt/builtins/arm/fixsfsivfp.S
new file mode 100644 (file)
index 0000000..30b2f3c
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- fixsfsivfp.S - Implement fixsfsivfp -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __fixsfsivfp(float a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR..
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__fixsfsivfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.s32.f32 s0, s0
+       vmov r0, s0
+#else
+       vmov    s15, r0        // load float register from R0
+       vcvt.s32.f32 s15, s15  // convert single to 32-bit int into s15
+       vmov    r0, s15        // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__fixsfsivfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/fixunsdfsivfp.S b/lib/compiler-rt/builtins/arm/fixunsdfsivfp.S
new file mode 100644 (file)
index 0000000..44e6dbd
--- /dev/null
@@ -0,0 +1,34 @@
+//===-- fixunsdfsivfp.S - Implement fixunsdfsivfp -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern unsigned int __fixunsdfsivfp(double a);
+//
+// Converts double precision float to a 32-bit unsigned int rounding towards
+// zero. All negative values become zero.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in GPR register pair.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.u32.f64 s0, d0
+       vmov r0, s0
+#else
+       vmov    d7, r0, r1    // load double register from R0/R1
+       vcvt.u32.f64 s15, d7  // convert double to 32-bit int into s15
+       vmov    r0, s15       // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__fixunsdfsivfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/fixunssfsivfp.S b/lib/compiler-rt/builtins/arm/fixunssfsivfp.S
new file mode 100644 (file)
index 0000000..5d6ee7c
--- /dev/null
@@ -0,0 +1,34 @@
+//===-- fixunssfsivfp.S - Implement fixunssfsivfp -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern unsigned int __fixunssfsivfp(float a);
+//
+// Converts single precision float to a 32-bit unsigned int rounding towards
+// zero. All negative values become zero.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR..
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__fixunssfsivfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.u32.f32 s0, s0
+       vmov r0, s0
+#else
+       vmov    s15, r0        // load float register from R0
+       vcvt.u32.f32 s15, s15  // convert single to 32-bit unsigned into s15
+       vmov    r0, s15        // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__fixunssfsivfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/floatsidfvfp.S b/lib/compiler-rt/builtins/arm/floatsidfvfp.S
new file mode 100644 (file)
index 0000000..ae8d246
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- floatsidfvfp.S - Implement floatsidfvfp ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __floatsidfvfp(int a);
+//
+// Converts a 32-bit int to a double precision float.
+// Uses Darwin calling convention where a double precision result is
+// return in GPR register pair.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmov s0, r0
+       vcvt.f64.s32 d0, s0
+#else
+       vmov    s15, r0        // move int to float register s15
+       vcvt.f64.s32 d7, s15   // convert 32-bit int in s15 to double in d7
+       vmov    r0, r1, d7     // move d7 to result register pair r0/r1
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__floatsidfvfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/floatsisfvfp.S b/lib/compiler-rt/builtins/arm/floatsisfvfp.S
new file mode 100644 (file)
index 0000000..a36bc5e
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- floatsisfvfp.S - Implement floatsisfvfp ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __floatsisfvfp(int a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision result is
+// return in a GPR..
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__floatsisfvfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmov s0, r0
+       vcvt.f32.s32 s0, s0
+#else
+       vmov    s15, r0        // move int to float register s15
+       vcvt.f32.s32 s15, s15  // convert 32-bit int in s15 to float in s15
+       vmov    r0, s15        // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__floatsisfvfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/floatunssidfvfp.S b/lib/compiler-rt/builtins/arm/floatunssidfvfp.S
new file mode 100644 (file)
index 0000000..0932dab
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- floatunssidfvfp.S - Implement floatunssidfvfp ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __floatunssidfvfp(unsigned int a);
+//
+// Converts a 32-bit int to a double precision float.
+// Uses Darwin calling convention where a double precision result is
+// return in GPR register pair.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmov s0, r0
+       vcvt.f64.u32 d0, s0
+#else
+       vmov    s15, r0        // move int to float register s15
+       vcvt.f64.u32 d7, s15   // convert 32-bit int in s15 to double in d7
+       vmov    r0, r1, d7     // move d7 to result register pair r0/r1
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__floatunssidfvfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/floatunssisfvfp.S b/lib/compiler-rt/builtins/arm/floatunssisfvfp.S
new file mode 100644 (file)
index 0000000..9578546
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- floatunssisfvfp.S - Implement floatunssisfvfp ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __floatunssisfvfp(unsigned int a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision result is
+// return in a GPR..
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__floatunssisfvfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmov s0, r0
+       vcvt.f32.u32 s0, s0
+#else
+       vmov    s15, r0        // move int to float register s15
+       vcvt.f32.u32 s15, s15  // convert 32-bit int in s15 to float in s15
+       vmov    r0, s15        // move s15 to result register
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__floatunssisfvfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/gedf2vfp.S b/lib/compiler-rt/builtins/arm/gedf2vfp.S
new file mode 100644 (file)
index 0000000..2af9d90
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- gedf2vfp.S - Implement gedf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __gedf2vfp(double a, double b);
+//
+// Returns one iff a >= b and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__gedf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ge)
+       movge   r0, #1      // set result register to 1 if greater than or equal
+       movlt   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__gedf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/gesf2vfp.S b/lib/compiler-rt/builtins/arm/gesf2vfp.S
new file mode 100644 (file)
index 0000000..cedd1e1
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- gesf2vfp.S - Implement gesf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __gesf2vfp(float a, float b);
+//
+// Returns one iff a >= b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__gesf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0     // move from GPR 0 to float register
+       vmov    s15, r1     // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ge)
+       movge   r0, #1      // set result register to 1 if greater than or equal
+       movlt   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__gesf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/gtdf2vfp.S b/lib/compiler-rt/builtins/arm/gtdf2vfp.S
new file mode 100644 (file)
index 0000000..782ad8c
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- gtdf2vfp.S - Implement gtdf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __gtdf2vfp(double a, double b);
+//
+// Returns one iff a > b and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__gtdf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(gt)
+       movgt   r0, #1          // set result register to 1 if equal
+       movle   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__gtdf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/gtsf2vfp.S b/lib/compiler-rt/builtins/arm/gtsf2vfp.S
new file mode 100644 (file)
index 0000000..1cc2bd1
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- gtsf2vfp.S - Implement gtsf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __gtsf2vfp(float a, float b);
+//
+// Returns one iff a > b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__gtsf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0         // move from GPR 0 to float register
+       vmov    s15, r1         // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(gt)
+       movgt   r0, #1          // set result register to 1 if equal
+       movle   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__gtsf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/ledf2vfp.S b/lib/compiler-rt/builtins/arm/ledf2vfp.S
new file mode 100644 (file)
index 0000000..0097e4b
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- ledf2vfp.S - Implement ledf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __ledf2vfp(double a, double b);
+//
+// Returns one iff a <= b and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__ledf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ls)
+       movls   r0, #1          // set result register to 1 if equal
+       movhi   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__ledf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/lesf2vfp.S b/lib/compiler-rt/builtins/arm/lesf2vfp.S
new file mode 100644 (file)
index 0000000..2052d38
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- lesf2vfp.S - Implement lesf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __lesf2vfp(float a, float b);
+//
+// Returns one iff a <= b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__lesf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0     // move from GPR 0 to float register
+       vmov    s15, r1     // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ls)
+       movls   r0, #1      // set result register to 1 if equal
+       movhi   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__lesf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/ltdf2vfp.S b/lib/compiler-rt/builtins/arm/ltdf2vfp.S
new file mode 100644 (file)
index 0000000..a126aa9
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- ltdf2vfp.S - Implement ltdf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __ltdf2vfp(double a, double b);
+//
+// Returns one iff a < b and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__ltdf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(mi)
+       movmi   r0, #1          // set result register to 1 if equal
+       movpl   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__ltdf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/ltsf2vfp.S b/lib/compiler-rt/builtins/arm/ltsf2vfp.S
new file mode 100644 (file)
index 0000000..ba10d71
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- ltsf2vfp.S - Implement ltsf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __ltsf2vfp(float a, float b);
+//
+// Returns one iff a < b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__ltsf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0     // move from GPR 0 to float register
+       vmov    s15, r1     // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(mi)
+       movmi   r0, #1      // set result register to 1 if equal
+       movpl   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__ltsf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index f53d58d..5312f5b 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- modsi3.S - 32-bit signed integer modulus --------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __modsi3 (32-bit signed integer modulus) function
- * for the ARM architecture as a wrapper around the unsigned routine.
- *
- *===----------------------------------------------------------------------===*/
+//===-- modsi3.S - 32-bit signed integer modulus --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __modsi3 (32-bit signed integer modulus) function
+// for the ARM architecture as a wrapper around the unsigned routine.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
@@ -22,6 +21,7 @@
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
 @ int __modsi3(int divident, int divisor)
 @   Calculate and return the remainder of the (signed) division.
@@ -54,3 +54,6 @@ LOCAL_LABEL(divzero):
     CLEAR_FRAME_AND_RETURN
 #endif
 END_COMPILERRT_FUNCTION(__modsi3)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/muldf3vfp.S b/lib/compiler-rt/builtins/arm/muldf3vfp.S
new file mode 100644 (file)
index 0000000..9adc937
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- muldf3vfp.S - Implement muldf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __muldf3vfp(double a, double b);
+//
+// Multiplies two double precision floating point numbers using the Darwin
+// calling convention where double arguments are passsed in GPR pairs
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__muldf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmul.f64 d0, d0, d1
+#else
+       vmov    d6, r0, r1         // move first param from r0/r1 pair into d6
+       vmov    d7, r2, r3         // move second param from r2/r3 pair into d7
+       vmul.f64 d6, d6, d7
+       vmov    r0, r1, d6         // move result back to r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__muldf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/mulsf3vfp.S b/lib/compiler-rt/builtins/arm/mulsf3vfp.S
new file mode 100644 (file)
index 0000000..a94131b
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- mulsf3vfp.S - Implement mulsf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __mulsf3vfp(float a, float b);
+//
+// Multiplies two single precision floating point numbers using the Darwin
+// calling convention where single arguments are passsed like 32-bit ints.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__mulsf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vmul.f32 s0, s0, s1
+#else
+       vmov    s14, r0         // move first param from r0 into float register
+       vmov    s15, r1         // move second param from r1 into float register
+       vmul.f32 s13, s14, s15
+#endif
+       vmov    r0, s13         // move result back to r0
+       bx      lr
+END_COMPILERRT_FUNCTION(__mulsf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/nedf2vfp.S b/lib/compiler-rt/builtins/arm/nedf2vfp.S
new file mode 100644 (file)
index 0000000..32d35c4
--- /dev/null
@@ -0,0 +1,35 @@
+//===-- nedf2vfp.S - Implement nedf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+// extern double __nedf2vfp(double a, double b);
+//
+// Returns zero if a and b are unequal and neither is NaN.
+// Uses Darwin calling convention where double precision arguments are passsed
+// like in GPR pairs.
+
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__nedf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f64 d0, d1
+#else
+       vmov    d6, r0, r1      // load r0/r1 pair in double register
+       vmov    d7, r2, r3      // load r2/r3 pair in double register
+       vcmp.f64 d6, d7
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ne)
+       movne   r0, #1          // set result register to 0 if unequal
+       moveq   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__nedf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/negdf2vfp.S b/lib/compiler-rt/builtins/arm/negdf2vfp.S
new file mode 100644 (file)
index 0000000..b7cf918
--- /dev/null
@@ -0,0 +1,29 @@
+//===-- negdf2vfp.S - Implement negdf2vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __negdf2vfp(double a, double b);
+//
+// Returns the negation a double precision floating point numbers using the
+// Darwin calling convention where double arguments are passsed in GPR pairs.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__negdf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vneg.f64 d0, d0
+#else
+       eor     r1, r1, #-2147483648    // flip sign bit on double in r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__negdf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/negsf2vfp.S b/lib/compiler-rt/builtins/arm/negsf2vfp.S
new file mode 100644 (file)
index 0000000..b6d3c61
--- /dev/null
@@ -0,0 +1,29 @@
+//===-- negsf2vfp.S - Implement negsf2vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __negsf2vfp(float a);
+//
+// Returns the negation of a single precision floating point numbers using the
+// Darwin calling convention where single arguments are passsed like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__negsf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vneg.f32 s0, s0
+#else
+       eor     r0, r0, #-2147483648    // flip sign bit on float in r0
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__negsf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/nesf2vfp.S b/lib/compiler-rt/builtins/arm/nesf2vfp.S
new file mode 100644 (file)
index 0000000..34c8bb4
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- nesf2vfp.S - Implement nesf2vfp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern int __nesf2vfp(float a, float b);
+//
+// Returns one iff a != b and neither is NaN.
+// Uses Darwin calling convention where single precision arguments are passsed
+// like 32-bit ints
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__nesf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcmp.f32 s0, s1
+#else
+       vmov    s14, r0     // move from GPR 0 to float register
+       vmov    s15, r1     // move from GPR 1 to float register
+       vcmp.f32 s14, s15
+#endif
+       vmrs    apsr_nzcv, fpscr
+       ITE(ne)
+       movne   r0, #1      // set result register to 1 if unequal
+       moveq   r0, #0
+       bx      lr
+END_COMPILERRT_FUNCTION(__nesf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/restore_vfp_d8_d15_regs.S b/lib/compiler-rt/builtins/arm/restore_vfp_d8_d15_regs.S
new file mode 100644 (file)
index 0000000..fd6d59b
--- /dev/null
@@ -0,0 +1,34 @@
+//===-- save_restore_regs.S - Implement save/restore* ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// When compiling C++ functions that need to handle thrown exceptions the
+// compiler is required to save all registers and call __Unwind_SjLj_Register
+// in the function prolog.  But when compiling for thumb1, there are
+// no instructions to access the floating point registers, so the
+// compiler needs to add a call to the helper function _save_vfp_d8_d15_regs
+// written in ARM to save the float registers.  In the epilog, the compiler
+// must also add a call to __restore_vfp_d8_d15_regs to restore those registers.
+//
+
+       .text
+       .syntax unified
+
+//
+// Restore registers d8-d15 from stack
+//
+       .p2align 2
+DEFINE_COMPILERRT_PRIVATE_FUNCTION(__restore_vfp_d8_d15_regs)
+       vldmia  sp!, {d8-d15}           // pop registers d8-d15 off stack
+       bx      lr                      // return to prolog
+END_COMPILERRT_FUNCTION(__restore_vfp_d8_d15_regs)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/save_vfp_d8_d15_regs.S b/lib/compiler-rt/builtins/arm/save_vfp_d8_d15_regs.S
new file mode 100644 (file)
index 0000000..5eb3a2f
--- /dev/null
@@ -0,0 +1,34 @@
+//===-- save_restore_regs.S - Implement save/restore* ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// When compiling C++ functions that need to handle thrown exceptions the
+// compiler is required to save all registers and call __Unwind_SjLj_Register
+// in the function prolog.  But when compiling for thumb1, there are
+// no instructions to access the floating point registers, so the
+// compiler needs to add a call to the helper function _save_vfp_d8_d15_regs
+// written in ARM to save the float registers.  In the epilog, the compiler
+// must also add a call to __restore_vfp_d8_d15_regs to restore those registers.
+//
+
+       .text
+       .syntax unified
+
+//
+// Save registers d8-d15 onto stack
+//
+       .p2align 2
+DEFINE_COMPILERRT_PRIVATE_FUNCTION(__save_vfp_d8_d15_regs)
+       vstmdb  sp!, {d8-d15}           // push registers d8-d15 onto stack
+       bx      lr                      // return to prolog
+END_COMPILERRT_FUNCTION(__save_vfp_d8_d15_regs)
+
+NO_EXEC_STACK_DIRECTIVE
+
index cc6a4b3..ab6ed21 100644 (file)
@@ -1,5 +1,5 @@
 #
-# These are soft float functions which can be 
+# These are soft float functions which can be
 # aliased to the *vfp functions on arm processors
 # that support floating point instructions.
 #
diff --git a/lib/compiler-rt/builtins/arm/subdf3vfp.S b/lib/compiler-rt/builtins/arm/subdf3vfp.S
new file mode 100644 (file)
index 0000000..f4eaf9a
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- subdf3vfp.S - Implement subdf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern double __subdf3vfp(double a, double b);
+//
+// Returns difference between two double precision floating point numbers using
+// the Darwin calling convention where double arguments are passsed in GPR pairs
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__subdf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vsub.f64 d0, d0, d1
+#else
+       vmov    d6, r0, r1         // move first param from r0/r1 pair into d6
+       vmov    d7, r2, r3         // move second param from r2/r3 pair into d7
+       vsub.f64 d6, d6, d7
+       vmov    r0, r1, d6         // move result back to r0/r1 pair
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__subdf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/subsf3vfp.S b/lib/compiler-rt/builtins/arm/subsf3vfp.S
new file mode 100644 (file)
index 0000000..80e69f2
--- /dev/null
@@ -0,0 +1,33 @@
+//===-- subsf3vfp.S - Implement subsf3vfp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __subsf3vfp(float a, float b);
+//
+// Returns the difference between two single precision floating point numbers
+// using the Darwin calling convention where single arguments are passsed
+// like 32-bit ints.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__subsf3vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vsub.f32 s0, s0, s1
+#else
+       vmov    s14, r0         // move first param from r0 into float register
+       vmov    s15, r1         // move second param from r1 into float register
+       vsub.f32 s14, s14, s15
+       vmov    r0, s14         // move result back to r0
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__subsf3vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index 3c3a6b1..a4b568d 100644 (file)
@@ -1,9 +1,8 @@
 //===-- switch.S - Implement switch* --------------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -42,3 +41,5 @@ DEFINE_COMPILERRT_PRIVATE_FUNCTION(__switch16)
        bx      ip                      // jump to computed label
 END_COMPILERRT_FUNCTION(__switch16)
 
+NO_EXEC_STACK_DIRECTIVE
+
index b38cd2b..f2a5af5 100644 (file)
@@ -1,9 +1,8 @@
 //===-- switch.S - Implement switch* --------------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -42,3 +41,5 @@ DEFINE_COMPILERRT_PRIVATE_FUNCTION(__switch32)
        bx      ip                       // jump to computed label
 END_COMPILERRT_FUNCTION(__switch32)
 
+NO_EXEC_STACK_DIRECTIVE
+
index d7c2042..0db875c 100644 (file)
@@ -1,9 +1,8 @@
 //===-- switch.S - Implement switch* --------------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -40,3 +39,5 @@ DEFINE_COMPILERRT_PRIVATE_FUNCTION(__switch8)
        bx      ip                      // jump to computed label
 END_COMPILERRT_FUNCTION(__switch8)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 1844f11..551abeb 100644 (file)
@@ -1,9 +1,8 @@
 //===-- switch.S - Implement switch* --------------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -40,3 +39,5 @@ DEFINE_COMPILERRT_PRIVATE_FUNCTION(__switchu8)
        bx      ip                      // jump to computed label
 END_COMPILERRT_FUNCTION(__switchu8)
 
+NO_EXEC_STACK_DIRECTIVE
+
index ee02c30..c962324 100644 (file)
@@ -1,64 +1,61 @@
-/*===-- sync-ops.h - --===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements outline macros for the __sync_fetch_and_*
- * operations. Different instantiations will generate appropriate assembly for
- * ARM and Thumb-2 versions of the functions.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync-ops.h - --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements outline macros for the __sync_fetch_and_*
+// operations. Different instantiations will generate appropriate assembly for
+// ARM and Thumb-2 versions of the functions.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
-#define SYNC_OP_4(op) \
-        .p2align 2 ; \
-        .thumb ; \
-        .syntax unified ; \
-        DEFINE_COMPILERRT_THUMB_FUNCTION(__sync_fetch_and_ ## op) \
-        dmb ; \
-        mov r12, r0 ; \
-        LOCAL_LABEL(tryatomic_ ## op): \
-        ldrex r0, [r12] ; \
-        op(r2, r0, r1) ; \
-        strex r3, r2, [r12] ; \
-        cmp r3, #0 ; \
-        bne LOCAL_LABEL(tryatomic_ ## op) ; \
-        dmb ; \
-        bx lr
+#define SYNC_OP_4(op)                                                          \
+  .p2align 2;                                                                  \
+  .thumb;                                                                      \
+  .syntax unified;                                                             \
+  DEFINE_COMPILERRT_THUMB_FUNCTION(__sync_fetch_and_##op)                      \
+  dmb;                                                                         \
+  mov r12, r0;                                                                 \
+  LOCAL_LABEL(tryatomic_##op) : ldrex r0, [r12];                               \
+  op(r2, r0, r1);                                                              \
+  strex r3, r2, [r12];                                                         \
+  cmp r3, #0;                                                                  \
+  bne LOCAL_LABEL(tryatomic_##op);                                             \
+  dmb;                                                                         \
+  bx lr
 
-#define SYNC_OP_8(op) \
-        .p2align 2 ; \
-        .thumb ; \
-        .syntax unified ; \
-        DEFINE_COMPILERRT_THUMB_FUNCTION(__sync_fetch_and_ ## op) \
-        push {r4, r5, r6, lr} ; \
-        dmb ; \
-        mov r12, r0 ; \
-        LOCAL_LABEL(tryatomic_ ## op): \
-        ldrexd r0, r1, [r12] ; \
-        op(r4, r5, r0, r1, r2, r3) ; \
-        strexd r6, r4, r5, [r12] ; \
-        cmp r6, #0 ; \
-        bne LOCAL_LABEL(tryatomic_ ## op) ; \
-        dmb ; \
-        pop {r4, r5, r6, pc}
+#define SYNC_OP_8(op)                                                          \
+  .p2align 2;                                                                  \
+  .thumb;                                                                      \
+  .syntax unified;                                                             \
+  DEFINE_COMPILERRT_THUMB_FUNCTION(__sync_fetch_and_##op)                      \
+  push {r4, r5, r6, lr};                                                       \
+  dmb;                                                                         \
+  mov r12, r0;                                                                 \
+  LOCAL_LABEL(tryatomic_##op) : ldrexd r0, r1, [r12];                          \
+  op(r4, r5, r0, r1, r2, r3);                                                  \
+  strexd r6, r4, r5, [r12];                                                    \
+  cmp r6, #0;                                                                  \
+  bne LOCAL_LABEL(tryatomic_##op);                                             \
+  dmb;                                                                         \
+  pop { r4, r5, r6, pc }
 
-#define MINMAX_4(rD, rN, rM, cmp_kind) \
-        cmp rN, rM ; \
-        mov rD, rM ; \
-        it cmp_kind ; \
-        mov##cmp_kind rD, rN
+#define MINMAX_4(rD, rN, rM, cmp_kind)                                         \
+  cmp rN, rM;                                                                  \
+  mov rD, rM;                                                                  \
+  it cmp_kind;                                                                 \
+  mov##cmp_kind rD, rN
 
-#define MINMAX_8(rD_LO, rD_HI, rN_LO, rN_HI, rM_LO, rM_HI, cmp_kind) \
-        cmp rN_LO, rM_LO ; \
-        sbcs rN_HI, rM_HI ; \
-        mov rD_LO, rM_LO ; \
-        mov rD_HI, rM_HI ; \
-        itt cmp_kind ; \
-        mov##cmp_kind rD_LO, rN_LO ; \
-        mov##cmp_kind rD_HI, rN_HI
+#define MINMAX_8(rD_LO, rD_HI, rN_LO, rN_HI, rM_LO, rM_HI, cmp_kind)           \
+  cmp rN_LO, rM_LO;                                                            \
+  sbcs rN_HI, rM_HI;                                                           \
+  mov rD_LO, rM_LO;                                                            \
+  mov rD_HI, rM_HI;                                                            \
+  itt cmp_kind;                                                                \
+  mov##cmp_kind rD_LO, rN_LO;                                                  \
+  mov##cmp_kind rD_HI, rN_HI
index 54c33e2..0d55975 100644 (file)
@@ -1,21 +1,22 @@
-/*===-- sync_fetch_and_add_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_add_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_add_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_add_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
-/* "adds" is 2 bytes shorter than "add". */
+// "adds" is 2 bytes shorter than "add".
 #define add_4(rD, rN, rM)  add rD, rN, rM
 
 SYNC_OP_4(add_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 5724bb1..18bdd87 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_add_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_add_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_add_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_add_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -22,3 +21,5 @@
 SYNC_OP_8(add_8)
 #endif
 
+NO_EXEC_STACK_DIRECTIVE
+
index e2b77a1..3a76acc 100644 (file)
@@ -1,19 +1,21 @@
-/*===-- sync_fetch_and_and_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_and_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_and_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_and_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
 #define and_4(rD, rN, rM)  and rD, rN, rM
 
 SYNC_OP_4(and_4)
+
+NO_EXEC_STACK_DIRECTIVE
+
index a74163a..3716eff 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_and_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_and_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_and_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_and_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -21,3 +20,6 @@
 
 SYNC_OP_8(and_8)
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
index 01e4f44..b9cee45 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_max_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_max_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_max_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_max_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(max_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 1eef2b2..06115ab 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_max_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_max_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_max_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_max_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -19,3 +18,6 @@
 
 SYNC_OP_8(max_8)
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
index 015626b..60d435a 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_min_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_min_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_min_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_min_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(min_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index ad5cce0..4f3e299 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_min_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_min_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_min_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_min_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -19,3 +18,6 @@
 
 SYNC_OP_8(min_8)
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
index b32a314..5a04be0 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_nand_4.S - -----------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_nand_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_nand_4.S - -----------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_nand_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(nand_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index a2c17c0..425c944 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_nand_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_nand_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_nand_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_nand_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -22,3 +21,5 @@
 SYNC_OP_8(nand_8)
 #endif
 
+NO_EXEC_STACK_DIRECTIVE
+
index f2e0857..f44751b 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_or_4.S - -------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_or_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_or_4.S - -------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_or_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(or_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 87b940b..4f18dcf 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_or_8.S - -------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_or_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_or_8.S - -------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_or_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -22,3 +21,5 @@
 SYNC_OP_8(or_8)
 #endif
 
+NO_EXEC_STACK_DIRECTIVE
+
index 460b2bc..999d48c 100644 (file)
@@ -1,21 +1,22 @@
-/*===-- sync_fetch_and_sub_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_sub_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_sub_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_sub_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
-/* "subs" is 2 bytes shorter than "sub". */
+// "subs" is 2 bytes shorter than "sub".
 #define sub_4(rD, rN, rM)  sub rD, rN, rM
 
 SYNC_OP_4(sub_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index a8035a2..25a4a10 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_sub_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_sub_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_sub_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_sub_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -22,3 +21,5 @@
 SYNC_OP_8(sub_8)
 #endif
 
+NO_EXEC_STACK_DIRECTIVE
+
index c591530..a7b233b 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_umax_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_umax_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_umax_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_umax_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(umax_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index d9b7965..aa5213f 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_umax_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_umax_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_umax_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_umax_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -19,3 +18,6 @@
 
 SYNC_OP_8(umax_8)
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
index 9f3896f..c7a9c89 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_umin_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_umin_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_umin_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_umin_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(umin_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index 7bf5e23..8b40541 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_umin_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_umin_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_umin_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_umin_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -19,3 +18,6 @@
 
 SYNC_OP_8(umin_8)
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
index 7e7c90c..f509191 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_xor_4.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_xor_4 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_xor_4.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_xor_4 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -18,3 +17,5 @@
 
 SYNC_OP_4(xor_4)
 
+NO_EXEC_STACK_DIRECTIVE
+
index ea9aa6d..7436eb1 100644 (file)
@@ -1,16 +1,15 @@
-/*===-- sync_fetch_and_xor_8.S - ------------------------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __sync_fetch_and_xor_8 function for the ARM
- * architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- sync_fetch_and_xor_8.S - ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __sync_fetch_and_xor_8 function for the ARM
+// architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "sync-ops.h"
 
@@ -22,3 +21,5 @@
 SYNC_OP_8(xor_8)
 #endif
 
+NO_EXEC_STACK_DIRECTIVE
+
index 178f245..dd06e71 100644 (file)
@@ -1,20 +1,17 @@
 //===-- sync_synchronize - Implement memory barrier * ----------------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
-//
 // When compiling a use of the gcc built-in __sync_synchronize() in thumb1 mode
-// the compiler may emit a call to __sync_synchronize.  
-// On Darwin the implementation jumps to an OS supplied function named 
+// the compiler may emit a call to __sync_synchronize.
+// On Darwin the implementation jumps to an OS supplied function named
 // OSMemoryBarrier
-//
 
        .text
        .syntax unified
@@ -31,5 +28,8 @@ END_COMPILERRT_FUNCTION(__sync_synchronize)
 
        // tell linker it can break up file at label boundaries
        .subsections_via_symbols
-               
+
 #endif
+
+NO_EXEC_STACK_DIRECTIVE
+
diff --git a/lib/compiler-rt/builtins/arm/truncdfsf2vfp.S b/lib/compiler-rt/builtins/arm/truncdfsf2vfp.S
new file mode 100644 (file)
index 0000000..a3c0a73
--- /dev/null
@@ -0,0 +1,32 @@
+//===-- truncdfsf2vfp.S - Implement truncdfsf2vfp -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+//
+// extern float __truncdfsf2vfp(double a);
+//
+// Converts double precision float to signle precision result.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in a R0/R1 pair and a signle precision result is returned in R0.
+//
+       .syntax unified
+       .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__truncdfsf2vfp)
+#if defined(COMPILER_RT_ARMHF_TARGET)
+       vcvt.f32.f64 s0, d0
+#else
+       vmov    d7, r0, r1   // load double from r0/r1 pair
+       vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
+       vmov    r0, s15      // return result in r0
+#endif
+       bx      lr
+END_COMPILERRT_FUNCTION(__truncdfsf2vfp)
+
+NO_EXEC_STACK_DIRECTIVE
+
index d6247e8..0f40575 100644 (file)
@@ -1,21 +1,21 @@
-/*===-- udivmodsi4.S - 32-bit unsigned integer divide and modulus ---------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __udivmodsi4 (32-bit unsigned integer divide and
- * modulus) function for the ARM 32-bit architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- udivmodsi4.S - 32-bit unsigned integer divide and modulus ---------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __udivmodsi4 (32-bit unsigned integer divide and
+// modulus) function for the ARM 32-bit architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
        .syntax unified
        .text
+       DEFINE_CODE_STATE
 
 @ unsigned int __udivmodsi4(unsigned int divident, unsigned int divisor,
 @                           unsigned int *remainder)
@@ -38,33 +38,40 @@ DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
        beq     LOCAL_LABEL(divby1)
        cmp     r0, r1
        bcc     LOCAL_LABEL(quotient0)
-       /*
-        * Implement division using binary long division algorithm.
-        *
-        * r0 is the numerator, r1 the denominator.
-        *
-        * The code before JMP computes the correct shift I, so that
-        * r0 and (r1 << I) have the highest bit set in the same position.
-        * At the time of JMP, ip := .Ldiv0block - 12 * I.
-        * This depends on the fixed instruction size of block.
-        * For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
-        *
-        * block(shift) implements the test-and-update-quotient core.
-        * It assumes (r0 << shift) can be computed without overflow and
-        * that (r0 << shift) < 2 * r1. The quotient is stored in r3.
-        */
+
+       // Implement division using binary long division algorithm.
+       //
+       // r0 is the numerator, r1 the denominator.
+       //
+       // The code before JMP computes the correct shift I, so that
+       // r0 and (r1 << I) have the highest bit set in the same position.
+       // At the time of JMP, ip := .Ldiv0block - 12 * I.
+       // This depends on the fixed instruction size of block.
+       // For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
+       //
+       // block(shift) implements the test-and-update-quotient core.
+       // It assumes (r0 << shift) can be computed without overflow and
+       // that (r0 << shift) < 2 * r1. The quotient is stored in r3.
 
 #  ifdef __ARM_FEATURE_CLZ
        clz     ip, r0
        clz     r3, r1
-       /* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
+       // r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3.
        sub     r3, r3, ip
+#    if defined(USE_THUMB_2)
+       adr     ip, LOCAL_LABEL(div0block) + 1
+       sub     ip, ip, r3, lsl #1
+#    else
        adr     ip, LOCAL_LABEL(div0block)
+#    endif
        sub     ip, ip, r3, lsl #2
        sub     ip, ip, r3, lsl #3
        mov     r3, #0
        bx      ip
 #  else
+#    if defined(USE_THUMB_2)
+#    error THUMB mode requires CLZ or UDIV
+#    endif
        str     r4, [sp, #-8]!
 
        mov     r4, r0
@@ -90,11 +97,11 @@ DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
        movhs   r4, r3
        subhs   ip, ip, #(2 * 12)
 
-       /* Last block, no need to update r3 or r4. */
+       // Last block, no need to update r3 or r4.
        cmp     r1, r4, lsr #1
        subls   ip, ip, #(1 * 12)
 
-       ldr     r4, [sp], #8    /* restore r4, we are done with it. */
+       ldr     r4, [sp], #8    // restore r4, we are done with it.
        mov     r3, #0
 
        JMP(ip)
@@ -155,7 +162,7 @@ LOCAL_LABEL(divby1):
        mov     r3, #0
        str     r3, [r2]
        JMP(lr)
-#endif /* __ARM_ARCH_EXT_IDIV__ */
+#endif // __ARM_ARCH_EXT_IDIV__
 
 LOCAL_LABEL(divby0):
        mov     r0, #0
@@ -166,3 +173,6 @@ LOCAL_LABEL(divby0):
 #endif
 
 END_COMPILERRT_FUNCTION(__udivmodsi4)
+
+NO_EXEC_STACK_DIRECTIVE
+
index bb539c1..9b1b035 100644 (file)
@@ -1,22 +1,23 @@
-/*===-- udivsi3.S - 32-bit unsigned integer divide ------------------------===//
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- *===----------------------------------------------------------------------===//
- *
- * This file implements the __udivsi3 (32-bit unsigned integer divide)
- * function for the ARM 32-bit architecture.
- *
- *===----------------------------------------------------------------------===*/
+//===-- udivsi3.S - 32-bit unsigned integer divide ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the __udivsi3 (32-bit unsigned integer divide)
+// function for the ARM 32-bit architecture.
+//
+//===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
        .syntax unified
        .text
 
+DEFINE_CODE_STATE
+
        .p2align 2
 DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_uidiv, __udivsi3)
 
@@ -29,81 +30,192 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
        beq     LOCAL_LABEL(divby0)
        udiv    r0, r0, r1
        bx      lr
-#else
+
+LOCAL_LABEL(divby0):
+       mov     r0, #0
+#  ifdef __ARM_EABI__
+       b       __aeabi_idiv0
+#  else
+       JMP(lr)
+#  endif
+
+#else // ! __ARM_ARCH_EXT_IDIV__
        cmp     r1, #1
        bcc     LOCAL_LABEL(divby0)
+#if defined(USE_THUMB_1)
+       bne LOCAL_LABEL(num_neq_denom)
+       JMP(lr)
+LOCAL_LABEL(num_neq_denom):
+#else
        IT(eq)
        JMPc(lr, eq)
+#endif
        cmp     r0, r1
+#if defined(USE_THUMB_1)
+       bhs LOCAL_LABEL(num_ge_denom)
+       movs r0, #0
+       JMP(lr)
+LOCAL_LABEL(num_ge_denom):
+#else
        ITT(cc)
        movcc   r0, #0
        JMPc(lr, cc)
-       /*
-        * Implement division using binary long division algorithm.
-        *
-        * r0 is the numerator, r1 the denominator.
-        *
-        * The code before JMP computes the correct shift I, so that
-        * r0 and (r1 << I) have the highest bit set in the same position.
-        * At the time of JMP, ip := .Ldiv0block - 12 * I.
-        * This depends on the fixed instruction size of block.
-        * For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
-        *
-        * block(shift) implements the test-and-update-quotient core.
-        * It assumes (r0 << shift) can be computed without overflow and
-        * that (r0 << shift) < 2 * r1. The quotient is stored in r3.
-        */
-
-#  ifdef __ARM_FEATURE_CLZ
+#endif
+
+       // Implement division using binary long division algorithm.
+       //
+       // r0 is the numerator, r1 the denominator.
+       //
+       // The code before JMP computes the correct shift I, so that
+       // r0 and (r1 << I) have the highest bit set in the same position.
+       // At the time of JMP, ip := .Ldiv0block - 12 * I.
+       // This depends on the fixed instruction size of block.
+       // For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
+       //
+       // block(shift) implements the test-and-update-quotient core.
+       // It assumes (r0 << shift) can be computed without overflow and
+       // that (r0 << shift) < 2 * r1. The quotient is stored in r3.
+
+#  if defined(__ARM_FEATURE_CLZ)
        clz     ip, r0
        clz     r3, r1
-       /* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
+       // r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3.
        sub     r3, r3, ip
+#    if defined(USE_THUMB_2)
+       adr     ip, LOCAL_LABEL(div0block) + 1
+       sub     ip, ip, r3, lsl #1
+#    else
        adr     ip, LOCAL_LABEL(div0block)
+#    endif
        sub     ip, ip, r3, lsl #2
        sub     ip, ip, r3, lsl #3
        mov     r3, #0
        bx      ip
-#  else
+#  else // No CLZ Feature
+#    if defined(USE_THUMB_2)
+#    error THUMB mode requires CLZ or UDIV
+#    endif
+#    if defined(USE_THUMB_1)
+#      define BLOCK_SIZE 10
+#    else
+#      define BLOCK_SIZE 12
+#    endif
+
        mov     r2, r0
+#    if defined(USE_THUMB_1)
+       mov ip, r0
+       adr r0, LOCAL_LABEL(div0block)
+