Added: Postcodes to the Xeon Phi Boot device
authorReto Achermann <acreto@student.ethz.ch>
Sun, 27 Apr 2014 14:42:30 +0000 (16:42 +0200)
committerStefan Kaestle <stefan.kaestle@inf.ethz.ch>
Wed, 20 Aug 2014 13:59:05 +0000 (15:59 +0200)
devices/xeon_phi/xeon_phi_boot.dev
usr/drivers/xeon_phi/boot.c
usr/drivers/xeon_phi/dma.c
usr/drivers/xeon_phi/dma.h
usr/drivers/xeon_phi/xeon_phi.c
usr/drivers/xeon_phi/xeon_phi.h

index 2008dd6..63f550f 100644 (file)
@@ -67,97 +67,107 @@ device xeon_phi_boot lsbfirst ( addr sbox_base, addr dbox_base ) "Intel Xeon Phi
        reset  1 "Perform device rest";
        _     31; 
     };
+    
     /*
-    constants postcodes "" {
-       postcode_invalid = 0x0 "Invalid Postcode";
-               postcode_lidt = 0x01 "LIDT";
-               postcode_sboxinit = 0x02 "SBOX initialization";
-               postcode_gddrtop = 0x03 "Set GDDR Top";
-               postcode_memtest = 0x04 "Begin memory test";
-               postcode_e820 = 0x05 "Program E820 table";
-               postcode_dbox = 0x06 "Initialize DBOX";
-               postcode_cache = 0x09 "Enable Cache";    
-               postcode_initap = 0x0b "Pass initialization params to APs";
-               postcode_code = 0x0c "Cache C code";
-               postcode_mp = 0x0d "Program MP table";
-               postcode_apwkup = 0x0f "Wake up APs";
-               postcode_apboot = 0x10 "Wait for APs to boot";
-               postcode_sig = 0x11 "Signal host to download OS";
-               postcode_ready = 0x12 "Wait for download READY";
-               postcode_boot = 0x13 "Signal to boot received";
-               postcode_pinfo = 0x15 "Report platform information";
-               postcode_ptable = 0x17 "Page table setup";
-               postcode_memtrain = 0x30 ""Begin memory training;
-               postcode_gddrtrain = 0x31 ""GDDR Training to query memory modules;
-               postcode_findgddrtrain = 0x32 "Find GDDR training parameters in flash";
-               postcode_mmiotrain = 0x33 "MMIO training";
-               postcode_rcomptrain = 0x34 "RCOMP training";
-               postcode_dcctrain = 0x35 "DCC disable training";
-               postcode_hcktrain = 0x36 "HCK training";
-               postcode_ucodetrain = 0x37 "UCode Training";
-               postcode_vendortrain = 0x38 "Vendor specific training";
-               postcode_addrtrain = 0x39 "GDDR address training";
-               postcode_gddrident = 0x3A "GDDR memory module identification";
-               postcode_wcktrain = 0x3B "GDDR WCK training";
-               postcode_cdrdtrain = 0x3C "GDDR read training with CDR enabled";
-               postcode_cdretrain = 0x3D "GDDR Read Training with CDR disabled";
-               postcode_wrtrain = 0x3E "GDDR Write Training";
-               postcode_fintrain = 0x3F "Finalize GDDR Training";
-               postcode_osauth = 0x40 "Begin Coprocessor OS authentification";
-               postcode_loading0 = 0x50 "Coprocessor OS Loading 0";
-               postcode_loading1 = 0x51 "Coprocessor OS Loading 1";
-               postcode_loading2 = 0x52 "Coprocessor OS Loading 2";
-               postcode_loading3 = 0x53 "Coprocessor OS Loading 3";
-               postcode_loading4 = 0x54 "Coprocessor OS Loading 4";
-               postcode_loading5 = 0x55 "Coprocessor OS Loading 5";
-               postcode_loading6 = 0x56 "Coprocessor OS Loading 6";
-               postcode_loading7 = 0x57 "Coprocessor OS Loading 7";
-               postcode_loading8 = 0x58 "Coprocessor OS Loading 8";
-               postcode_loading9 = 0x59 "Coprocessor OS Loading 9";
-               postcode_loadingb = 0x5A "Coprocessor OS Loading A";
-               postcode_loadinga = 0x5B "Coprocessor OS Loading B";
-               postcode_loadingc = 0x5C "Coprocessor OS Loading C";
-               postcode_loadingd = 0x5D "Coprocessor OS Loading D";
-               postcode_loadinge = 0x5E "Coprocessor OS Loading E";
-               postcode_loadingf = 0x5F "Coprocessor OS Loading F";
-               postcode_gp = 0x6P "Int 13 - General Protection Fault";
-               postcode_invaltss = 0x75 "Int 10 - Invalid TSS";
-               postcode_fpu = 0x87 "Int 16 - x87 FPU Error";
-               postcode_algin = 0xac "";
-               postcode_bp = 0x "";
-               postcode_bound = 0x "";
-               postcode_mc = 0x "";
-               postcode_seg = 0x "";
-               postcode_dbg = 0x "";
-               postcode_div = 0x "";
-               postcode_df = 0x "";
-               postcode_memf = 0x "";
-               postcode_ = 0x "";
-               postcode_ = 0x "";
-               postcode_ = 0x "";
-               postcode_ = 0x "";
-               
-               postcode_ = 0x "";
-
-
-
-
-
-
-
-
-       postcode_invalid         = 0; 
-               postcode_reset_failed_f2 = 12870;
-               postcode_reset_failed_f4 = 13382;
-       postcode_fatal               = 0xffffffff;
+     * Note: The post codes are represented as a two byte ASCII values  
+     */
+    constants postcodes width(16) "The Xeon Phi Post codes" {
+               postcode_lidt           = 0x3031 "01 LIDT";
+               postcode_sboxinit       = 0x3032 "02 SBOX initialization";
+               postcode_gddrtop        = 0x3033 "03 Set GDDR Top";
+               postcode_memtest        = 0x3034 "04 Begin memory test";
+               postcode_e820           = 0x3035 "05 Program E820 table";
+               postcode_dbox           = 0x3036 "06 Initialize DBOX";
+               postcode_cache          = 0x3039 "09 Enable Cache";    
+               postcode_initap         = 0x3062 "0b Pass initialization params to APs";
+               postcode_code           = 0x3063 "0c Cache C code";
+               postcode_mp             = 0x3045 "0E Program MP table";
+               postcode_apwkup         = 0x3046 "0F Wake up APs";
+               postcode_apboot         = 0x3130 "10 Wait for APs to boot";
+               postcode_sig            = 0x3131 "11 Signal host to download OS";
+               postcode_ready          = 0x3132 "12 Wait for download READY";
+               postcode_boot           = 0x3133 "13 Signal to boot received";
+               postcode_pinfo          = 0x3135 "15 Report platform information";
+               postcode_ptable         = 0x3137 "17 Page table setup";
+               postcode_memtrain       = 0x3330 "30 Begin memory training";
+               postcode_gddrtrain      = 0x3331 "31 GDDR Training to query memory modules";
+               postcode_findgddrtrain  = 0x3332 "32 Find GDDR training parameters in flash";
+               postcode_mmiotrain      = 0x3333 "33 MMIO training";
+               postcode_rcomptrain     = 0x3334 "34 RCOMP training";
+               postcode_dcctrain       = 0x3335 "35 DCC disable training";
+               postcode_hcktrain       = 0x3336 "36 HCK training";
+               postcode_ucodetrain     = 0x3337 "37 UCode Training";
+               postcode_vendortrain    = 0x3338 "38 Vendor specific training";
+               postcode_addrtrain      = 0x3339 "39 GDDR address training";
+               postcode_gddrident      = 0x3341 "3A GDDR memory module identification";
+               postcode_wcktrain       = 0x3362 "3b GDDR WCK training";
+               postcode_cdrdtrain      = 0x3343 "3C GDDR read training with CDR enabled";
+               postcode_cdretrain      = 0x3364 "3d GDDR Read Training with CDR disabled";
+               postcode_wrtrain        = 0x3345 "3E GDDR Write Training";
+               postcode_fintrain       = 0x3346 "3F Finalize GDDR Training";
+               postcode_osauth         = 0x3430 "40 Begin Coprocessor OS authentification";
+               postcode_loading0       = 0x3530 "50 Coprocessor OS Loading 0";
+               postcode_loading1       = 0x3531 "51 Coprocessor OS Loading 1";
+               postcode_loading2       = 0x3532 "52 Coprocessor OS Loading 2";
+               postcode_loading3       = 0x3533 "53 Coprocessor OS Loading 3";
+               postcode_loading4       = 0x3534 "54 Coprocessor OS Loading 4";
+               postcode_loading5       = 0x3535 "55 Coprocessor OS Loading 5";
+               postcode_loading6       = 0x3536 "56 Coprocessor OS Loading 6";
+               postcode_loading7       = 0x3537 "57 Coprocessor OS Loading 7";
+               postcode_loading8       = 0x3538 "58 Coprocessor OS Loading 8";
+               postcode_loading9       = 0x3539 "59 Coprocessor OS Loading 9";
+               postcode_loadingb       = 0x3541 "5A Coprocessor OS Loading A";
+               postcode_loadinga       = 0x3542 "5B Coprocessor OS Loading B";
+               postcode_loadingc       = 0x3543 "5C Coprocessor OS Loading C";
+               postcode_loadingd       = 0x3544 "5D Coprocessor OS Loading D";
+               postcode_loadinge       = 0x3545 "5E Coprocessor OS Loading E";
+               postcode_loadingf       = 0x3546 "5F Coprocessor OS Loading F";
+               postcode_gp             = 0x3650 "6P Int 13 - General Protection Fault";
+               postcode_tss            = 0x3735 "75 Int 10 - Invalid TSS";
+               postcode_fpu            = 0x3837 "87 Int 16 - x87 FPU Error";
+               postcode_algin          = 0x4143 "AC INT 17 - Alignment Check";
+               postcode_bp             = 0x6250 "bP INT 3 - Break Point";
+               postcode_bound          = 0x6272 "br INT 5 - BOUND Range Exceeded";
+               postcode_mc             = 0x4343 "CC INT 18 - Machine Check";
+               postcode_seg            = 0x636F "co INT 9 - Coprocessor Segmenet Overrun";
+               postcode_dbg            = 0x6462 "db INT 1 - Debug";
+               postcode_div            = 0x6445 "dE INT 0 - Divide Error";
+               postcode_df             = 0x6446 "dF INT 8 - Double Fault";
+               postcode_memf           = 0x4545 "EE Memory Test Failed";
+               postcode_pnf            = 0x4630 "F0 GDDR Parameters not found";
+               postcode_pllf           = 0x4631 "F1 GBOX PLL lock failure";
+               postcode_memtf          = 0x4632 "F2 GDDR failed memory training";
+               postcode_memqf          = 0x4633 "F3 GDDR memory module query failed";
+               postcode_mempf          = 0x4634 "F4 Memory preservation failure";
+           postcode_sf             = 0x4635 "F5 INT 12 - Stack Fault";
+           postcode_done           = 0x4646 "FF - Bootstrap finished execution";
+           postcode_ld             = 0x4C64 "Ld - Locking down hardware access";
+           postcode_authf          = 0x6E41 "nA - OS Image failed Authentification";
+           postcode_dna            = 0x6E64 "nd INT 7 - Device not Available";
+           postcode_nmi            = 0x6E6F "no INT 2 - Non-maskable Interrupt";
+           postcode_snp            = 0x6E50 "nP INT 11 - Segment Not Present";
+           postcode_of             = 0x6F46 "oF INT 4 - Overflow";
+           postcode_pf             = 0x5046 "PF INT 14 - Pagefault";
+           postcode_rs             = 0x7235 "r5 INT 15 - Reserved";
+           postcode_iop            = 0x7564 "ud INT 6 - Invalid OP code";
+    };
+    
+    constants postcodes_special width(32) "The Xeon Phi Post codes" {
+        postcode_invalid = 0x0;
+        postcode_fatal   = 0xffffffff;
     };
-    */
+    
     
     register postcode rw addr(dbox_base, 0x242c) {
-       code0  8;
-       code1  8;
+       code  16 type(postcodes);
        _     16;
     };
+    
+    register postcode_raw rw also addr(dbox_base, 0x242c) {
+        code0  8;
+        code1  8;
+        _     16;
+    };
 
 };
 
index 5d4aed6..a7072d7 100644 (file)
@@ -27,6 +27,21 @@ struct bootinfo *bi = NULL;
 
 #include "xeon_phi.h"
 
+/*
+ * TODO: Verify these values if they are really needed
+ */
+#define MEMORY_RESERVE_PERCENT 50
+#define UOS_RESERVE_SIZE_MIN    ((128) * 1024 * 1024)
+#define UOS_RESERVE_SIZE_MAX    (((4) * 1024 * 1024 * 1024ULL) - ((4) * 1024))
+
+/*
+ * Helper macros
+ */
+#define MAX(a, b)   ( ((a) > (b)) ? (a) : (b) )
+#define MIN(a, b)   ( ((a) < (b)) ? (a) : (b) )
+#define ALIGN(x) ((x + BASE_PAGE_SIZE-1) & ~(BASE_PAGE_SIZE-1))
+
+
 static xeon_phi_boot_t boot_registers;
 static xeon_phi_apic_t apic_registers;
 
@@ -51,11 +66,15 @@ static inline lvaddr_t get_load_offset(struct xeon_phi *phi)
  * \param xloader_img   name of the bootloader image
  * \param ret_imgsize   returned image size
  * \param ret_cmdoffset returned offset to load the next piece onto the card
+ *
+ * Note: it is important that the bootloader just uses statically allocated
+ *       memory and does not exceed its image size with additional memory.
+ *       Otherwise the CMD line or the multiboot image will be overwritten.
  */
-static errval_t load_os(struct xeon_phi *phi,
-                        char *xloader_img,
-                        uint32_t *ret_imgsize,
-                        lvaddr_t *ret_cmdoffset)
+static errval_t load_bootloader(struct xeon_phi *phi,
+                                char *xloader_img,
+                                uint32_t *ret_imgsize,
+                                lvaddr_t *ret_cmdoffset)
 {
     errval_t err;
     /*
@@ -262,11 +281,14 @@ errval_t xeon_phi_boot(struct xeon_phi *phi,
     xeon_phi_apic_initialize(&apic_registers, XEON_PHI_MMIO_TO_SBOX(phi));
 
     // load the coprocessor OS
-    err = load_os(phi, xloader_img, &osimg_size, &offset);
+    err = load_bootloader(phi, xloader_img, &osimg_size, &offset);
     if (err_is_fail(err)) {
         USER_PANIC_ERR(err, "Could not load bootloader image");
     }
 
+    // round to next page
+    offset = ALIGN(offset);
+
     // load cmdline
     err = load_cmdline(phi, offset, &size);
     if (err_is_fail(err)) {
@@ -274,7 +296,7 @@ errval_t xeon_phi_boot(struct xeon_phi *phi,
     }
 
     // round to next page
-    offset += size + BASE_PAGE_SIZE - (size & (BASE_PAGE_SIZE - 1));
+    offset = ALIGN(offset);
 
     // load multiboot image
     err = load_multiboot_image(phi, multiboot_img, offset, &size);
index eec6807..b7ddc4e 100644 (file)
 #include <barrelfish/barrelfish.h>
 
 #include "xeon_phi.h"
+#include "dma.h"
+
+/**
+ * \brief Initializes the DMA structure for the Xeon Phi
+ *
+ * \param phi the xeon phi DMA structure
+ *
+ * \return SYS_ERR_OK on success,
+ */
+errval_t dma_init(struct xeon_phi *phi)
+{
+
+    return SYS_ERR_OK;
+}
 
index 4461815..6e2030d 100644 (file)
  * If you do not find this file, copies can be found by writing to:
  * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
  */
-#ifndef XEON_PHI_SMPT_H
-#define XEON_PHI_SMPT_H
+#ifndef XEON_PHI_DMA_H
+#define XEON_PHI_DMA_H
 
-#include <dev/xeon_phi/xeon_phi_smpt_dev.h>
+//#include <dev/xeon_phi/xeon_phi_dma_dev.h>
 
 
 struct dma_info {
@@ -30,8 +30,16 @@ errval_t dma_request_alloc(void);
 
 errval_t dma_request_exec(void);
 
-errval_t dma_request_free(void)
+errval_t dma_request_free(void);
 
+
+/**
+ * \brief Initializes the DMA structure for the Xeon Phi
+ *
+ * \param phi the xeon phi DMA structure
+ *
+ * \return SYS_ERR_OK on success,
+ */
 errval_t dma_init(struct xeon_phi *phi);
 
-#endif /* XEON_PHI_SMPT_H */
+#endif /* XEON_PHI_DMA_H */
index f64e1e4..982d2ca 100644 (file)
@@ -22,6 +22,7 @@
 #include "xeon_phi.h"
 #include "interrupts.h"
 #include "sleep.h"
+#include "dma.h"
 
 static uint32_t initialized = 0;
 
@@ -171,6 +172,8 @@ errval_t xeon_phi_init(struct xeon_phi *phi)
 
     device_init(phi);
 
+    dma_init(phi);
+
     return SYS_ERR_OK;
 }
 
@@ -205,19 +208,27 @@ errval_t xeon_phi_reset(struct xeon_phi *phi)
     milli_sleep(1000);
 
     xeon_phi_boot_postcode_t postcode;
+    xeon_phi_boot_postcodes_t pc;
     for (uint32_t time = 0; time < XEON_PHI_RESET_TIME; ++time) {
         postcode = xeon_phi_boot_postcode_rd(&boot_registers);
-
-        debug_printf("Resetting (Post Code %c%c)\n",
-                     xeon_phi_boot_postcode_code0_extract(postcode),
-                     xeon_phi_boot_postcode_code1_extract(postcode));
-
-
+        pc = xeon_phi_boot_postcode_extract(postcode);
+        debug_printf("Resetting; %s\n", xeon_phi_boot_postcodes_describe(pc));
+        XBOOT_DEBUG("Resetting (Post Code %c%c)\n",
+                     xeon_phi_boot_postcode_raw_code0_extract(postcode),
+                     xeon_phi_boot_postcode_raw_code1_extract(postcode));
+
+        if (postcode == xeon_phi_boot_postcode_invalid
+                || postcode == xeon_phi_boot_postcode_fatal
+                || pc == xeon_phi_boot_postcode_memtf
+                || pc == xeon_phi_boot_postcode_mempf) {
+            break;
+        }
 
         if (xeon_phi_boot_download_status_rdf(&boot_registers)) {
             phi->state = XEON_PHI_STATE_READY;
             debug_printf("Reset successful\n");
             /*
+             * XXX; Maybe we should re-enable the IRQ if they were enabled beforehand
              * if (mic_ctx->msie)
                     mic_enable_msi_interrupts(mic_ctx);
                 mic_enable_interrupts(mic_ctx);
@@ -231,44 +242,14 @@ errval_t xeon_phi_reset(struct xeon_phi *phi)
     }
 
     if (phi->state != XEON_PHI_STATE_READY) {
-        debug_printf("Reset Failed (Post Code %c%c)\n",
-                             xeon_phi_boot_postcode_code0_extract(postcode),
-                             xeon_phi_boot_postcode_code1_extract(postcode));
-    }
-#if 0
-
-
-
-        void
-        reset_timer(unsigned long arg)
-        {
-            if (mic_ctx->reset_count == RESET_FAIL_TIME ||
-                !postcode || 0xffffffff == postcode || mic_ctx->state == MIC_RESETFAIL) {
-                mic_ctx->reset_count = 0;
-                mic_setstate(mic_ctx, MIC_RESETFAIL);
-                wake_up(&mic_ctx->resetwq);
-                printk("MIC %d RESETFAIL postcode %c%c %d\n", mic_ctx->bi_id,
-                    postcode & 0xff, (postcode >> 8) & 0xff, postcode);
-                return;
-            }
-
-            /* check for F2 or F4 error codes from bootstrap */
-            if ((postcode == RESET_FAILED_F2) || (postcode == RESET_FAILED_F4)) {
-                if (mic_ctx->resetworkq) {
-                    queue_work(mic_ctx->resetworkq, &mic_ctx->resetwork);
-                } else {
-                    mic_ctx->reset_count = 0;
-                    mic_setstate(mic_ctx, MIC_RESETFAIL);
-                    wake_up(&mic_ctx->resetwq);
-                    return;
-                }
-            }
-
-
+        debug_printf("Reset Failed; %s\n", xeon_phi_boot_postcodes_describe(pc));
+        XBOOT_DEBUG("Reset Failed (Post Code %c%c)\n",
+                             xeon_phi_boot_postcode_raw_code0_extract(postcode),
+                             xeon_phi_boot_postcode_raw_code1_extract(postcode));
 
+        return 1;
+    }
 
-        }
-#endif
     return SYS_ERR_OK;
 }
 
index 190945e..35f7eda 100644 (file)
 #ifndef XEON_PHI_H_
 #define XEON_PHI_H_
 
+/*
+ * Common setting values
+ */
 
+/// the name of the Xeon Phi bootloader image
 #define XEON_PHI_BOOTLOADER "xeon_phi_bootloader"
+
+/// the name of the Xeon Phi multiboot image containint the modules
 #define XEON_PHI_MULTIBOOT "xeon_phi_multiboot"
 
+/// if we use MSIX interrupts or legacy interrupts
 #define XEON_PHI_MSIX_ENABLED 1
 
+/// the number of MSIX interrupts we use
+#define XEON_PHI_MSIX_NUM     1
+
+/*
+ * Debug output switches
+ */
+#define XDEBUG_ENABLED  1
+#define XDEBUG_BOOT     1
+#define XDEBUG_DMA      1
+#define XDEBUG_INT      1
+#define XDEBUG_SMPT     1
+#define XDEBUG_SERVICE  1
+
+
+
+/*
+ * This defines are used to reference the MMIO registers on the host side.
+ *
+ * The Mackerel Specifications use the SBOX or DBOX baseaddress as their
+ * register base. however the SBOX or DBOX have a certain offset into the
+ * MMIO range.
+ */
 #define HOST_DBOX_OFFSET      0x00000000
 #define HOST_SBOX_OFFSET      0x00010000
 
 #define XEON_PHI_MMIO_TO_DBOX(phi) \
     ((mackerel_addr_t)((lvaddr_t)(phi->mmio.vbase)+HOST_DBOX_OFFSET))
 
-#define XEON_PHI_NUM_CARDS 8
 
-#define XBOOT_DEBUG(x...) debug_printf(" BOOT | " x)
-//#define XBOOT_DEBUG(x...)
+/*
+ * --------------------------------------------------------------------------
+ * Debug output generation
+ */
+#if XDEBUG_ENABLED
+#define XDEBUG_PRINT(x...) debug_printf(x)
+#else
+#define XDEBUG_PRINT(x... )
+#endif
+#if XDEBUG_BOOT
+#define XBOOT_DEBUG(x...) XDEBUG_PRINT(" BOOT | " x)
+#else
+#define XBOOT_DEBUG(x...)
+#endif
+#if XDEBUG_DMA
+#define XDMA_DEBUG(x...) XDEBUG_PRINT(" DMA | " x)
+#else
+#define XDMA_DEBUG(x...)
+#endif
+#if XDEBUG_INT
+#define XINT_DEBUG(x...) XDEBUG_PRINT(" INT | " x)
+#else
+#define XINT_DEBUG(x...)
+#endif
+#if XDEBUG_SMPT
+#define XSMPT_DEBUG(x...) XDEBUG_PRINT(" SMPT | " x)
+#else
+#define XSMPT_DEBUG(x...)
+#endif
+#if XDEBUG_SERVICE
+#define XSERVICE_DEBUG(x...) XDEBUG_PRINT(" SVC | " x)
+#else
+#define XSERVICE_DEBUG(x...)
+#endif
+
 
-#define MAX(a, b)   ( ((a) > (b)) ? (a) : (b) )
-#define MIN(a, b)   ( ((a) < (b)) ? (a) : (b) )
+/*
+ * --------------------------------------------------------------------------
+ * Xeon Phi Management structure
+ */
 
+/// represents the state of the Xeon Phi
 typedef enum xeon_phi_state {
-    XEON_PHI_STATE_NULL,
-    XEON_PHI_STATE_PCI_OK,
-    XEON_PHI_STATE_RESET,
-    XEON_PHI_STATE_READY,
-    XEON_PHI_STATE_BOOTING,
-    XEON_PHI_STATE_ONLINE
+    XEON_PHI_STATE_NULL,    ///< The card has not yet been initialized
+    XEON_PHI_STATE_PCI_OK,  ///< The card has been registered with PCI
+    XEON_PHI_STATE_RESET,   ///< The card has been reset
+    XEON_PHI_STATE_READY,   ///< The card is ready to load the os
+    XEON_PHI_STATE_BOOTING, ///< The card is in the booting state
+    XEON_PHI_STATE_ONLINE   ///< the card has booted and is online
 } xeon_phi_state_t;
 
-/*
- * TODO: Verify these values if they are really needed
- */
-#define MEMORY_RESERVE_PERCENT 50
-#define UOS_RESERVE_SIZE_MIN    ((128) * 1024 * 1024)
-#define UOS_RESERVE_SIZE_MAX    (((4) * 1024 * 1024 * 1024ULL) - ((4) * 1024))
 
+/// represents the memory ranges occupied by the Xeon Phi card
 struct mbar {
     lvaddr_t vbase;
     lpaddr_t pbase;
     size_t   length;
+    /*
+     * XXX: may it be useful to store the cap here aswell ?
+     */
 };
 
 struct xeon_phi
 {
     xeon_phi_state_t state;
-    struct mbar mmio;
-    struct mbar apt;
+    struct mbar mmio;       ///< pointer to the MMIO address range
+    struct mbar apt;        ///< pointer to the aperture address range
 
-    uint8_t pci_init;
     uint8_t id;             ///< card id for identifying the card
 
+
     uint32_t apicid;        ///< APIC id used for sending the boot interrupt
 
     char *cmdline;          ///< pointer to the bootloader cmdline
 
-    struct smpt_info       *smpt;
-
-
-    struct irq_info         *irq;
+    struct smpt_info  *smpt; ///< pointer to the SMPT information struct
+    struct irq_info   *irq;  ///< pointer to the IRQ information struct
+    struct dma_infi   *dma;  ///< pointer to the DMA information struct
 };
 
 /**