* counter each time that it completes (or skips) a descriptor.This
* register is RW if CHANCNT register is 1 otherwise this register is RO.
*/
- register dcount addr(chan_base, 0x06) "DMA Descriptor Count Register"
+ register dmacount addr(chan_base, 0x06) "DMA Descriptor Count Register"
type(uint16);
constants trans_state "DMA Transfer States" {
- trans_state_idle = 0x1 "Idle, All DMA transfers done";
- trans_state_susp = 0x2 "Suspended";
- trans_state_halt = 0x3 "Halted, operation aborted (error)";
- trans_state_armed = 0x4 "Armed State";
+ trans_state_active = 0x0 "The transfer is active";
+ trans_state_idle = 0x1 "Idle, All DMA transfers done";
+ trans_state_susp = 0x2 "Suspended";
+ trans_state_halt = 0x3 "Halted, operation aborted (error)";
+ trans_state_armed = 0x4 "Armed State";
};
/*
errors ioat IOAT_ERR_ {
failure PCI_ADDRESS "The PCI address of the device is not as expected",
failure DEVICE_UNSUPPORTED "Device ID not supported / wrong configuration",
-
+ failure ARG_INVALID "Supplied argument was not valid",
+ failure CHAN_ERROR "Hardware channel error",
+ failure NO_DESCRIPTORS "There are too less descriptors available",
+ failure NO_REQUESTS "There are no request descriptors left",
+ failure CHAN_BUSY "The channel is busy and cannot accept more",
+ failure CHAN_IDLE "There were no finished requests on the channel",
+ failure REQUEST_UNFINISHED "The request is still in operation",
};