GICv3: Generate softirq

Currently only does so for cores in the same affinity domain.

Signed-off-by: Lukas Humbel <lukas.humbel@inf.ethz.ch>

diff --git a/kernel/arch/armv8/gic_v3.c b/kernel/arch/armv8/gic_v3.c
index e6c3161..86f5158 100644 (file)
--- a/kernel/arch/armv8/gic_v3.c
+++ b/kernel/arch/armv8/gic_v3.c
@@ -55,15 +55,19 @@ void gicv3_ack_irq(uint32_t irq)
 }
 
 /*
- * Raise an SGI on a core
+ * Raise an SGI on a core. 
  */
-void gicv3_raise_softirq(uint8_t cpumask, uint8_t irq)
+void gicv3_raise_softirq(coreid_t cpuid, uint8_t irq)
 {
     assert(irq <= 15);
-    gic_v3_GICD_SGIR_t reg = 0;
-    reg = gic_v3_GICD_SGIR_INTID_insert(reg, irq);
-    reg = gic_v3_GICD_SGIR_CPUTargetList_insert(reg, cpumask);
-    gic_v3_GICD_SGIR_wr(&gic_v3_dev, reg);
+    armv8_ICC_SGI1R_EL1_t reg = 0;
+    reg = armv8_ICC_SGI1R_EL1_intid_insert(reg, 1);
+    // TODO: make that work for cpuids > 15
+    reg = armv8_ICC_SGI1R_EL1_target_insert(reg, 1<<cpuid);
+    reg = armv8_ICC_SGI1R_EL1_aff3_insert(reg, 0);
+    reg = armv8_ICC_SGI1R_EL1_aff2_insert(reg, 0);
+    reg = armv8_ICC_SGI1R_EL1_aff1_insert(reg, 0);
+    armv8_ICC_SGI1R_EL1_wr(NULL, reg);
 }
 
 /*

diff --git a/kernel/include/arch/armv8/gic_v3.h b/kernel/include/arch/armv8/gic_v3.h
index ae4afee..383149e 100644 (file)
--- a/kernel/include/arch/armv8/gic_v3.h
+++ b/kernel/include/arch/armv8/gic_v3.h
@@ -13,6 +13,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 #include <stddef.h>
+#include <barrelfish_kpi/types.h>
 
 /*
  * generic interrupt controller functionality
@@ -25,6 +26,6 @@ uint32_t gicv3_get_active_irq(void);
 
 void gicv3_ack_irq(uint32_t irq);
 
-void gicv3_raise_softirq(uint8_t cpumask, uint8_t irq);
+void gicv3_raise_softirq(coreid_t cpuid, uint8_t irq);
 
 #endif // __GIC_V3_H__