Some bugfixes in the register definitons of the Xeon Phi.
authorReto Achermann <acreto@student.ethz.ch>
Sat, 3 May 2014 21:25:57 +0000 (23:25 +0200)
committerStefan Kaestle <stefan.kaestle@inf.ethz.ch>
Wed, 20 Aug 2014 15:05:01 +0000 (17:05 +0200)
devices/xeon_phi/xeon_phi_apic.dev
devices/xeon_phi/xeon_phi_boot.dev
usr/drivers/xeon_phi/boot.c
usr/drivers/xeon_phi/serial.c
usr/drivers/xeon_phi/xeon_phi.c
usr/drivers/xeon_phi/xeon_phi.h
usr/pci/pci.c

index 5b9c188..5feec6f 100644 (file)
@@ -116,12 +116,12 @@ device xeon_phi_apic lsbfirst ( addr base ) "Intel Xeon Phi APIC register" {
      * Register Access: CRU
      * Number: 8
      */
-    regarray icr_lo rw addr(base, 0x9D0) [8; 0x8] "APIC Interrupt Command Register 0 to 7" { 
+    regarray icr_lo rw addr(base, 0xA9D0) [8; 0x8] "APIC Interrupt Command Register 0 to 7" { 
         vector      8 "Vector";
         dlv_mode    3 type(vdm) "Delivery mode";
         dst_mode    1 type(dst_mode) "Destination mode";
         dlv_stat    1 ro "Delivery status";
-        _           1;
+        boot_notify 1 "Boot notify bit";
         level       1 type(int_level) "Level";
         trig_mode   1 type(trigm) "Trigger mode";
         _           2;
@@ -129,7 +129,7 @@ device xeon_phi_apic lsbfirst ( addr base ) "Intel Xeon Phi APIC register" {
         _           12;
     };            
     
-    regarray icr_hi rw addr(base, 0x9D4) [8; 0x8]  "APIC Interrupt Command Register 0 to 7" { 
+    regarray icr_hi rw addr(base, 0xA9D4) [8; 0x8]  "APIC Interrupt Command Register 0 to 7" { 
         dest        32 "Destination field";
     }; 
 
index c89c337..837bd24 100644 (file)
@@ -72,84 +72,84 @@ device xeon_phi_boot lsbfirst ( addr sbox_base, addr dbox_base ) "Intel Xeon Phi
      * Note: The post codes are represented as a two byte ASCII values  
      */
     constants postcodes width(16) "The Xeon Phi Post codes" {
-        postcode_lidt           = 0x3031 "01 LIDT";
-        postcode_sboxinit       = 0x3032 "02 SBOX initialization";
-        postcode_gddrtop        = 0x3033 "03 Set GDDR Top";
-        postcode_memtest        = 0x3034 "04 Begin memory test";
-        postcode_e820           = 0x3035 "05 Program E820 table";
-        postcode_dbox           = 0x3036 "06 Initialize DBOX";
-        postcode_cache          = 0x3039 "09 Enable Cache";    
-        postcode_initap         = 0x3062 "0b Pass initialization params to APs";
-        postcode_code           = 0x3063 "0c Cache C code";
-        postcode_mp             = 0x3045 "0E Program MP table";
-        postcode_apwkup         = 0x3046 "0F Wake up APs";
-        postcode_apboot         = 0x3130 "10 Wait for APs to boot";
+        postcode_lidt           = 0x3130 "01 LIDT";
+        postcode_sboxinit       = 0x3230 "02 SBOX initialization";
+        postcode_gddrtop        = 0x3330 "03 Set GDDR Top";
+        postcode_memtest        = 0x3430 "04 Begin memory test";
+        postcode_e820           = 0x3530 "05 Program E820 table";
+        postcode_dbox           = 0x3630 "06 Initialize DBOX";
+        postcode_cache          = 0x3930 "09 Enable Cache";    
+        postcode_initap         = 0x6230 "0b Pass initialization params to APs";
+        postcode_code           = 0x6330 "0c Cache C code";
+        postcode_mp             = 0x4530 "0E Program MP table";
+        postcode_apwkup         = 0x4630 "0F Wake up APs";
+        postcode_apboot         = 0x3031 "10 Wait for APs to boot";
         postcode_sig            = 0x3131 "11 Signal host to download OS";
-        postcode_ready          = 0x3132 "12 Wait for download READY";
-        postcode_boot           = 0x3133 "13 Signal to boot received";
-        postcode_pinfo          = 0x3135 "15 Report platform information";
-        postcode_ptable         = 0x3137 "17 Page table setup";
-        postcode_memtrain       = 0x3330 "30 Begin memory training";
-        postcode_gddrtrain      = 0x3331 "31 GDDR Training to query memory modules";
-        postcode_findgddrtrain  = 0x3332 "32 Find GDDR training parameters in flash";
+        postcode_ready          = 0x3231 "12 Wait for download READY";
+        postcode_boot           = 0x3331 "13 Signal to boot received";
+        postcode_pinfo          = 0x3531 "15 Report platform information";
+        postcode_ptable         = 0x3731 "17 Page table setup";
+        postcode_memtrain       = 0x3033 "30 Begin memory training";
+        postcode_gddrtrain      = 0x3133 "31 GDDR Training to query memory modules";
+        postcode_findgddrtrain  = 0x3233 "32 Find GDDR training parameters in flash";
         postcode_mmiotrain      = 0x3333 "33 MMIO training";
-        postcode_rcomptrain     = 0x3334 "34 RCOMP training";
-        postcode_dcctrain       = 0x3335 "35 DCC disable training";
-        postcode_hcktrain       = 0x3336 "36 HCK training";
-        postcode_ucodetrain     = 0x3337 "37 UCode Training";
-        postcode_vendortrain    = 0x3338 "38 Vendor specific training";
-        postcode_addrtrain      = 0x3339 "39 GDDR address training";
-        postcode_gddrident      = 0x3341 "3A GDDR memory module identification";
-        postcode_wcktrain       = 0x3362 "3b GDDR WCK training";
-        postcode_cdrdtrain      = 0x3343 "3C GDDR read training with CDR enabled";
-        postcode_cdretrain      = 0x3364 "3d GDDR Read Training with CDR disabled";
-        postcode_wrtrain        = 0x3345 "3E GDDR Write Training";
-        postcode_fintrain       = 0x3346 "3F Finalize GDDR Training";
-        postcode_osauth         = 0x3430 "40 Begin Coprocessor OS authentification";
-        postcode_loading0       = 0x3530 "50 Coprocessor OS Loading 0";
-        postcode_loading1       = 0x3531 "51 Coprocessor OS Loading 1";
-        postcode_loading2       = 0x3532 "52 Coprocessor OS Loading 2";
-        postcode_loading3       = 0x3533 "53 Coprocessor OS Loading 3";
-        postcode_loading4       = 0x3534 "54 Coprocessor OS Loading 4";
+        postcode_rcomptrain     = 0x3433 "34 RCOMP training";
+        postcode_dcctrain       = 0x3533 "35 DCC disable training";
+        postcode_hcktrain       = 0x3633 "36 HCK training";
+        postcode_ucodetrain     = 0x3733 "37 UCode Training";
+        postcode_vendortrain    = 0x3833 "38 Vendor specific training";
+        postcode_addrtrain      = 0x3933 "39 GDDR address training";
+        postcode_gddrident      = 0x4133 "3A GDDR memory module identification";
+        postcode_wcktrain       = 0x6233 "3b GDDR WCK training";
+        postcode_cdrdtrain      = 0x4333 "3C GDDR read training with CDR enabled";
+        postcode_cdretrain      = 0x6433 "3d GDDR Read Training with CDR disabled";
+        postcode_wrtrain        = 0x4533 "3E GDDR Write Training";
+        postcode_fintrain       = 0x4633 "3F Finalize GDDR Training";
+        postcode_osauth         = 0x3034 "40 Begin Coprocessor OS authentification";
+        postcode_loading0       = 0x3035 "50 Coprocessor OS Loading 0";
+        postcode_loading1       = 0x3135 "51 Coprocessor OS Loading 1";
+        postcode_loading2       = 0x3235 "52 Coprocessor OS Loading 2";
+        postcode_loading3       = 0x3335 "53 Coprocessor OS Loading 3";
+        postcode_loading4       = 0x3435 "54 Coprocessor OS Loading 4";
         postcode_loading5       = 0x3535 "55 Coprocessor OS Loading 5";
-        postcode_loading6       = 0x3536 "56 Coprocessor OS Loading 6";
-        postcode_loading7       = 0x3537 "57 Coprocessor OS Loading 7";
-        postcode_loading8       = 0x3538 "58 Coprocessor OS Loading 8";
-        postcode_loading9       = 0x3539 "59 Coprocessor OS Loading 9";
-        postcode_loadingb       = 0x3541 "5A Coprocessor OS Loading A";
-        postcode_loadinga       = 0x3542 "5B Coprocessor OS Loading B";
-        postcode_loadingc       = 0x3543 "5C Coprocessor OS Loading C";
-        postcode_loadingd       = 0x3544 "5D Coprocessor OS Loading D";
-        postcode_loadinge       = 0x3545 "5E Coprocessor OS Loading E";
-        postcode_loadingf       = 0x3546 "5F Coprocessor OS Loading F";
-        postcode_gp             = 0x3650 "6P Int 13 - General Protection Fault";
-        postcode_tss            = 0x3735 "75 Int 10 - Invalid TSS";
-        postcode_fpu            = 0x3837 "87 Int 16 - x87 FPU Error";
-        postcode_algin          = 0x4143 "AC INT 17 - Alignment Check";
-        postcode_bp             = 0x6250 "bP INT 3 - Break Point";
-        postcode_bound          = 0x6272 "br INT 5 - BOUND Range Exceeded";
+        postcode_loading6       = 0x3635 "56 Coprocessor OS Loading 6";
+        postcode_loading7       = 0x3735 "57 Coprocessor OS Loading 7";
+        postcode_loading8       = 0x3835 "58 Coprocessor OS Loading 8";
+        postcode_loading9       = 0x3935 "59 Coprocessor OS Loading 9";
+        postcode_loadingb       = 0x4135 "5A Coprocessor OS Loading A";
+        postcode_loadinga       = 0x4235 "5B Coprocessor OS Loading B";
+        postcode_loadingc       = 0x4335 "5C Coprocessor OS Loading C";
+        postcode_loadingd       = 0x4435 "5D Coprocessor OS Loading D";
+        postcode_loadinge       = 0x4535 "5E Coprocessor OS Loading E";
+        postcode_loadingf       = 0x4635 "5F Coprocessor OS Loading F";
+        postcode_gp             = 0x5036 "6P Int 13 - General Protection Fault";
+        postcode_tss            = 0x3537 "75 Int 10 - Invalid TSS";
+        postcode_fpu            = 0x3738 "87 Int 16 - x87 FPU Error";
+        postcode_algin          = 0x4341 "AC INT 17 - Alignment Check";
+        postcode_bp             = 0x5062 "bP INT 3 - Break Point";
+        postcode_bound          = 0x7262 "br INT 5 - BOUND Range Exceeded";
         postcode_mc             = 0x4343 "CC INT 18 - Machine Check";
-        postcode_seg            = 0x636F "co INT 9 - Coprocessor Segmenet Overrun";
-        postcode_dbg            = 0x6462 "db INT 1 - Debug";
-        postcode_div            = 0x6445 "dE INT 0 - Divide Error";
-        postcode_df             = 0x6446 "dF INT 8 - Double Fault";
+        postcode_seg            = 0x6F63 "co INT 9 - Coprocessor Segmenet Overrun";
+        postcode_dbg            = 0x6264 "db INT 1 - Debug";
+        postcode_div            = 0x4564 "dE INT 0 - Divide Error";
+        postcode_df             = 0x4664 "dF INT 8 - Double Fault";
         postcode_memf           = 0x4545 "EE Memory Test Failed";
-        postcode_pnf            = 0x4630 "F0 GDDR Parameters not found";
-        postcode_pllf           = 0x4631 "F1 GBOX PLL lock failure";
-        postcode_memtf          = 0x4632 "F2 GDDR failed memory training";
-        postcode_memqf          = 0x4633 "F3 GDDR memory module query failed";
-        postcode_mempf          = 0x4634 "F4 Memory preservation failure";
-        postcode_sf             = 0x4635 "F5 INT 12 - Stack Fault";
+        postcode_pnf            = 0x3046 "F0 GDDR Parameters not found";
+        postcode_pllf           = 0x3146 "F1 GBOX PLL lock failure";
+        postcode_memtf          = 0x3246 "F2 GDDR failed memory training";
+        postcode_memqf          = 0x3346 "F3 GDDR memory module query failed";
+        postcode_mempf          = 0x3446 "F4 Memory preservation failure";
+        postcode_sf             = 0x3546 "F5 INT 12 - Stack Fault";
         postcode_done           = 0x4646 "FF - Bootstrap finished execution";
-        postcode_ld             = 0x4C64 "Ld - Locking down hardware access";
-        postcode_authf          = 0x6E41 "nA - OS Image failed Authentification";
-        postcode_dna            = 0x6E64 "nd INT 7 - Device not Available";
-        postcode_nmi            = 0x6E6F "no INT 2 - Non-maskable Interrupt";
-        postcode_snp            = 0x6E50 "nP INT 11 - Segment Not Present";
-        postcode_of             = 0x6F46 "oF INT 4 - Overflow";
-        postcode_pf             = 0x5046 "PF INT 14 - Pagefault";
-        postcode_rs             = 0x7235 "r5 INT 15 - Reserved";
-        postcode_iop            = 0x7564 "ud INT 6 - Invalid OP code";
+        postcode_ld             = 0x644C "Ld - Locking down hardware access";
+        postcode_authf          = 0x416E "nA - OS Image failed Authentification";
+        postcode_dna            = 0x646E "nd INT 7 - Device not Available";
+        postcode_nmi            = 0x6F6E "no INT 2 - Non-maskable Interrupt";
+        postcode_snp            = 0x506E "nP INT 11 - Segment Not Present";
+        postcode_of             = 0x466F "oF INT 4 - Overflow";
+        postcode_pf             = 0x4650 "PF INT 14 - Pagefault";
+        postcode_rs             = 0x3572 "r5 INT 15 - Reserved";
+        postcode_iop            = 0x6475 "ud INT 6 - Invalid OP code";
     };
     
     constants postcodes_special width(32) "The Xeon Phi Post codes" {
index 92e3bf3..c454af4 100644 (file)
@@ -244,12 +244,12 @@ static errval_t bootstrap_notify(struct xeon_phi *phi,
 
     XBOOT_DEBUG("memsize = 0x%x, reserved size = 0x%x\n", memsize, reserved);
 
-    xeon_phi_boot_res_size_wr(&boot_registers, reserved);
+    xeon_phi_boot_res_size_rawwr(&boot_registers, reserved);
 
     // sending the bootstrap interrupt
     xeon_phi_apic_icr_lo_t icr_lo = xeon_phi_apic_icr_lo_default;
     icr_lo = xeon_phi_apic_icr_lo_vector_insert(icr_lo, xeon_phi_apic_vec_bsp);
-    icr_lo = xeon_phi_apic_icr_lo_dlv_stat_insert(icr_lo, 0x1);
+    icr_lo = xeon_phi_apic_icr_lo_boot_notify_insert(icr_lo, 0x1);
 
     assert(icr_lo == (229 | (1 << 13)));
 
@@ -284,6 +284,11 @@ errval_t xeon_phi_boot(struct xeon_phi *phi,
                              XEON_PHI_MMIO_TO_DBOX(phi));
     xeon_phi_apic_initialize(&apic_registers, XEON_PHI_MMIO_TO_SBOX(phi));
 
+
+    phi->apicid = xeon_phi_boot_download_apicid_rdf(&boot_registers);
+    XBOOT_DEBUG("APICID = %u\n", phi->apicid);
+
+
     // load the coprocessor OS
     err = load_bootloader(phi, xloader_img, &osimg_size, &offset);
     if (err_is_fail(err)) {
@@ -308,14 +313,19 @@ errval_t xeon_phi_boot(struct xeon_phi *phi,
         USER_PANIC_ERR(err, "Could not load multiboot image");
     }
 
-    // start the receive thread
-    serial_start_recv_thread(phi);
+    xeon_phi_boot_download_status_wrf(&boot_registers, 0x0);
 
     XBOOT_DEBUG("Notify value: 0x%x\n", xeon_phi_boot_download_status_rdf(&boot_registers));
 
+    phi->apicid = xeon_phi_boot_download_apicid_rdf(&boot_registers);
+    XBOOT_DEBUG("APICID = %u\n", phi->apicid);
+
     // notify the bootstrap
     bootstrap_notify(phi, osimg_size);
 
+    // start the receive thread
+    serial_start_recv_thread(phi);
+
     uint32_t time = 0;
     while(time < 300) {
         milli_sleep(1000);
index 259d53b..6eaa3d1 100644 (file)
@@ -23,8 +23,6 @@
 #define XEON_PHI_BUFFER_LENGTH 0x400
 #define XEON_PHI_POLL_GIVEUP   0x100
 
-static xeon_phi_serial_t mmio_serial;
-
 uint8_t xeon_phi_id = 0;
 
 static inline void xprintf(uint8_t xid,
@@ -51,7 +49,7 @@ static int xeon_phi_recv_handler(void *arg)
 
     debug_printf("xeon phi receive handler started. %d\n", xarg->xid);
 
-    xeon_phi_serial_ctrl_rawwr(&mmio_serial, xeon_phi_serial_reset);
+    xeon_phi_serial_ctrl_rawwr(&xarg->base, xeon_phi_serial_reset);
 
     nodata = XEON_PHI_POLL_GIVEUP;
 
@@ -62,6 +60,8 @@ static int xeon_phi_recv_handler(void *arg)
             if (--nodata) {
                 continue;
             }
+
+
             // reset counter
             nodata = XEON_PHI_POLL_GIVEUP;
 
index 9418ab6..22d240d 100644 (file)
@@ -256,6 +256,12 @@ errval_t xeon_phi_reset(struct xeon_phi *phi)
         return 1;
     }
 
+#if 0
+#define ENABLE_MIC_INTERRUPTS(mmio) { \
+    uint32_t sboxSice0reg = SBOX_READ((mmio), SBOX_SICE0); \
+    sboxSice0reg |= SBOX_SICE0_DBR_BITS(0xf) | SBOX_SICE0_DMA_BITS(0xff); \
+    SBOX_WRITE(sboxSice0reg, (mmio), SBOX_SICE0); }
+#endif
     return SYS_ERR_OK;
 }
 
index 05cbdcb..ba4baaf 100644 (file)
@@ -20,7 +20,7 @@
 #define XEON_PHI_BOOTLOADER "xeon_phi_bootloader"
 
 /// the name of the Xeon Phi multiboot image containint the modules
-#define XEON_PHI_MULTIBOOT "xeon_phi_multiboot"
+#define XEON_PHI_MULTIBOOT "xeon_phi_multiboot_ramfs"
 
 /// if we use MSIX interrupts or legacy interrupts
 #define XEON_PHI_MSIX_ENABLED 1
index 99583ff..e2ca556 100644 (file)
@@ -95,7 +95,12 @@ bar_mapping_size64(uint64_t base)
     for (pciaddr_t mask = 1;; mask <<= 1) {
         assert(mask != 0);
         if (base & mask) {
-            return mask << 7;
+            /*
+             * Note: we get the actual raw register content here and not
+             *       the bar.base value so no shift.
+             *       - 2014-05-03, RA
+             */
+            return mask;
         }
     }
 }
@@ -1132,10 +1137,8 @@ pci_setup_root_complex(void)
 //           PCI header like for any PCI device. PCI HDR0 is misused
 //           here for the bridges.
 
-static void
-query_bars(pci_hdr0_t devhdr,
-           struct pci_address addr,
-           bool pci2pci_bridge)
+static void query_bars(pci_hdr0_t devhdr, struct pci_address addr,
+                       bool pci2pci_bridge)
 {
     pci_hdr0_bar32_t bar, barorigaddr;
 
@@ -1145,7 +1148,7 @@ query_bars(pci_hdr0_t devhdr,
         orig_value.raw = pci_hdr0_bars_rd(&devhdr, i);
         barorigaddr = orig_value.val;
 
-        // probe BAR to see if it is implemented
+        // probe BAR to determine the mapping size
         pci_hdr0_bars_wr(&devhdr, i, BAR_PROBE);
 
         uint32_t bar_value = pci_hdr0_bars_rd(&devhdr, i);
@@ -1158,15 +1161,16 @@ query_bars(pci_hdr0_t devhdr,
         /*
          * Cannot just compare the base value, with addresses over 4G there
          * will be a problem. Thus we need to check if the entire register is
-         * zero.
-         * 2014-05-02, RA
+         * zero. If it is a 32bit register, then the address part will be filled.
+         * If it is a 64bit register, the type will contain a nonzero value.
+         * - 2014-05-02, RA
          */
         if (bar_value == 0) {
             // BAR not implemented
             continue;
         }
 
-        if (bar.space == 0) {  // memory mapped
+        if (bar.space == 0) { // memory mapped
             //bar(addr(bus, device, function), barnr, orig address, size, space,
             //         prefetchable?, 64bit?).
             //where space = mem | io, prefetchable= prefetchable | nonprefetchable,
@@ -1187,70 +1191,54 @@ query_bars(pci_hdr0_t devhdr,
                 //is constructed out of two consequtive 32bit BARs
 
                 //read the upper 32bits of the address
-                pci_hdr0_bar32_t bar_high, barorigaddr_high;
-                union pci_hdr0_bar32_un orig_value_high;
-                orig_value_high.raw = pci_hdr0_bars_rd(&devhdr, i + 1);
-                barorigaddr_high = orig_value_high.val;
+                uint32_t orig_value_high = pci_hdr0_bars_rd(&devhdr, i + 1);
 
                 // probe BAR to determine the mapping size
                 pci_hdr0_bars_wr(&devhdr, i + 1, BAR_PROBE);
 
-                bar_high = (union pci_hdr0_bar32_un ) { .raw = pci_hdr0_bars_rd(
-                                &devhdr, i + 1) } .val;
+                // read the size information of the bar
+                uint32_t bar_value_high = pci_hdr0_bars_rd(&devhdr, i+1);
 
                 //write original value back to the BAR
-                pci_hdr0_bars_wr(&devhdr, i + 1, orig_value_high.raw);
+                pci_hdr0_bars_wr(&devhdr, i + 1, orig_value_high);
 
-                pciaddr_t base64 = bar_high.base;
+                pciaddr_t base64 = 0, origbase64 = 0;
+                base64 = bar_value_high;
                 base64 <<= 32;
-                base64 |= bar.base;
+                base64 |= (uint32_t) (bar.base<<7);
 
-                pciaddr_t origbase64 = barorigaddr_high.base;
+                origbase64 = orig_value_high;
                 origbase64 <<= 32;
-                origbase64 |= barorigaddr.base;
+                origbase64 |= (uint32_t) (barorigaddr.base<<7);
 
-                PCI_DEBUG(
-                        "(%u,%u,%u): 64bit BAR %d at 0x%" PRIxPCIADDR ", size %" PRIx64 ", %s\n",
-                        addr.bus, addr.device, addr.function, i, origbase64 << 7,
-                        bar_mapping_size64(base64),
-                        (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"));
+                PCI_DEBUG("(%u,%u,%u): 64bit BAR %d at 0x%" PRIxPCIADDR ", size %" PRIx64 ", %s\n",
+                            addr.bus, addr.device, addr.function, i, origbase64,
+                            bar_mapping_size64(base64),
+                            (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"));
 
-                skb_add_fact(
-                        "bar(addr(%u, %u, %u), %d, 16'%"PRIxPCIADDR", "
-                        "16'%" PRIx64 ", mem, %s, %d).",
-                        addr.bus, addr.device, addr.function, i, origbase64 << 7,
-                        bar_mapping_size64(base64),
-                        (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"),
-                        type);
-
-                i++;  //step one forward, because it is a 64bit BAR
-            } else {
-                PCI_DEBUG("(%u,%u,%u): 32bit BAR %d at 0x%" PRIx32 ", size %x, %s\n",
-                          addr.bus, addr.device, addr.function, i,
-                          barorigaddr.base << 7, bar_mapping_size(bar),
-                          (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"));
+                skb_add_fact("bar(addr(%u, %u, %u), %d, 16'%"PRIxPCIADDR", "
+                            "16'%" PRIx64 ", mem, %s, %d).",
+                            addr.bus, addr.device, addr.function, i, origbase64,
+                            bar_mapping_size64(base64),
+                            (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"),
+                            type);
 
+                i++; //step one forward, because it is a 64bit BAR
+            } else {
                 //32bit BAR
-                skb_add_fact(
-                        "bar(addr(%u, %u, %u), %d, 16'%"PRIx32", 16'%" PRIx32 ", mem, %s, %d).",
-                        addr.bus, addr.device, addr.function, i,
-                        (uint32_t) (barorigaddr.base << 7),
-                        (uint32_t) bar_mapping_size(bar),
-                        (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"),
-                        type);
+                skb_add_fact("bar(addr(%u, %u, %u), %d, 16'%"PRIx32", 16'%" PRIx32 ", mem, %s, %d).",
+                             addr.bus, addr.device, addr.function,
+                             i, (uint32_t)(barorigaddr.base << 7), (uint32_t)bar_mapping_size(bar),
+                             (bar.prefetch == 1 ? "prefetchable" : "nonprefetchable"),
+                             type);
             }
         } else {
-            PCI_DEBUG("(%u,%u,%u): IO BAR %d at 0x%x, size %x\n", addr.bus,
-                      addr.device, addr.function, i, barorigaddr.base << 7,
-                      bar_mapping_size(bar));
             //bar(addr(bus, device, function), barnr, orig address, size, space).
             //where space = mem | io
-            skb_add_fact(
-                    "bar(addr(%u, %u, %u), %d, 16'%"PRIx32", 16'%" PRIx32 ", io, "
-                    "nonprefetchable, 32).",
-                    addr.bus, addr.device, addr.function, i,
-                    (uint32_t) (barorigaddr.base << 7),
-                    (uint32_t) bar_mapping_size(bar));
+            skb_add_fact("bar(addr(%u, %u, %u), %d, 16'%"PRIx32", 16'%" PRIx32 ", io, "
+                         "nonprefetchable, 32).",
+                         addr.bus, addr.device, addr.function,
+                         i, (uint32_t)(barorigaddr.base << 7), (uint32_t)bar_mapping_size(bar));
         }
     }
 }