Fixed Octopus dependency bug.
authorMothy <troscoe@inf.ethz.ch>
Sun, 29 Jul 2012 13:02:01 +0000 (15:02 +0200)
committerMothy <troscoe@inf.ethz.ch>
Sun, 29 Jul 2012 13:02:01 +0000 (15:02 +0200)
Cleanup some badly-formatted files.
Added new memory map for TI OMAP 44xx devices.

devices/a9scu.dev
hake/Hakefile
hake/RuleDefs.hs
include/omap44xx_map.h [new file with mode: 0644]
kernel/Hakefile
kernel/arch/arm_gem5/init.c
kernel/arch/arm_gem5/omap.c
lib/barrelfish/Hakefile
usr/pci/Hakefile

index 3ec7a34..7e9ee2a 100644 (file)
  *
  */
  
- device a9scu msbfirst ( addr base ) "Cortex A9 SCU" {
+device a9scu msbfirst ( addr base ) "Cortex A9 SCU" {
  
-        register SCUControl addr(base, 0x0) "SCU Control Register" {
-               _                                               25      rsvd;
-               IC_standby                              1       rw              "IC standby enable";
-               SCU_standby                             1       rw              "SCU standby enable";
-               all_device_to_port0             1       rw              "Force all Device to port 0 enable";
-               SCU_spec_linefill               1       rw              "SCU speculative linefills enable";
-               SCU_ram_parity                  1       rw              "SCU RAMs parity enable";
-               address_filtering               1       rw              "Address Filtering enable";
-               SCU_enable                              1       rw              "SCU enable";
-        };
+    register SCUControl addr(base, 0x0) "SCU Control" {
+       _                       25 rsvd;
+       IC_standby              1 rw    "IC standby enable";
+       SCU_standby             1 rw    "SCU standby enable";
+       all_device_to_port0     1 rw    "Force all Device to port 0 enable";
+       SCU_spec_linefill       1 rw    "SCU speculative linefills enable";
+       SCU_ram_parity          1 rw    "SCU RAMs parity enable";
+       address_filtering       1 rw    "Address Filtering enable";
+       SCU_enable              1 rw    "SCU enable";
+    };
         
-        register SCUConfig     ro addr(base, 0x4) "SCU Configuration Register" {
-               _                                               16      rsvd;
-               tag_ram_sizes                   8       ro              "Tag RAM sizes";
-               cpu_smp                                 4       ro              "CPUs SMP bits";
-               _                                               2       rsvd;
-               cpu_number                              2       ro              "Number of CPUs present";
-        };
-        
-        constants cpu_status "CPU Status" {
-               normal_mode             =       0b00            "Normal mode";
-               dormant_mode    =       0b10            "Dormant mode";
-               powered_off_mode =      0b11            "Powered-off mode";
-        };
-        
-        register SCUPowerStatus addr(base, 0x8) "SCU CPU Power Status Register" {
-               _                                               6       rsvd;
-               cpu3_status                             2       rw              "Status CPU3";
-               _                                               6       rsvd;
-               cpu2_status                             2       rw              "Status CPU2";
-               _                                               6       rsvd;
-               cpu1_status                             2       rw              "Status CPU1";
-               _                                               6       rsvd;
-               cpu0_status                             2       rw              "Status CPU0";
-        };
-       
-       register SCUFilteringStart addr(base, 0x40) "Filtering Start Address Register" {
-               start_address                   12      rw              "Filtering Start address";
-               _                                               20      rsvd;
-       };
-       
-       register SCUFilteringEnd addr(base, 0x44) "Filtering End Address Register" {
-               end_address                     12      rw              "Filtering Start address";
-               _                                       20      rsvd;
-       };
-       
+    register SCUConfig ro addr(base, 0x4) "SCU Configuration" {
+       _               16;
+       tag_ram_sizes   8 ro    "Tag RAM sizes";
+       cpu_smp         4 ro    "CPUs SMP bits";
+       _               2;
+       cpu_number      2 ro    "Number of CPUs present";
+    };
+    
+    constants cpu_status "CPU Status" {
+       normal_mode      = 0b00         "Normal mode";
+       dormant_mode     = 0b10         "Dormant mode";
+       powered_off_mode = 0b11         "Powered-off mode";
+    };
+    
+    register SCUPowerStatus addr(base, 0x8) "SCU CPU Power Status" {
+       _               6;
+       cpu3_status     2 rw    "Status CPU3";
+       _               6;
+       cpu2_status     2 rw    "Status CPU2";
+       _               6;      
+       cpu1_status     2 rw    "Status CPU1";
+       _               6;
+       cpu0_status     2 rw    "Status CPU0";
+    };
+    
+    register SCUFilteringStart addr(base, 0x40) "Filtering Start Address" {
+       start_address   12 rw   "Filtering Start address";
+       _               20;
+    };
+    
+    register SCUFilteringEnd addr(base, 0x44) "Filtering End Address" {
+       end_address     12 rw   "Filtering Start address";
+       _               20;
+    };
  
- };
\ No newline at end of file
+ };
index 1fca6a2..bb958d6 100644 (file)
@@ -4,7 +4,8 @@
 --
 -- This file is distributed under the terms in the attached LICENSE file.
 -- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
+-- ETH Zurich D-INFK CAB F.78, Universitaetstr 6, CH-8092 Zurich. 
+-- Attn: Systems Group.
 --
 -- Hakefile for /hake
 --
index ec835cc..0e989c5 100644 (file)
@@ -3,8 +3,9 @@
 -- All rights reserved.
 --
 -- This file is distributed under the terms in the attached LICENSE file.
--- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
+-- If you do not find this file, copies can be found by writing to:-
+-- ETH Zurich D-INFK CAB F.78, Universitaetstr 6, CH-8092 Zurich. 
+-- Attn: Systems Group.
 --
 -- Basic Hake rule definitions and combinators
 --
diff --git a/include/omap44xx_map.h b/include/omap44xx_map.h
new file mode 100644 (file)
index 0000000..38689a0
--- /dev/null
@@ -0,0 +1,453 @@
+/**
+ * \file
+ * \brief Physical memory map for TI OMAP 44xx-series SoCs. 
+ * 
+ * This is derived from:
+ *
+ * OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference
+ * Manual Version O 
+ * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
+ * Manual Version Q
+ * 
+ * Section numbers refer to the OMAP4460 TRM.
+ */
+
+/*
+ * Copyright (c) 2012, ETH Zurich.
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached LICENSE file.
+ * If you do not find this file, copies can be found by writing to:
+ * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich. 
+ * Attn: Systems Group.
+ */
+
+#ifndef OMAP44XX_MAP_H
+#define OMAP44XX_MAP_H
+
+/* 
+ * 2.2.1 L3_EMU Memory Space Mapping 
+ */
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM_0                  0x54000000
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM_0_SIZE             0x100000
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM_1                  0x54100000
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM_1_SIZE             0x40000
+#define OMAP44XX_MAP_L3_EMU_A9_CPU0_DEBUG_PMU           0x54140000
+#define OMAP44XX_MAP_L3_EMU_A9_CPU0_DEBUG_PMU_SIZE      0x2000
+#define OMAP44XX_MAP_L3_EMU_A9_CPU1_DEBUG_PMU           0x54142000
+#define OMAP44XX_MAP_L3_EMU_A9_CPU1_DEBUG_PMU_SIZE      0x2000
+
+#define OMAP44XX_MAP_L3_EMU_CTI0                        0x54148000
+#define OMAP44XX_MAP_L3_EMU_CTI0_SIZE                   0x1000
+#define OMAP44XX_MAP_L3_EMU_CTI1                        0x54149000
+#define OMAP44XX_MAP_L3_EMU_CTI1_SIZE                   0x1000
+
+#define OMAP44XX_MAP_L3_EMU_PTM0                        0x5414C000
+#define OMAP44XX_MAP_L3_EMU_PTM0_SIZE                   0x1000
+#define OMAP44XX_MAP_L3_EMU_PTM1                        0x5414D000
+#define OMAP44XX_MAP_L3_EMU_PTM1_SIZE                   0x1000
+
+#define OMAP44XX_MAP_L3_EMU_TRACE_FUNNEL                0x54158000
+#define OMAP44XX_MAP_L3_EMU_TRACE_FUNNEL_SIZE           0x1000
+#define OMAP44XX_MAP_L3_EMU_DAP_PC                      0x54159000
+#define OMAP44XX_MAP_L3_EMU_DAP_PC_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L3_EMU_APB                         0x5415F000
+#define OMAP44XX_MAP_L3_EMU_APB_SIZE                    0x1000
+#define OMAP44XX_MAP_L3_EMU_DRM                         0x54160000
+#define OMAP44XX_MAP_L3_EMU_DRM_SIZE                    0x1000
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM                    0x54161000
+#define OMAP44XX_MAP_L3_EMU_MIPI_STM_SIZE               0x1000
+#define OMAP44XX_MAP_L3_EMU_ETB                         0x54162000
+#define OMAP44XX_MAP_L3_EMU_ETB_SIZE                    0x1000
+#define OMAP44XX_MAP_L3_EMU_CS_TPIU                     0x54163000
+#define OMAP44XX_MAP_L3_EMU_CS_TPIU_SIZE                0x1000
+#define OMAP44XX_MAP_L3_EMU_CS_TF0                      0x54164000
+#define OMAP44XX_MAP_L3_EMU_CS_TF0_SIZE                 0x1000
+
+/*
+ * 2.3.1 L4_CFG Memory Space Mapping
+ */
+#define OMAP44XX_MAP_L4_CFG_AP                          0x4A000000
+#define OMAP44XX_MAP_L4_CFG_AP_SIZE                     0x800
+#define OMAP44XX_MAP_L4_CFG_LA                          0x4A000800
+#define OMAP44XX_MAP_L4_CFG_LA_SIZE                     0x800
+#define OMAP44XX_MAP_L4_CFG_IP0                         0x4A001000
+#define OMAP44XX_MAP_L4_CFG_IP0_SIZE                    0x1000
+#define OMAP44XX_MAP_L4_CFG_SYSCTRL_GENERAL_CORE        0x4A002000
+#define OMAP44XX_MAP_L4_CFG_SYSCTRL_GENERAL_CORE_SIZE   0x1000
+#define OMAP44XX_MAP_L4_CFG_CM1                         0x4A004000
+#define OMAP44XX_MAP_L4_CFG_CM1_SIZE                    0x1000
+
+#define OMAP44XX_MAP_L4_CFG_CM2                         0x4A008000
+#define OMAP44XX_MAP_L4_CFG_CM2_SIZE                    0x2000
+
+#define OMAP44XX_MAP_L4_CFG_SDMA                        0x4A056000
+#define OMAP44XX_MAP_L4_CFG_SDMA_SIZE                   0x1000
+#define OMAP44XX_MAP_L4_CFG_HSI_TOP                     0x4A058000
+#define OMAP44XX_MAP_L4_CFG_HSI_TOP_SIZE                0x1000
+#define OMAP44XX_MAP_L4_CFG_HSI_DMA                     0x4A059000
+#define OMAP44XX_MAP_L4_CFG_HSI_DMA_SIZE                0x1000
+#define OMAP44XX_MAP_L4_CFG_HSI_PORT1                   0x4A05A000
+#define OMAP44XX_MAP_L4_CFG_HSI_PORT1_SIZE              0x1000
+#define OMAP44XX_MAP_L4_CFG_HSI_PORT2                   0x4A05B000
+#define OMAP44XX_MAP_L4_CFG_HSI_PORT2_SIZE              0x1000
+
+#define OMAP44XX_MAP_L4_CFG_SAR_ROM                     0x4A05E000
+#define OMAP44XX_MAP_L4_CFG_SAR_ROM_SIZE                0x2000
+
+#define OMAP44XX_MAP_L4_CFG_HSUSBTLL                    0x4A062000
+#define OMAP44XX_MAP_L4_CFG_HSUSBTLL_SIZE               0x1000
+
+#define OMAP44XX_MAP_L4_CFG_HSUSBHOST                   0x4A064000
+#define OMAP44XX_MAP_L4_CFG_HSUSBHOST_SIZE              0x1000
+#define OMAP44XX_MAP_L4_CFG_DSP_SUBSYSTEN               0x4A066000
+#define OMAP44XX_MAP_L4_CFG_DSP_SUBSYSTEN_SIZE          0x1000
+
+#define OMAP44XX_MAP_L4_CFG_FSUSB                       0x4A0A9000
+#define OMAP44XX_MAP_L4_CFG_FSUSB_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_CFG_HSUSBOTG                    0x4A0AB000
+#define OMAP44XX_MAP_L4_CFG_HSUSBOTG_SIZE               0x1000
+#define OMAP44XX_MAP_L4_CFG_USBPHY                      0x4A0AD000
+#define OMAP44XX_MAP_L4_CFG_USBPHY_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_CFG_SR_MPU                      0x4A0D9000
+#define OMAP44XX_MAP_L4_CFG_SR_MPU_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_CFG_SR_IVA                      0x4A0DB000
+#define OMAP44XX_MAP_L4_CFG_SR_IVA_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_CFG_SR_CORE                     0x4A0DD000
+#define OMAP44XX_MAP_L4_CFG_SR_CORE_SIZE                0x1000
+
+#define OMAP44XX_MAP_L4_CFG_MAILBOX                     0x4A0F4000
+#define OMAP44XX_MAP_L4_CFG_MAILBOX_SIZE                0x1000
+#define OMAP44XX_MAP_L4_CFG_SPINLOCK                    0x4A0F6000
+#define OMAP44XX_MAP_L4_CFG_SPINLOCK_SIZE               0x1000
+
+#define OMAP44XX_MAP_L4_CFG_SYSCTRL_PADCONF_CORE        0x4A100000
+#define OMAP44XX_MAP_L4_CFG_SYSCTRL_PADCONF_CORE_SIZE   0x1000
+#define OMAP44XX_MAP_L4_CFG_OCP_WP                      0x4A102000
+#define OMAP44XX_MAP_L4_CFG_OCP_WP_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_CFG_FACE_DETECT                 0x4A10A000
+#define OMAP44XX_MAP_L4_CFG_FACE_DETECT_SIZE            0x1000
+
+#define OMAP44XX_MAP_L4_CFG_C2C_INIT_FIREWALL           0x4A204000
+#define OMAP44XX_MAP_L4_CFG_C2C_INIT_FIREWALL_SIZE      0x1000
+#define OMAP44XX_MAP_L4_CFG_C2C_TARGET_FIREWALL         0x4A206000
+#define OMAP44XX_MAP_L4_CFG_C2C_TARGET_FIREWALL_SIZE    0x1000
+
+#define OMAP44XX_MAP_L4_CFG_MA_FIREWALL                 0x4A20A000
+#define OMAP44XX_MAP_L4_CFG_MA_FIREWALL_SIZE            0x1000
+#define OMAP44XX_MAP_L4_CFG_EMIF_FIREWALL               0x4A20C000
+#define OMAP44XX_MAP_L4_CFG_EMIF_FIREWALL_SIZE          0x1000
+
+#define OMAP44XX_MAP_L4_CFG_GPMC_FIREWALL               0x4A210000
+#define OMAP44XX_MAP_L4_CFG_GPMC_FIREWALL_SIZE          0x1000
+#define OMAP44XX_MAP_L4_CFG_OCMC_RAM_FIREWALL           0x4A212000
+#define OMAP44XX_MAP_L4_CFG_OCMC_RAM_FIREWALL_SIZE      0x1000
+#define OMAP44XX_MAP_L4_CFG_GFX_T_FIREWALL              0x4A214000
+#define OMAP44XX_MAP_L4_CFG_GFX_T_FIREWALL_SIZE         0x1000
+#define OMAP44XX_MAP_L4_CFG_ISS_T_FIREWALL              0x4A216000
+#define OMAP44XX_MAP_L4_CFG_ISS_T_FIREWALL_SIZE         0x1000
+#define OMAP44XX_MAP_L4_CFG_M3_T_FIREWALL               0x4A218000
+#define OMAP44XX_MAP_L4_CFG_M3_T_FIREWALL_SIZE          0x1000
+
+#define OMAP44XX_MAP_L4_CFG_DSS_T_FIREWALL              0x4A21C000
+#define OMAP44XX_MAP_L4_CFG_DSS_T_FIREWALL_SIZE         0x1000
+#define OMAP44XX_MAP_L4_CFG_SL2_T_FIREWALL              0x4A21E000
+#define OMAP44XX_MAP_L4_CFG_SL2_T_FIREWALL_SIZE         0x1000
+#define OMAP44XX_MAP_L4_CFG_IVAHD_CFG_T_FIREWALL        0x4A220000
+#define OMAP44XX_MAP_L4_CFG_IVAHD_CFG_T_FIREWALL_SIZE   0x1000
+
+#define OMAP44XX_MAP_L4_CFG_L4_EMU_FIREWALL             0x4A226000
+#define OMAP44XX_MAP_L4_CFG_L4_EMU_FIREWALL_SIZE        0x1000
+#define OMAP44XX_MAP_L4_CFG_L4_ABE_FIREWALL             0x4A228000
+#define OMAP44XX_MAP_L4_CFG_L4_ABE_FIREWALL_SIZE        0x1000
+
+#define OMAP44XX_MAP_L4_CFG_L4_WKUP                     0x4A300000
+#define OMAP44XX_MAP_L4_CFG_L4_WKUP_SIZE                0x40000
+
+/*
+ * 2.3.2 L4_WKUP Memory Space Mapping
+ */
+#define OMAP44XX_MAP_L4_WKUP_AP                         0x4A300000
+#define OMAP44XX_MAP_L4_WKUP_AP_SIZE                    0x800
+#define OMAP44XX_MAP_L4_WKUP_LA                         0x4A300800
+#define OMAP44XX_MAP_L4_WKUP_LA_SIZE                    0x800
+#define OMAP44XX_MAP_L4_WKUP_IP0                        0x4A301000
+#define OMAP44XX_MAP_L4_WKUP_IP0_SIZE                   0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_32KTIMER                   0x4A304000
+#define OMAP44XX_MAP_L4_WKUP_32KTIMER_SIZE              0x1000
+#define OMAP44XX_MAP_L4_WKUP_PRM                        0x4A306000
+#define OMAP44XX_MAP_L4_WKUP_PRM_SIZE                   0x2000
+
+#define OMAP44XX_MAP_L4_WKUP_SRCM                       0x4A30A000
+#define OMAP44XX_MAP_L4_WKUP_SRCM_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_WKUP_SYSCTRL_GENERAL_WKUP       0x4A30C000
+#define OMAP44XX_MAP_L4_WKUP_SYSCTRL_GENERAL_WKUP_SIZE  0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_GPIO1                      0x4A310000
+#define OMAP44XX_MAP_L4_WKUP_GPIO1_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_WDTIMER2                   0x4A314000 
+#define OMAP44XX_MAP_L4_WKUP_WDTIMER2_SIZE              0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_GPTIMER1                   0x4A318000
+#define OMAP44XX_MAP_L4_WKUP_GPTIMER1_SIZE              0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_KEYBOARD                   0x4A31C000
+#define OMAP44XX_MAP_L4_WKUP_KEYBOARD_SIZE              0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_SYSCTRL_PADCONF_WKUP       0x4A31E000
+#define OMAP44XX_MAP_L4_WKUP_SYSCTRL_PADCONF_WKUP_SIZE  0x1000
+
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM1                   0x4A326000
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM1_SIZE              0x1000
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM2                   0x4A328000
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM2_SIZE              0x800
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM3                   0x4A329000
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM3_SIZE              0x400
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM4                   0x4A32A000
+#define OMAP44XX_MAP_L4_WKUP_SAR_RAM4_SIZE              0x1000
+
+/*
+ * 2.3.3 L4_PER Memory Space Mapping
+ */
+#define OMAP44XX_MAP_L4_PER_AP                          0x48000000
+#define OMAP44XX_MAP_L4_PER_AP_SIZE                     0x800
+#define OMAP44XX_MAP_L4_PER_LA                          0x48000800
+#define OMAP44XX_MAP_L4_PER_LA_SIZE                     0x800
+#define OMAP44XX_MAP_L4_PER_IP0                         0x48001000
+#define OMAP44XX_MAP_L4_PER_IP0_SIZE                    0x400
+#define OMAP44XX_MAP_L4_PER_IP1                         0x48001400
+#define OMAP44XX_MAP_L4_PER_IP1_SIZE                    0x400
+#define OMAP44XX_MAP_L4_PER_IP2                         0x48001800
+#define OMAP44XX_MAP_L4_PER_IP2_SIZE                    0x400
+#define OMAP44XX_MAP_L4_PER_IP3                         0x48001C00
+#define OMAP44XX_MAP_L4_PER_IP3_SIZE                    0x400
+
+#define OMAP44XX_MAP_L4_PER_UART3                       0x48020000
+#define OMAP44XX_MAP_L4_PER_UART3_SIZE                  0x1000
+
+#define OMAP44XX_MAP_L4_PER_GPTIMER2                    0x48030000
+#define OMAP44XX_MAP_L4_PER_GPTIMER2_SIZE               0x1000
+#define OMAP44XX_MAP_L4_PER_GPTIMER3                    0x48034000
+#define OMAP44XX_MAP_L4_PER_GPTIMER3_SIZE               0x1000
+#define OMAP44XX_MAP_L4_PER_GPTIMER4                    0x48036000
+#define OMAP44XX_MAP_L4_PER_GPTIMER4_SIZE               0x1000
+
+#define OMAP44XX_MAP_L4_PER_GPTIMER9                    0x4803E000
+#define OMAP44XX_MAP_L4_PER_GPTIMER9_SIZE               0x1000
+#define OMAP44XX_MAP_L4_PER_DISPLAY                     0x48040000
+#define OMAP44XX_MAP_L4_PER_DISPLAY_SIZE                0x10000
+
+#define OMAP44XX_MAP_L4_PER_GPIO2                       0x48055000
+#define OMAP44XX_MAP_L4_PER_GPIO2_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_GPIO3                       0x48057000
+#define OMAP44XX_MAP_L4_PER_GPIO3_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_GPIO4                       0x48059000
+#define OMAP44XX_MAP_L4_PER_GPIO4_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_GPIO5                       0x4805B000
+#define OMAP44XX_MAP_L4_PER_GPIO5_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_GPIO6                       0x4805D000
+#define OMAP44XX_MAP_L4_PER_GPIO6_SIZE                  0x1000
+
+#define OMAP44XX_MAP_L4_PER_I2C3                        0x48060000
+#define OMAP44XX_MAP_L4_PER_I2C3_SIZE                   0x1000
+
+#define OMAP44XX_MAP_L4_PER_UART1                       0x4806A000
+#define OMAP44XX_MAP_L4_PER_UART1_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_UART2                       0x4806C000
+#define OMAP44XX_MAP_L4_PER_UART2_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_UART4                       0x4806E000
+#define OMAP44XX_MAP_L4_PER_UART4_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_PER_I2C1                        0x48070000
+#define OMAP44XX_MAP_L4_PER_I2C1_SIZE                   0x1000
+#define OMAP44XX_MAP_L4_PER_I2C2                        0x48072000
+#define OMAP44XX_MAP_L4_PER_I2C2_SIZE                   0x1000
+
+#define OMAP44XX_MAP_L4_PER_SLIMBUS2                    0x48076000
+#define OMAP44XX_MAP_L4_PER_SLIMBUS2_SIZE               0x1000
+#define OMAP44XX_MAP_L4_PER_ELM                         0x48078000
+#define OMAP44XX_MAP_L4_PER_ELM_SIZE                    0x1000
+
+#define OMAP44XX_MAP_L4_PER_GPTIMER10                   0x48086000
+#define OMAP44XX_MAP_L4_PER_GPTIMER10_SIZE              0x1000
+#define OMAP44XX_MAP_L4_PER_GPTIMER11                   0x48088000
+#define OMAP44XX_MAP_L4_PER_GPTIMER11_SIZE              0x1000
+
+#define OMAP44XX_MAP_L4_PER_MCBSP4                      0x48096000
+#define OMAP44XX_MAP_L4_PER_MCBSP4_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_PER_MCSPI1                      0x48098000
+#define OMAP44XX_MAP_L4_PER_MCSPI1_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_PER_MCSPI2                      0x4809A000
+#define OMAP44XX_MAP_L4_PER_MCSPI2_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_PER_HSMMC1                      0x4809C000
+#define OMAP44XX_MAP_L4_PER_HSMMC1_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_PER_MMC_SD3                     0x480AD000
+#define OMAP44XX_MAP_L4_PER_MMC_SD3_SIZE                0x1000
+
+#define OMAP44XX_MAP_L4_PER_HDQ                         0x480B2000
+#define OMAP44XX_MAP_L4_PER_HDQ_SIZE                    0x1000
+
+#define OMAP44XX_MAP_L4_PER_HSMMC2                      0x480B4000
+#define OMAP44XX_MAP_L4_PER_HSMMC2_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_PER_MCSPI3                      0x480B8000
+#define OMAP44XX_MAP_L4_PER_MCSPI3_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_PER_MCSPI4                      0x480BA000
+#define OMAP44XX_MAP_L4_PER_MCSPI4_SIZE                 0x1000
+
+#define OMAP44XX_MAP_L4_PER_MMC_SD4                     0x480D1000
+#define OMAP44XX_MAP_L4_PER_MMC_SD4_SIZE                0x1000
+
+#define OMAP44XX_MAP_L4_PER_MMC_SD5                     0x480D2000
+#define OMAP44XX_MAP_L4_PER_MMC_SD5_SIZE                0x1000
+
+#define OMAP44XX_MAP_L4_PER_I2C4                        0x48350000
+#define OMAP44XX_MAP_L4_PER_I2C4_SIZE                   0x1000
+
+/*
+ * 2.3.4 ABE L4 Memory Space Mapping
+ */
+#define OMAP44XX_MAP_L4_ABE_L3_ABE                      0x40100000
+#define OMAP44XX_MAP_L4_ABE_L3_ABE_SIZE                 0x4000
+
+#define OMAP44XX_MAP_L4_ABE_MCBSP1                      0x40122000
+#define OMAP44XX_MAP_L4_ABE_MCBSP1_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_ABE_MCBSP2                      0x40124000
+#define OMAP44XX_MAP_L4_ABE_MCBSP2_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_ABE_MCBSP3                      0x40126000
+#define OMAP44XX_MAP_L4_ABE_MCBSP3_SIZE                 0x1000
+#define OMAP44XX_MAP_L4_ABE_MCASP                       0x40128000
+#define OMAP44XX_MAP_L4_ABE_MCASP_SIZE                  0x1000
+#define OMAP44XX_MAP_L4_ABE_SLIMBUS1                    0x4012C000
+#define OMAP44XX_MAP_L4_ABE_SLIMBUS1_SIZE               0x1000
+#define OMAP44XX_MAP_L4_ABE_DMIC                        0x4012E000
+#define OMAP44XX_MAP_L4_ABE_DMIC_SIZE                   0x1000
+#define OMAP44XX_MAP_L4_ABE_WDTIMER3                    0x40130000
+#define OMAP44XX_MAP_L4_ABE_WDTIMER3_SIZE               0x1000
+#define OMAP44XX_MAP_L4_ABE_MCPDM                       0x40132000
+#define OMAP44XX_MAP_L4_ABE_MCPDM_SIZE                  0x1000
+
+#define OMAP44XX_MAP_L4_ABE_GPTIMER5                    0x40138000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER5_SIZE               0x1000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER6                    0x4013A000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER6_SIZE               0x1000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER7                    0x4013C000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER7_SIZE               0x1000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER8                    0x4013E000
+#define OMAP44XX_MAP_L4_ABE_GPTIMER8_SIZE               0x1000
+
+#define OMAP44XX_MAP_L4_ABE_DMEM                        0x40180000
+#define OMAP44XX_MAP_L4_ABE_DMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L4_ABE_CMEM                        0x401A0000
+#define OMAP44XX_MAP_L4_ABE_CMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L4_ABE_SMEM                        0x401C0000
+#define OMAP44XX_MAP_L4_ABE_SMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L4_ABE_AESS                        0x401F1000
+#define OMAP44XX_MAP_L4_ABE_AESS_SIZE                   0x1000
+
+/*
+ * ABE L3 Memory Space Mapping
+ */
+#define OMAP44XX_MAP_L3_ABE_L3_ABE                      0x49000000
+#define OMAP44XX_MAP_L3_ABE_L3_ABE_SIZE                 0x4000
+
+#define OMAP44XX_MAP_L3_ABE_MCBSP1                      0x49022000
+#define OMAP44XX_MAP_L3_ABE_MCBSP1_SIZE                 0x1000
+#define OMAP44XX_MAP_L3_ABE_MCBSP2                      0x49024000
+#define OMAP44XX_MAP_L3_ABE_MCBSP2_SIZE                 0x1000
+#define OMAP44XX_MAP_L3_ABE_MCBSP3                      0x49026000
+#define OMAP44XX_MAP_L3_ABE_MCBSP3_SIZE                 0x1000
+#define OMAP44XX_MAP_L3_ABE_MCASP                       0x49028000
+#define OMAP44XX_MAP_L3_ABE_MCASP_SIZE                  0x1000
+#define OMAP44XX_MAP_L3_ABE_SLIMBUS1                    0x4902C000
+#define OMAP44XX_MAP_L3_ABE_SLIMBUS1_SIZE               0x1000
+#define OMAP44XX_MAP_L3_ABE_DMIC                        0x4902E000
+#define OMAP44XX_MAP_L3_ABE_DMIC_SIZE                   0x1000
+#define OMAP44XX_MAP_L3_ABE_WDTIMER3                    0x49030000
+#define OMAP44XX_MAP_L3_ABE_WDTIMER3_SIZE               0x1000
+#define OMAP44XX_MAP_L3_ABE_MCPDM                       0x49032000
+#define OMAP44XX_MAP_L3_ABE_MCPDM_SIZE                  0x1000
+
+#define OMAP44XX_MAP_L3_ABE_GPTIMER5                    0x49038000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER5_SIZE               0x1000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER6                    0x4903A000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER6_SIZE               0x1000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER7                    0x4903C000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER7_SIZE               0x1000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER8                    0x4903E000
+#define OMAP44XX_MAP_L3_ABE_GPTIMER8_SIZE               0x1000
+
+#define OMAP44XX_MAP_L3_ABE_DMEM                        0x49080000
+#define OMAP44XX_MAP_L3_ABE_DMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L3_ABE_CMEM                        0x490A0000
+#define OMAP44XX_MAP_L3_ABE_CMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L3_ABE_SMEM                        0x490C0000
+#define OMAP44XX_MAP_L3_ABE_SMEM_SIZE                   0x10000
+
+#define OMAP44XX_MAP_L3_ABE_AESS                        0x490F1000
+#define OMAP44XX_MAP_L3_ABE_AESS_SIZE                   0x1000
+
+/*
+ * 2.4 Dual Cortex-M3 Subsystem Memory Space Mapping
+ */
+
+/*
+ * 2.5 DSP Subsystem Memory Space Mapping
+ */
+
+/* 
+ * 2.6.1 L3 Interconnect View of the Display Memory Spac
+ */
+#define OMAP44XX_MAP_L3_DISPLAY_REGISTERS               0x58000000
+#define OMAP44XX_MAP_L3_DISPLAY_REGISTERS_SIZE          0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_DISPC                   0x58001000
+#define OMAP44XX_MAP_L3_DISPLAY_DISPC_SIZE              0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_RFBI                    0x58002000
+#define OMAP44XX_MAP_L3_DISPLAY_RFBI_SIZE               0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_VENC                    0x58003000
+#define OMAP44XX_MAP_L3_DISPLAY_VENC_SIZE               0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_DSI1                    0x58004000
+#define OMAP44XX_MAP_L3_DISPLAY_DSI1_SIZE               0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_DSI2                    0x58005000
+#define OMAP44XX_MAP_L3_DISPLAY_DSI2_SIZE               0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_HDMI                    0x58006000
+#define OMAP44XX_MAP_L3_DISPLAY_HDMI_SIZE               0x1000
+#define OMAP44XX_MAP_L3_DISPLAY_HDCP                    0x58007000
+#define OMAP44XX_MAP_L3_DISPLAY_HDCP_SIZE               0x1000
+
+/* 
+ * 2.6.2 L4 Interconnect View of the Display Memory Spac
+ */
+#define OMAP44XX_MAP_L4_DISPLAY_REGISTERS               0x48040000
+#define OMAP44XX_MAP_L4_DISPLAY_REGISTERS_SIZE          0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_DISPC                   0x48041000
+#define OMAP44XX_MAP_L4_DISPLAY_DISPC_SIZE              0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_RFBI                    0x48042000
+#define OMAP44XX_MAP_L4_DISPLAY_RFBI_SIZE               0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_VENC                    0x48043000
+#define OMAP44XX_MAP_L4_DISPLAY_VENC_SIZE               0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_DSI1                    0x48044000
+#define OMAP44XX_MAP_L4_DISPLAY_DSI1_SIZE               0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_DSI2                    0x48045000
+#define OMAP44XX_MAP_L4_DISPLAY_DSI2_SIZE               0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_HDMI                    0x48046000
+#define OMAP44XX_MAP_L4_DISPLAY_HDMI_SIZE               0x1000
+#define OMAP44XX_MAP_L4_DISPLAY_HDCP                    0x48047000
+#define OMAP44XX_MAP_L4_DISPLAY_HDCP_SIZE               0x1000
+
+/*
+ * Others from Table 2.1
+ */
+#define OMAP44XX_MAP_SDRAM                             0x80000000
+
+#endif  // OMAP44XX_MAP_H
index 6de2949..7b2ce31 100644 (file)
@@ -108,7 +108,7 @@ in [
         cfiles = [ "exec.c", "misc.c", "phys_mmap.c" ]
         arch_sfiles = [ "boot.S", "exceptions.S" ]
        arch_cfiles = ["init.c", "omap.c", "paging.c", "pl011_uart.c", "startup_arch.c", "syscall.c", "kludges.c", "multiboot.c", "omap_uart.c", "start_aps.c", "exn.c",  "kputchar.c" ]
-       mackerelFiles = [ "arm", "arm_icp_pit", "pl011_uart", "pl130_gic", "sp804_pit", "cortex_a9_pit", "a9scu", "omap_uart" ]
+       mackerelFiles = [ "arm", "arm_icp_pit", "pl011_uart", "pl130_gic", "sp804_pit", "cortex_a9_pit", "a9scu", "omap_uart", "omap44xx_id" ]
         libs = [ "elf", "cpio" ]
     in mkrules "arm_gem5" cfiles sfiles mackerelFiles libs [] [] arch_cfiles arch_sfiles),
     
index e271e42..9bfa0d4 100644 (file)
@@ -20,7 +20,7 @@
 #include <arm_hal.h>
 #include <cpiobin.h>
 #include <getopt/getopt.h>
-#include <romfs_size.h>
+//#include <romfs_size.h>
 #include <cp15.h>
 #include <elf/elf.h>
 #include <arm_core_data.h>
 #include <global.h>
 #include <start_aps.h>
 
+#include <omap44xx_map.h>
 #include <dev/omap44xx_id_dev.h>
 
 #define GEM5_RAM_SIZE  0x20000000
 //#define GEM5_RAM_SIZE        0x2000000
-#define CONFIG_PHYSBASE 0x4a002000
-#define DEVICE_ID_PADDR 0x4A002204
 
 extern errval_t early_serial_init(uint8_t port_no);
 
@@ -255,43 +254,39 @@ static void enable_cycle_counter_user_access(void)
 }
 #endif
 
-void
-paging_map_device_section(uintptr_t ttbase, lvaddr_t va, lpaddr_t pa);
+void paging_map_device_section(uintptr_t ttbase, lvaddr_t va, lpaddr_t pa);
 
 
 static void paging_init(void)
 {
+    // configure system to use TTBR1 for VAs >= 2GB
+    uint32_t ttbcr;
+    ttbcr = cp15_read_ttbcr();
+    ttbcr |= 1;
+    cp15_write_ttbcr(ttbcr);
+    
+    // make sure pagetables are aligned to 16K
+    aligned_boot_l1_low = (union arm_l1_entry *)ROUND_UP((uintptr_t)boot_l1_low, ARM_L1_ALIGN);
+    aligned_boot_l1_high = (union arm_l1_entry *)ROUND_UP((uintptr_t)boot_l1_high, ARM_L1_ALIGN);
+    
+    lvaddr_t vbase = MEMORY_OFFSET, base =  0;
+
+    for(size_t i=0; i < ARM_L1_MAX_ENTRIES/2; i++,
+           base += ARM_L1_SECTION_BYTES, vbase += ARM_L1_SECTION_BYTES) {
+       // create 1:1 mapping
+       //              paging_map_kernel_section((uintptr_t)aligned_boot_l1_low, base, base);
+       paging_map_device_section((uintptr_t)aligned_boot_l1_low, base, base);
+       
+       // Alias the same region at MEMORY_OFFSET (gem5 code)
+       // create 1:1 mapping for pandaboard
+       //              paging_map_device_section((uintptr_t)boot_l1_high, vbase, vbase);
+       /* if(vbase < 0xc0000000) */
+       paging_map_device_section((uintptr_t)aligned_boot_l1_high, vbase, vbase);
+    }
 
-
-       // configure system to use TTBR1 for VAs >= 2GB
-       uint32_t ttbcr;
-       ttbcr = cp15_read_ttbcr();
-       ttbcr |= 1;
-       cp15_write_ttbcr(ttbcr);
-
-       // make sure pagetables are aligned to 16K
-       aligned_boot_l1_low = (union arm_l1_entry *)ROUND_UP((uintptr_t)boot_l1_low, ARM_L1_ALIGN);
-       aligned_boot_l1_high = (union arm_l1_entry *)ROUND_UP((uintptr_t)boot_l1_high, ARM_L1_ALIGN);
-
-       lvaddr_t vbase = MEMORY_OFFSET, base =  0;
-
-       for(size_t i=0; i < ARM_L1_MAX_ENTRIES/2; i++,
-               base += ARM_L1_SECTION_BYTES, vbase += ARM_L1_SECTION_BYTES)
-       {
-               // create 1:1 mapping
-//             paging_map_kernel_section((uintptr_t)aligned_boot_l1_low, base, base);
-               paging_map_device_section((uintptr_t)aligned_boot_l1_low, base, base);
-
-               // Alias the same region at MEMORY_OFFSET (gem5 code)
-               // create 1:1 mapping for pandaboard
-//             paging_map_device_section((uintptr_t)boot_l1_high, vbase, vbase);
-                /* if(vbase < 0xc0000000) */
-                    paging_map_device_section((uintptr_t)aligned_boot_l1_high, vbase, vbase);
-       }
-
-       // Activate new page tables
-       cp15_write_ttbr1((lpaddr_t)aligned_boot_l1_high);
-        cp15_write_ttbr0((lpaddr_t)aligned_boot_l1_low);
+    // Activate new page tables
+    cp15_write_ttbr1((lpaddr_t)aligned_boot_l1_high);
+    cp15_write_ttbr0((lpaddr_t)aligned_boot_l1_low);
 }
 
 void kernel_startup_early(void)
@@ -370,12 +365,12 @@ static void  __attribute__ ((noinline,noreturn)) text_init(void)
 
     // Test MMU by remapping the device identifier and reading it using a
     // virtual address 
-    lpaddr_t id_code_section = CONFIG_PHYSBASE & ~ARM_L1_SECTION_MASK;
+    lpaddr_t id_code_section = OMAP44XX_MAP_L4_CFG_SYSCTRL_GENERAL_CORE & ~ARM_L1_SECTION_MASK;
     lvaddr_t id_code_remapped = paging_map_device(id_code_section, 
                                                   ARM_L1_SECTION_BYTES);
     omap44xx_id_t id;
     omap44xx_id_initialize(&id, (mackerel_addr_t)(id_code_remapped + 
-                                (CONFIG_PHYSBASE & ARM_L1_SECTION_MASK)));
+                                (OMAP44XX_MAP_L4_CFG_SYSCTRL_GENERAL_CORE & ARM_L1_SECTION_MASK)));
     char buf[200];
     omap44xx_id_code_pr(buf,200,&id);
     printf("Using MMU, %s", buf);
@@ -415,13 +410,6 @@ static void  __attribute__ ((noinline,noreturn)) text_init(void)
     arm_kernel_startup();
 }
 
-void put_serial_test(char c);
-void put_serial_test(char c)
-{
-  volatile uint32_t *reg = (uint32_t *)0x48020000;
-  *reg = c;
-}
-
 /**
  * Use Mackerel to print the identification from the system
  * configuration block.
@@ -430,7 +418,7 @@ static void print_system_identification(void)
 {
     char buf[800];
     omap44xx_id_t id;
-    omap44xx_id_initialize(&id, (mackerel_addr_t)CONFIG_PHYSBASE);
+    omap44xx_id_initialize(&id, (mackerel_addr_t)OMAP44XX_MAP_L4_CFG_SYSCTRL_GENERAL_CORE);
     omap44xx_id_pr(buf, 799, &id);
     printf("%s", buf);
     omap44xx_id_codevals_prtval(buf, 799, omap44xx_id_code_rawrd(&id));
index c64113f..a79de7b 100644 (file)
@@ -18,6 +18,8 @@
 #include <dev/a9scu_dev.h>
 
 #include <omap_uart.h>
+#include <omap44xx_map.h>
+
 #include <serial.h>
 #include <arm_hal.h>
 #include <cp15.h>
@@ -528,24 +530,20 @@ int scu_get_core_count(void)
 #define CONSOLE_PORT 2
 #define DEBUG_PORT   2
 
-#define UART3_VBASE                    0x48020000
 #define UART3_SECTION_OFFSET               0x20000
-#define UART_DEVICE_BYTES              0x1000
-#define UART_MAPPING_DIFF              0x1000
 
 static omap_uart_t ports[4];
 
-void enable_mmu(void);
-
 static errval_t serial_init(uint8_t index, uint8_t port_no)
 {
     if (port_no < 4) {
         assert(port_no == 2);
-        lvaddr_t base = paging_map_device(UART3_VBASE, UART_DEVICE_BYTES);
+        lvaddr_t base = paging_map_device(OMAP44XX_MAP_L4_PER_UART3,
+                                         OMAP44XX_MAP_L4_PER_UART3_SIZE);
         printf("serial_init: base = 0x%"PRIxLVADDR" 0x%"PRIxLVADDR"\n",
                 base, base + UART3_SECTION_OFFSET);
 
-        volatile uint32_t *p2 = (uint32_t *) UART3_VBASE;
+        volatile uint32_t *p2 = (uint32_t *)OMAP44XX_MAP_L4_PER_UART3;
         volatile uint32_t *p = (uint32_t *) (base + UART3_SECTION_OFFSET);
         *p2 = 's';
         *p = 'S';
@@ -563,7 +561,7 @@ errval_t early_serial_init(uint8_t port_no)
 {
     if (port_no < 4) {
         assert(ports[port_no].base == 0);
-        omap_uart_init(&ports[CONSOLE_PORT], UART3_VBASE);
+        omap_uart_init(&ports[CONSOLE_PORT], OMAP44XX_MAP_L4_PER_UART3);
         return SYS_ERR_OK;
     }
     else {
index af33626..f07f706 100644 (file)
@@ -77,6 +77,7 @@
                     flounderBindings = [ "mem", "octopus", "serial",
                                          "interdisp", "spawn", "keyboard" ],
                     -- only makes sense to compile monitor binding for lmp
+                    flounderTHCStubs = [ "octopus" ],
                     flounderExtraBindings = [ ("monitor", ["lmp"]),
                                              ("monitor_blocking", ["lmp", "rpcclient"]),
                                               ("mem", ["rpcclient"]),
index c831b3a..8e42c30 100644 (file)
@@ -1,19 +1,21 @@
 --------------------------------------------------------------------------
--- Copyright (c) 2007-2010, ETH Zurich.
+-- Copyright (c) 2007-2012, ETH Zurich.
 -- All rights reserved.
 --
 -- This file is distributed under the terms in the attached LICENSE file.
 -- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
+-- ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich. 
+-- Attn: Systems Group.
 --
--- Hakefile for /usr/pci
+-- Hakefile for /usr/pci, the PCI bus driver.
 --
 --------------------------------------------------------------------------
 
 [  build application { target = "pci",
                       flounderDefs = [ "acpi", "monitor", "monitor_blocking" ],
                       flounderExtraDefs = [ ("monitor_blocking", ["rpcclient"]) ],
-                      flounderBindings = [ "pci", "acpi" ],
+                      flounderTHCStubs = [ "octopus" ],
+                      flounderBindings = [ "pci", "acpi", "octopus" ],
                       flounderExtraBindings = [("acpi", ["rpcclient"])],
                                             
                       mackerelDevices = [ "pci_hdr0", "pci_hdr1", "ht_config" ],