First take on complete OMAP4460 specs
authorDaniel Schwyn <schwyda@student.ethz.ch>
Fri, 9 Jun 2017 13:00:19 +0000 (15:00 +0200)
committerDaniel Schwyn <schwyda@student.ethz.ch>
Tue, 13 Jun 2017 12:22:55 +0000 (14:22 +0200)
Signed-off-by: Daniel Schwyn <schwyda@student.ethz.ch>

socs/omap4460.soc

index 3a41c72..b113baf 100644 (file)
  * 2.2 L3 Memory space mapping
  */
 /* Q0 */
-GPM is memory accept [0x00000000/30]
+SRAM is memory accept [0/30]
 
 /* Q1 */
-boot_ROM_internal is memory accept [0x40028000-0x40033FFF]
-L3_OCM_RAM is memory accept [0x40300000-0x4030DFFF]
-L3_config is device accept [0x44000000/26]
+BOOT_ROM is memory accept [0-0xBFFF]
+L3_OCM_RAM is memory accept [0-0xDFFF]
 
 /* Q2 */
 SDRAM is memory accept [0/30]
@@ -33,185 +32,158 @@ SDRAM is memory accept [0/30]
 /* TODO: Tiler view */
 
 L3 is map [
-        0x00000000/30 to GPMC
+        0x00000000/30 to SRAM at 0
         /* 0x40000000-0x4002FFFF reserved */
-        0x40030000-0x4003BFFF to boot_ROM_internal
+        0x40030000-0x4003BFFF to BOOT_ROM at 0
         /* 0x4003C000-0x400FFFFF reserved */ //TRM: 0x40034000-0x400FFFFF?
         0x40100000/20 to L4_ABE at 0
         /* 0x40200000/20 reserved */
-        0x40300000-0x4030DFFFF to L3_OCM_RAM
+        0x40300000-0x4030DFFFF to L3_OCM_RAM at 0
         /* 0x4030E000-0x43FFFFFF reserved */
-        0x44000000/26 to L3_config
+        0x44000000/26 to L3_config at 0
         0x48000000/24 to L4_PER
         0x49000000/24 to L4_ABE at 0
         0x4A000000/24 to L4_CFG
         /* 0x4B000000/24 reserved */
-        0x4C000000/24 to EMIF1
-        0x4D000000/24 to EMIF2
-        0x4E000000/25 to DMM
-        0x50000000/25 to GPMC_config
-        // 0x52000000/25 ISS
-        0x54000000/24 to L3_EMU
-        0x55000000/24 to M3_subsystem
-        // 0x56000000/25 SGX
-        0x58000000/24 to Display_subsystem
+        0x4C000000/24 to EMIF1 at 0
+        0x4D000000/24 to EMIF2 at 0
+        0x4E000000/25 to DMM at 0
+        0x50000000/25 to GPMC at 0
+        0x52000000/25 to ISS at 0
+        0x54000000/24 to L3_EMU at 0
+        0x55000000/24 to M3
+        0x56000000/25 to SGX at 0
+        0x58000000/24 to Display at 0
         /* 0x59000000/24 reserved */
         // 0x5A000000/24 IVA-HD configuration
         // 0x5B000000/24 IVA-HD SL2
         /* 0x5C000000/26 reserved */
         // 0x60000000/28 Tiler address mapping
-        0x80000000/30 to EMIF1-CS0_SDRAM
-        /* other RAM controllers disabled at reset */
+        0x80000000/30 to SDRAM at 0
       ]
 
 /*
  * 2.2.1 L3_EMU Memory Space Mapping
  */
-MIPI_STM_0 is device accept [0x54000000/20]
-MIPI_STM_1 is device accept [0x54100000/18]
-A9_CPU0_debug_PMU is device accept [0x54140000/13]
-A9_CPU1_debug_PMU is device accept [0x54142000/13]
-CTI0 is device accept [0x54148000/12]
-CTI1 is device accept [0x54149000/12]
-PTM0 is device accept [0x5414C000/12]
-PTM1 is device accept [0x5414D000/12]
-Trace_funnel is device accept [0x54158000/12]
-DAP_PC is device accept [0x54159000/12]
-APB is device accept [0x5415F000/12]
-DRM is device accept [0x54160000/12]
-MIPI_STM is device accept [0x54161000/12]
-ETB is device accept [0x54162000/12]
-CS_TPIU is device accept [0x54163000/12]
-CS_TF0 is device accept [0x54164000/12]
-tech_spec_registers_1 is accept [0x54167000/12]
-tech_spec_registers_2 is accept [0x54180000/12]
-
 L3_EMU is map [
-            0x54000000/20 to MIPI_STM_0
-            0x54100000/18 to MIPI_STM_1
-            0x54140000/13 to A9_CPU0_debug_PMU
-            0x54142000/13 to A9_CPU1_debug_PMU
+            0x54000000/20 to MIPI_STM_0 at 0
+            0x54100000/18 to MIPI_STM_1 at 0
+            0x54140000/13 to A9_CPU0_debug_PMU at 0
+            0x54142000/13 to A9_CPU1_debug_PMU at 0
             /* 0x54144000/14 reserved */
-            0x54148000/12 to CTI0
-            0x54149000/12 to CTI1
+            0x54148000/12 to CTI0 at 0
+            0x54149000/12 to CTI1 at 0
             /* 0x5414A000/13 reserved */
-            0x5414C000/12 to PTM0
-            0x5414D000/12 to PTM1
+            0x5414C000/12 to PTM0 at 0
+            0x5414D000/12 to PTM1 at 0
             /* 0x5414E000/13 reserved */
-            0x54158000/12 to Trace_funnel
-            0x54159000/12 to DAP_PC
+            0x54158000/12 to A9_CS-TF at 0
+            0x54159000/12 to DAP_PC at 0
             /* 0x5415A000-0x5415EFFF reserved */
-            0x5416F000/12 to APB
-            0x54160000/12 to DRM
-            0x54161000/12 to MIPI_STM
-            0x54162000/12 to ETB
-            0x54163000/12 to CS_TPIU
-            0x54164000/12 to CS_TF0
+            0x5416F000/12 to APB at 0
+            0x54160000/12 to DRM at 0
+            0x54161000/12 to MIPI_STM at 0
+            0x54162000/12 to CS-ETB at 0
+            0x54163000/12 to CS-TPIU at 0
+            0x54164000/12 to CS-TF at 0
             /* 0x54165000/13 reserved */
-            0x54167000/12 to tech_spec_registers_1
+            // 0x54167000/12 Technology specific registers
             /* 0x54168000-0x5417FFFF reserved */
-            0x54180000/12 to tech_spec_registers_2
+            // 0x54180000/12 Technology specific registers
             /* 0x54181000-0x541FFFFF reserved */
-            // XXX: What about 0x54200000-0x54FFFFFF
+            // XXX: What about 0x54200000-0x54FFFFFF?
           ]
 
 /*
  * 2.3.1 L4_CFG Memory Space Mapping
  */
-CM1 is device accept [0x4A004000/12]
-CM2 is device accept [0x4A008000/12]
-SAR_ROM is device accept [0x4A05E000/13]
-
-OCP-WP is device accept [0x4A102000/12]
+SAR_ROM is device accept [0/13]
 
 L4_CFG is map [
-            0x4A000000/11 to L4_CFG_AP
-            0x4A000800/11 to L4_CFG_LA
-            0x4A001000/12 to L4_CFG_IP0
-            0x4A002000/12 to SYSCTRL_GENERAL_CORE
+            0x4A000000/11 to CFG_AP at 0
+            0x4A000800/11 to CFG_LA at 0
+            0x4A001000/12 to CFG_IP0 at 0
+            0x4A002000/12 to SYSCTRL_GENERAL_CORE at 0
             // 0x4A003000/12 L4 interconnect
-            0x4A004000/12 to CM1
+            0x4A004000/12 to CM1 at 0
             // 0x4A005000/12 L4 interconnect
             /* 0x4A006000/13 reserved
-            0x4A008000/13 to CM2
+            0x4A008000/13 to CM2 at 0
             // 0x4A00A000/12 L4 interconnect
             /* 0x4A00B000-0x4A055FFF reserved */
-            0x4A056000/12 to sDMA
+            0x4A056000/12 to SDMA at 0
             // 0x4A057000/12 L4 interconnect
-            0x4A058000/12 to HSI_top
-            0x4A059000/12 to HSI_DMA
-            0x4A05A000/12 to HSI_Port1
-            0x4A05B000/12 to HSI_Port2
+            0x4A058000/12 to HSI at 0
             // 0x4A05C000/12 L4 interconnect
             /* 0x4A05D000/12 reserved */
-            0x4A05E000/13 to SAR_ROM
+            0x4A05E000/13 to SAR_ROM at 0
             // 0x4A060000/12 L4 interconnect
             /* 0x4A061000/12 reserved */
-            0x4A062000/12 to HSUSBTLL
+            0x4A062000/12 to HSUSBTLL at 0
             // 0x4A063000/12 L4 interconnect
-            0x4A064000/12 to HSUSBHOST
+            0x4A064000/12 to HSUSBHOST at 0
             // 0x4A065000/12 L4 interconnect
-            0x4A066000/12 to DSP_subsystem at 0x01C20000
+            0x4A066000/12 to DSP at 0x01C20000
             // 0x4A067000/12 L4 interconnect
             /* 0x4A068000-0x4A0A8FFF reserved */
-            0x4A0A9000/12 to FSUSB
+            0x4A0A9000/12 to FSUSBHOST at 0
             // 0x4A0AA000/12 L4 interconnect
-            0x4A0AB000/12 to HSUSBOTG
+            0x4A0AB000/12 to HSUSBOTG at 0
             // 0x4A0AC000/12 L4 interconnect
-            0x4A0AD000/12 to USBPHY
+            0x4A0AD000/12 to USBPHY at 0
             // 0x4A0AE000/12 L4 interconnect
             /* 0x4A0AF000-0x4A0D8FFF reserved */
-            0x4A0D9000/12 to SR_MPU
+            0x4A0D9000/12 to SR_MPU at 0
             // 0x4A0DA000/12 L4 interconnect
-            0x4A0DB000/12 to SR_IVA
+            0x4A0DB000/12 to SR_IVA at 0
             // 0x4A0DC000/12 L4 interconnect
-            0x4A0DD000/12 to SR_CORE
+            0x4A0DD000/12 to SR_CORE at 0
             // 0x4A0DE000/12 L4 interconnect
             /* 0x4A0DF000-0x4A0F3FFF reserved */
-            0x4A0F4000/12 to Mailbox
+            0x4A0F4000/12 to System_Mailbox at 0
             // 0x4A0F5000/12 L4 interconnect
-            0x4A0F6000/12 to Spinlock
+            0x4A0F6000/12 to Spinlock at 0
             // 0x4A0F7000/12 L4 interconnect
             /* 0x4A0F8000/15 reserved */
-            0x4A100000/12 to SYSCTRL_PADCONF_CORE
+            0x4A100000/12 to SYSCTRL_PADCONF_CORE at 0
             // 0x4A101000/12 L4 interconnect
-            0x4A102000/12 to OCP-WP
+            0x4A102000/12 to OCP-WP at 0
             // 0x4A103000/12 L4 interconnect
             /* 0x4A104000-0x4A109FFF reserved */
-            0x4A10A000/12 to Face_detect
+            0x4A10A000/12 to FDIF at 0
             // 0x4A10B000/12 L4 interconnect
             /* 0x4A10C000-0x4A203FFF reserved */
-            0x4A204000/12 to C2C_INIT_firewall
+            0x4A204000/12 to C2C_INIT_firewall at 0
             // 0x4A205000/12 L4 interconnect
-            0x4A206000/12 to C2C_TARGET_firewall
+            0x4A206000/12 to C2C_TARGET_firewall at 0
             // 0x4A207000/12 L4 interconnect
             /* 0x4A208000/13 reserved */
-            0x4A20A000/12 to MA_firewall
+            0x4A20A000/12 to MA_firewall at 0
             // 0x4A20B000/12 L4 interconnect
-            0x4A20C000/12 to EMIF_firewall
+            0x4A20C000/12 to EMIF_firewall at 0
             // 0x4A20D000/12 L4 interconnect
             /* 0x4A20E000/13 reserved */
-            0x4A210000/12 to GPMC_firewall
+            0x4A210000/12 to GPMC_firewall at 0
             // 0x4A211000/12 L4 interconnect
-            0x4A212000/12 to OCMC_RAM_firewall
+            0x4A212000/12 to L3_OCMC_RAM_firewall at 0
             // 0x4A213000/12 L4 interconnect
-            0x4A214000/12 to GFX-T_firewall
+            0x4A214000/12 to SGX_firewall at 0
             // 0x4A215000/12 L4 interconnect
-            0x4A216000/12 to ISS-T_firewall
+            0x4A216000/12 to ISS_firewall at 0
             // 0x4A217000/12 L4 interconnect
-            0x4A218000/12 to M3-T_firewall
+            0x4A218000/12 to M3_firewall at 0
             // 0x4A219000/12 L4 interconnect
             /* 0x4A21A000/13 reserved */
-            0x4A21C000/12 to DSS-T_firewall
+            0x4A21C000/12 to DSS_firewall at 0
             // 0x4A21D000/12 L4 interconnect
-            0x4A21E000/12 to SL2-T_firewall
+            0x4A21E000/12 to SL2_firewall at 0
             // 0x4A21F000/12 L4 interconnect
-            0x4A220000/12 to IVAHD-CFG-T_firewall
+            0x4A220000/12 to IVA-HD_firewall at 0
             // 0x4A221000/12 L4 interconnect
             /* 0x4A222000/14 reserved */
-            0x4A226000/12 to L4-EMU_firewall
+            0x4A226000/12 to L4-EMU_firewall at 0
             // 0x4A227000/12 L4 interconnect
-            0x4A228000/12 to L4-ABE_firewall
+            0x4A228000/12 to L4-ABE_firewall at 0
             // 0x4A229000/12 L4 interconnect
             /* 0x4A22A000-0x4A2FFFFF reserved */
             0x4A300000/18 to L4_WKUP
@@ -223,46 +195,46 @@ L4_CFG is map [
 /*
  * 2.3.2 L4_WKUP Memory Space Mapping
  */
-SAR_RAM1 is device accept [0x4A326000/12]
-SAR_RAM2 is device accept [0x4A327000/10]
-SAR_RAM3 is device accept [0x4A328000/11]
-SAR_RAM4 is device accept [0x4A329000/10]
+SAR_RAM1 is memory accept [0/12]
+SAR_RAM2 is memory accept [0/10]
+SAR_RAM3 is memory accept [0/11]
+SAR_RAM4 is memory accept [0/10]
 
 L4_WKUP is map [
-                0x4A300000/11 to L4_WKUP_AP
-                0x4A300800/11 to L4_WKUP_LA
-                0x4A301000/12 to L4_WKUP_IP0
+                0x4A300000/11 to WKUP_AP at 0
+                0x4A300800/11 to WKUP_LA at 0
+                0x4A301000/12 to WKUP_IP0 at 0
                 /* 0x4A302000/13 reserved */
-                0x4A304000/12 to TIMER32K
+                0x4A304000/12 to S32KTIMER at 0
                 // 0x4A305000/12 L4 interconnect
-                0x4A306000/13 to PRM
+                0x4A306000/13 to PRM at 0
                 // 0x4A308000/12 L4 interconnect
                 /* 0x4A309000/12 reserved */
-                0x4A30A000/12 to SCRM
+                0x4A30A000/12 to SCRM at 0
                 // 0x4A30B000/12 L4 interconnect
-                0x4A30C000/12 to SYSCTRL_GENERAL_WKUP
+                0x4A30C000/12 to SYSCTRL_GENERAL_WKUP at 0
                 // 0x4A30D000/12 L4 interconnect
                 /* 0x4A30E000/13 reserved */
-                0x4A310000/12 to GPIO1
+                0x4A310000/12 to GPIO1 at 0
                 // 0x4A311000/12 L4 interconnect
                 /* 0x4A312000/13 reserved */
-                0x4A314000/12 to WDTIMER2
+                0x4A314000/12 to WDTIMER2 at 0
                 // 0x4A315000/12 L4 interconnect
                 /* 0x4A316000/13 reserved */
-                0x4A318000/12 to GPTIMER1
+                0x4A318000/12 to GPTIMER1 at 0
                 // 0x4A319000/12 L4 interconnect
                 /* 0x4A31A000/13 reserved (XXX: 'Module - Address space 0'?) */
-                0x4A31C000/12 to Keyboard
+                0x4A31C000/12 to Keyboard at 0
                 // 0x4A31D000/12 L4 interconnect
-                0x4A31E000/12 to SYSCTRL_PADCONF_WKUP
+                0x4A31E000/12 to SYSCTRL_PADCONF_WKUP at 0
                 // 0x4A31F000/12 L4 interconnect
                 /* 0x4A320000-0x4A325FFF reserved */
-                0x4A326000/12 to SAR_RAM1
-                0x4A327000/10 to SAR_RAM2
+                0x4A326000/12 to SAR_RAM1 at 0
+                0x4A327000/10 to SAR_RAM2 at 0
                 /* 0x4A327400-0x4A327FFF reserved */
-                0x4A328000/11 to SAR_RAM3
+                0x4A328000/11 to SAR_RAM3 at 0
                 /* 0x4A328800-0x4A328FFF reserved */
-                0x4A329000/10 to SAR_RAM4
+                0x4A329000/10 to SAR_RAM4 at 0
                 /* 0x4A329400-0x4A329FFF reserved */
                 // 0x4A32A000/12 L4 interconnect
                 /* 0x4A32B000-0x4A33FFFF reserved */
@@ -272,92 +244,92 @@ L4_WKUP is map [
  * 2.3.3 L4_PER Memory Space Mapping
  */
 L4_PER is map [
-            0x48000000/11 to L4_PER_AP
-            0x48000800/11 to L4_PER_LA
-            0x48001000/10 to L4_PER_IP0
-            0x48001400/10 to L4_PER_IP1
-            0x48001800/10 to L4_PER_IP2
-            0x48001C00/10 to L4_PER_IP3
+            0x48000000/11 to PER_AP at 0
+            0x48000800/11 to PER_LA at 0
+            0x48001000/10 to PER_IP0 at 0
+            0x48001400/10 to PER_IP1 at 0
+            0x48001800/10 to PER_IP2 at 0
+            0x48001C00/10 to PER_IP3 at 0
             /* 0x48002000-0x4801FFFF reserved */
-            0x48020000/12 to UART3
+            0x48020000/12 to UART3 at 0
             // 0x48021000/12 L4 interconnect
             /* 0x48022000/16 reserved */
-            0x48032000/12 to GPTIMER2
+            0x48032000/12 to GPTIMER2 at 0
             // 0x48033000/12 L4 interconnect
-            0x48034000/12 to GPTIMER3
+            0x48034000/12 to GPTIMER3 at 0
             // 0x48035000/12 L4 interconnect
-            0x48036000/12 to GPTIMER4
+            0x48036000/12 to GPTIMER4 at 0
             // 0x48037000/12 L4 interconnect
             /* 0x48038000-0x4803DFFF reserved */
-            0x4803E000/12 to GPTIMER9
+            0x4803E000/12 to GPTIMER9 at 0
             // 0x4803F000/12 L4 interconnect
-            0x48040000/16 to Display_subsystem
+            0x48040000/16 to Display at 0
             // 0x48050000/12 L4 interconnect
             /* 0x48051000/14 reserved */
-            0x48055000/12 to GPIO2
+            0x48055000/12 to GPIO2 at 0
             // 0x48056000/12 L4 interconnect
-            0x48057000/12 to GPIO3
+            0x48057000/12 to GPIO3 at 0
             // 0x48058000/12 L4 interconnect
-            0x48059000/12 to GPIO4
+            0x48059000/12 to GPIO4 at 0
             // 0x4805A000/12 L4 interconnect
-            0x4805B000/12 to GPIO5
+            0x4805B000/12 to GPIO5 at 0
             // 0x4805C000/12 L4 interconnect
-            0x4805D000/12 to GPIO6
+            0x4805D000/12 to GPIO6 at 0
             // 0x4805E000/12 L4 interconnect
             /* 0x4805F000/12 reserved */
-            0x48060000/12 to I2C3
+            0x48060000/12 to I2C3 at 0
             // 0x48061000/12 L4 interconnect
             /* 0x48062000/15 reserved */
-            0x4806A000/12 to UART1
+            0x4806A000/12 to UART1 at 0
             // 0x4806B000/12 L4 interconnect
-            0x4806C000/12 to UART2
+            0x4806C000/12 to UART2 at 0
             // 0x4806D000/12 L4 interconnect
-            0x4806E000/12 to UART4
+            0x4806E000/12 to UART4 at 0
             // 0x4806F000/12 L4 interconnect
-            0x48070000/12 to I2C1
+            0x48070000/12 to I2C1 at 0
             // 0x48071000/12 L4 interconnect
-            0x48072000/12 to I2C2
+            0x48072000/12 to I2C2 at 0
             // 0x48073000/12 L4 interconnect
             /* 0x48074000/13 reserved */
             0x48076000/12 to SLIMBUS2
             // 0x48077000/12 L4 interconnect
-            0x48078000/12 to ELM
+            0x48078000/12 to ELM at 0
             // 0x48079000/12 L4 interconnect
             /* 0x4807A000-0x48085FFF reserved */
-            0x48086000/12 to GPTIMER10
+            0x48086000/12 to GPTIMER10 at 0
             // 0x48087000/12 L4 interconnect
-            0x48088000/12 to GPTIMER11
+            0x48088000/12 to GPTIMER11 at 0
             // 0x48089000/12 L4 interconnect
             /* 0x4808A000-0x48095FFF reserved */
-            0x48096000/12 to McBSP4
+            0x48096000/12 to McBSP4 at 0
             // 0x48097000/12 L4 interconnect
-            0x48098000/12 to McSPI1
+            0x48098000/12 to McSPI1 at 0
             // 0x48099000/12 L4 interconnect
-            0x4809A000/12 to McSPI2
+            0x4809A000/12 to McSPI2 at 0
             // 0x4809B000/12 L4 interconnect
-            0x4809C000/12 to HSMMC1
+            0x4809C000/12 to HSMMC1 at 0
             // 0x4809D000/12 L4 interconnect
             /* 0x4809E000-0x480ACFFF reserved */
-            0x480AD000/12 to MMC_SD3
+            0x480AD000/12 to MMC_SD3 at 0
             // 0x480AE000/12 L4 interconnect
             /* 0x480AF000-0x480B1FFF reserved */
-            0x480B2000/12 to HDQ
+            0x480B2000/12 to HDQ at 0
             // 0x480B3000/12 L4 interconnect
-            0x480B4000/12 to HSMMC2
+            0x480B4000/12 to HSMMC2 at 0
             // 0x480B5000/12 L4 interconnect
             /* 0x480B6000/13 reserved */
-            0x480B8000/12 to MCSPI3
+            0x480B8000/12 to McSPI3 at 0
             // 0x480B9000/12 L4 interconnect
-            0x480BA000/12 to MCSPI4
+            0x480BA000/12 to McSPI4 at 0
             // 0x480BB000/12 L4 interconnect
             /* 0x480BC000-0x480D0FFF reserved */
-            0x480D1000/12 to MMC_SD4
+            0x480D1000/12 to MMC_SD4 at 0
             // 0x480D2000/12 L4 interconnect
             /* 0x480D3000/13 reserved */
-            0x480D5000/12 to MMC_SD5
+            0x480D5000/12 to MMC_SD5 at 0
             // 0x480D6000/12 L4 interconnect
             /* 0x480D7000-0x4834FFFF reserved */
-            0x48350000/12 to I2C4
+            0x48350000/12 to I2C4 at 0
             // 0x48351000/12 L4 interconnect
             /* 0x48352000-0x48FFFFFF reserved */
           ]
@@ -368,20 +340,19 @@ L4_PER is map [
 DMEM,
 CMEM,
 SMEM are memory accept [0/16]
-AESS_config is device accept [0/12]
 
 L4_ABE is accept [0x00000/14] // XXX: First 16KB do what?
           map [
             /* 0x04000-0x021FFF reserved */
-            0x22000/12 to McPSP1 at 0
+            0x22000/12 to McBSP1 at 0
             // 0x23000/12 L4 interconnect
-            0x24000/12 to McPSP2 at 0
+            0x24000/12 to McBSP2 at 0
             // 0x25000/12 L4 interconnect
-            0x26000/12 to McPSP3 at 0
+            0x26000/12 to McBSP3 at 0
             // 0x27000/12 L4 interconnect
-            0x28000/12 to McASP_CFG at 0
+            0x28000/12 to McASP at 0
             // 0x29000/12 L4 interconnect
-            0x2A000/12 to McASP_Data at 0
+            0x2A000/12 to McASP_DATA at 0
             // 0x2B000/12 L4 interconnect
             0x2C000/12 to SLIMBUS1 at 0
             // 0x2D000/12 L4 interconnect
@@ -410,7 +381,7 @@ L4_ABE is accept [0x00000/14] // XXX: First 16KB do what?
             0xC0000/16 to SMEM at 0
             // 0xD0000/12 L4 interconnect
             /* 0xD1000/17 reserved */
-            0xF1000/12 to ASS_config at 0
+            0xF1000/12 to AESS at 0
             // 0xF2000/12 L4 interconnect
             /* 0xF3000-0xFFFFF reserved */
           ]
@@ -422,14 +393,14 @@ M3_ROM is memory accept [0/14]
 M3_RAM is memory accept [0/16]
 
 // TODO: address space not accessible from L3
-
-M3_subsystem is map [
-                    0x55000000/14 to M3_ROM
-                    0x55020000/16 to M3_RAM
+M3 is map [
+                    0x00000000-0x54FFFFFF to L3
+                    0x55000000/14 to M3_ROM at 0
+                    0x55020000/16 to M3_RAM at 0
                     /* 0x55030000/16 reserved */
-                    0x55040000/18 to M3_ISS
-                    0x55080000/12 to M3_MMU_config
-                    0x55081000/12 to M3_WKUGEN
+                    0x55040000/18 to ISS at 0x10000 // XXX: Not accessible from L3?
+                    0x55080000/12 to M3_MMU
+                    0x55081000/12 to M3_WUGEN
                     /* 0x55082000-0x55FFFFFF reserved */
                     0x56000000/25 to L3
                 ]
@@ -437,25 +408,74 @@ M3_subsystem is map [
 /*
  * 2.5 DSP Subsystem Memory Space Mapping
  */
-
  // TODO: address space not accessible from L4_CFG
- DSP_subsystem is map [
-                    0x01C20000/12 to SYSC
-                  ]
+ DSP is map [
+            0x01C20000/12 to SYSC
+        ]
 
 /*
  * 2.6 Display Subsystem Memory Space Mapping
  */
-Display_subsystem is map [
+Display is map [
+                // 0x0000/12 Display subsystem registers
+                0x1000/12 to DISPC
+                0x2000/12 to RFBI
+                0x3000/12 to VENC
+                0x4000/12 to DSI1
+                0x5000/12 to DSI2
+                0x6000/12 to HDMI
+                0x7000/12 to HDCP
+           ]
 
 /*
  * 3 Power, Reset and Clock Management
  */
-PRM is device accept [0x4A306000/13]
-SCRM is device accept [0x4A30A000/12]
-SR_MPU is device accept [0x4A0D900/8]
-SR_IVA is device accept [0x4A0DB000/8]
-SR_CORE is device accept [0x4A0DD00/8]
+INTRCONN_SOCKET_PRM is device accept [0/8]
+CKGEN_PRM is device accept [0/8]
+MPU_PRM is device accept [0/8]
+DSP_PRM is device accept [0/8]
+ABE_PRM is device accept [0/8]
+ALWAYS_ON_PRM is device accept [0/8]
+CORE_PRM is device accept [0/11]
+IVAHD_PRM is device accept [0/8]
+CAM_PRM is device accept [0/8]
+DSS_PRM is device accept [0/8]
+SGX_PRM is device accept [0/8]
+L3INIT_PRM is device accept [0/8]
+L4PER_PRM is device accept [0/9]
+WKUP_PRM is device accept [0/8]
+WKUP_CM is device accept [0/8]
+EMU_PRM is device accept [0/8]
+EMU_CM is device accept [0/8]
+DEVICE_PRM is device accept [0/8]
+INSTR_PRM is device accept [0/8]
+PRM is map [
+            0x0000/8 to INTRCONN_SOCKET_PRM at 0
+            0x0100/8 to CKGEN_PRM at 0
+            0x0300/8 to MPU_PRM at 0
+            0x0400/8 to DSP_PRM at 0
+            0x0500/8 to ABE_PRM at 0
+            0x0600/8 to ALWAYS_ON_PRM at 0
+            0x0700/11 to CORE_PRM at 0
+            0x0F00/8 to IVAHD_PRM at 0
+            0x1000/8 to CAM_PRM
+            0x1100/8 to DSS_PRM
+            0x1200/8 to SGX_PRM
+            0x1300/8 to L3INIT_PRM
+            0x1400/9 to L4PER_PRM
+            0x1700/8 to WKUP_PRM
+            0x1800/8 to WKUP_CM
+            0x1900/8 to EMU_PRM
+            0x1A00/8 to EMU_CM
+            0x1B00/8 to DEVICE_PRM
+            0x1F00/8 to INSTR_PRM
+       ]
+
+SCRM is device accept [0/12]
+
+SR_MPU is device accept [0/8]
+SR_IVA is device accept [0/8]
+SR_CORE is device accept [0/8]
 
 /*
  * 4 Dual Cortex-A9 MPU Subsystem
@@ -486,7 +506,7 @@ TPTC1 are device accept [0/10]
 SYSC is device accept [0/12]
 WUGEN is device accept [0/12]
 L1_SCACHE,
-L2_SCACHE are device [0/8]
+L2_SCACHE are device accept [0/8]
 SCACHE_SCTM is device accept [0/9]
 SCACHE_MMU is device accept [0/11]
 
@@ -498,7 +518,6 @@ SYSCTRL is device accept [0/10]
 /*
  * 7 Dual Cortex-M3 MPU Subsystem
  */
-M3_MMU is device accept [0/12]
 M3_WUGEN is device accept [0/12]
 
 /*
@@ -522,7 +541,13 @@ FDIF is device accept [0/12]
 /*
  * 10 Display Subsystem
  */
-// TODO
+DISPC,
+RFBI,
+VENC,
+DSI1,
+DSI2,
+HDMI,
+HDCP are device accept [0/12]
 
 /*
  * 11 2D/3D Graphics Accelerator
@@ -530,15 +555,21 @@ FDIF is device accept [0/12]
 SGX is device accept [0/25]
 
 /*
+ * 12 Audio Backend
+ */
+AESS is device accept [0/12]
+
+/*
  * 13 Interconnect
  */
 /* 13.2 L3 Interconnect */
+L3_config is device accept [0/26]
 C2C_INIT_firewall is device accept [0/12] // not in TRM, from omap44xx_map.h
 C2C_TARGET_FIREWALL is device accept [0/12] // not in TRM, from omap44xx_map.h
 MA_firewall is device accept[0/12]
 EMIF_firewall is device accept [0/12]
 GPMC_firewall is device accept [0/12]
-L3_RAM_firewall is device accept [0/12]
+L3_OCMC_RAM_firewall is device accept [0/12]
 SGX_firewall is device accept [0/12]
 ISS_firewall is device accept [0/12]
 M3_firewall is device accept [0/12]
@@ -556,9 +587,9 @@ PER_IP1 is device accept [0/10]
 PER_IP2 is device accept [0/10]
 PER_IP3 is device accept [0/10]
 
-L4_CFG_AP is device accept [0/11]
-L4_CFG_LA is device accept [0/11]
-L4_CFG_IP0 is device accept [0/12]
+CFG_AP is device accept [0/11]
+CFG_LA is device accept [0/11]
+CFG_IP0 is device accept [0/12]
 
 WKUP_AP is device accept [0/11]
 WKUP_LA is device accept [0/11]
@@ -605,29 +636,29 @@ M3_MMU,
 DSP_MMU are device accept [0/12]
 
 /*
- * 21 Spinnlock
+ * 21 Spinlock
  */
-Spinnlock is device accept [0/12]
+Spinlock is device accept [0/12]
 
 /*
  * 22 Timers
  */
 /* 22.2 General Purpose Timers */
-GPTIMER1
-GPTIMER2
-GPTIMER3
-GPTIMER4
-GPTIMER5
-GPTIMER6
-GPTIMER7
-GPTIMER8
-GPTIMER9
-GPTIMER10
+GPTIMER1,
+GPTIMER2,
+GPTIMER3,
+GPTIMER4,
+GPTIMER5,
+GPTIMER6,
+GPTIMER7,
+GPTIMER8,
+GPTIMER9,
+GPTIMER10,
 GPTIMER11 are device accept [0/12]
 
 /* 22.3 Watchdog Timers */
 WDTIMER2,
-WDTIMER3 is device accept [0/12]
+WDTIMER3 are device accept [0/12]
 
 /* 22.4 32-KHz Synchronized Timer */
 S32KTIMER is device accept [0/12]
@@ -671,19 +702,25 @@ DMIC is device accept [0/12]
 
 /* 23.8 Multichannel Audio Serial Port */
 McASP is device accept [0/12]
+McASP_DATA is device accept [0/12]
 
 /* 23.9 Serial Low-Power Inter-Chip Media Bus Controller */
 SLIMBUS1,
 SLIMBUS2 are device accept [0/12]
 
 /* 23.10 MIPI-HSI */
-HSI_TOP is device accept [0/12]
-HSI_DMA is device accept [0/11]
-HSI_PORT1 is device accept [0/12]
-HSI_PORT2 is device accept [0/12]
+HSI_TOP is device accept [0-0x1400]
+HSI_DMA_CHANNELS is device accept [0/10]
+HSI_PORTS is device accept [0/13]
+
+HSI is map [
+        0x0000-0x1400 to HSI_TOP
+        0x1800/10 to HSI_DMA_CHANNELS
+        0x000/13 to HSI_PORTS
+       ]
 
 /* 23.11 High-Speed Multiport USB Host Subsystem */
-USBTLLHS is device accept [0/12]
+HSUSBTLL is device accept [0/12]
 HSUSBHOST is device accept [0/12]
 
 /* 23.12 High-Speed USB OTG Controller */
@@ -691,7 +728,7 @@ HSUSBOTG is device accept [0/12]
 USBPHY is device accept [0/12]
 
 /* 23.13 Full-speed USB Host Controller */
-USBFSHOST is device accept[0/12]
+FSUSBHOST is device accept[0/12]
 
 /*
  * 24 MMC/SD/SDIO
@@ -715,4 +752,30 @@ GPIO6 are device accept [0/12]
 /*
  * 26 Keyboard Controller
  */
-Keyboard is device accept [0/12]
\ No newline at end of file
+Keyboard is device accept [0/12]
+
+/*
+ * 28.10 On-Chip Debug Support Memory Mapping
+ */
+MIPI_STM_0 is device accept [0/20]
+MIPI_STM_1 is device accept [0/18]
+A9_CPU0_debug_PMU is device accept [0/13]
+A9_CPU1_debug_PMU is device accept [0/13]
+CTI0 is device accept [0/12]
+CTI1 is device accept [0/12]
+PTM0 is device accept [0/12]
+PTM1 is device accept [0/12]
+A9_CS-TF is device accept [0/12]
+DAP_PC is device accept [0/12]
+APB is device accept [0/12]
+DRM is device accept [0/12]
+MIPI_STM is device accept [0/12]
+CS-ETB is device accept [0x54162000/12]
+CS-TPIU is device accept [0x54163000/12]
+CS-TF is device accept [0x54164000/12]
+
+CM1 is device accept [0x4A004000/12]
+CM2 is device accept [0x4A008000/12]
+OCP-WP is device accept [0x4A102000/12]
+
+PMI is device accept [0/8]
\ No newline at end of file