"arm_icp_pic0",
"arm_icp_pit",
"cpuid",
- "crb_sif",
- "eMAC",
"ht_config",
"lpc_ioapic",
"lpc_timer",
"pci_hdr0",
"pci_hdr0_mem",
"pci_hdr1",
- "pl011_uart",
- "rck"
+ "pl011_uart"
], arch <- allArchitectures
]
+++ /dev/null
-/*
- * Copyright (c) 2008, 2009, 2010, ETH Zurich. All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-/*
- * crb_sif.dev
- *
- * DESCRIPTION: RockCreek Copperridge System Interface
- */
-
-device crb_sif lsbfirst (addr base) "RockCreek Copperridge System Interface" {
- register dcsr1 ro addr(base, 0x0) "Device Control Status" {
- _ 8;
- buildversion 8 "Build version";
- datapathwidth 8 "Data path width";
- fpgafamily 8 "FPGA Family";
- };
-
- register ddmacr ro addr(base, 0x4) "Device DMA Control Status" type(uint32);
- register wdmatlpa ro addr(base, 0x8) "Write DMA TLP Address" type(uint32);
- register wdmatlps ro addr(base, 0xc) "Write DMA TLP Size" type(uint32);
- register wdmatlpc ro addr(base, 0x10) "Write DMA TLP Count" type(uint32);
- register wdmatlpp ro addr(base, 0x14) "Write DMA TLP Data Pattern" type(uint32);
- register rdmatlpp ro addr(base, 0x18) "Read DMA TLP Expected Pattern" type(uint32);
- register rdmatlpa ro addr(base, 0x1c) "Read DMA TLP Address" type(uint32);
- register rdmatlps ro addr(base, 0x20) "Read DMA TLP Size" type(uint32);
- register rdmatlpc ro addr(base, 0x24) "Read DMA TLP Count" type(uint32);
- register wdmaperf ro addr(base, 0x28) "Write DMA Performance" type(uint32);
- register rdmaperf ro addr(base, 0x2c) "Read DMA Performance" type(uint32);
- register rdmastat ro addr(base, 0x30) "Read DMA Status" type(uint32);
- register nrdcomp ro addr(base, 0x34) "Number of Rad Completion w/ data" type(uint32);
- register rcompdsizw ro addr(base, 0x38) "Read Completion Data Size" type(uint32);
-
- register dlwstat ro addr(base, 0x3c) "Device Link Width Status" {
- capmaxwidth 6 "cap. max width";
- _ 2;
- negmaxwidth 6 "neg. max width";
- _ 18;
- };
-
- register dltrsstat ro addr(base, 0x40) "Device Link Transaction Size Status" {
- capmaxsize 3 "cap. max size";
- _ 5;
- progmaxsize 3 "prog. max size";
- _ 5;
- maxrdreqsize 3 "max. rd req size";
- _ 13;
- };
-
- register dmisccont ro addr(base, 0x44) "Device Miscellaneous Control" type(uint32);
-
- register id0 ro addr(base, 0x300) "BitSID" type(uint32);
- register id1 rw addr(base, 0x304) "GRBTest" type(uint32);
- register id2 rw addr(base, 0x308) "GRBTest" type(uint32);
-
- register trnct0 ro addr(base, 0x30c) "BAR Win 0" type(uint32);
- register trnct1 ro addr(base, 0x310) "BAR Win 1" type(uint32);
- register trnct2 ro addr(base, 0x314) "BAR Win 2" type(uint32);
- register trnct3 ro addr(base, 0x318) "BAR Win 3" type(uint32);
-
- register trnct4 ro addr(base, 0x31c) "MIP/MOP" {
- mopfifolvl 15 "MOP FIFO level";
- moperror 1 "MOP Error";
- mipfifolvl 15 "MIP FIFO level";
- miperror 1 "MIP Error";
- };
-
- register trnct5 ro addr(base, 0x320) "Init" {
- init 1 "Init";
- trncte 1 "TRNCTE";
- _ 30;
- };
-
- register config ro addr(base, 0x324) "Config" {
- softreset 1 "Soft reset";
- gen_memcomp 1 "Gen Memcomp";
- drop_memcomp 1 "Drop Memcomp";
- rcinitdone 1 "RC init done";
- _ 28;
- };
-
- register debug ro addr(base, 0x328) "Debug" {
- mipdisablerd 1 "MIP disable RD";
- scemiloopback 1 "SCEMI loopback";
- miprdtrig 1 "MIP rd trig";
- _ 29;
- };
-
- register scemidata0 ro addr(base, 0x32c) type(uint32);
- register scemidata1 ro addr(base, 0x330) type(uint32);
-};
+++ /dev/null
-/*
- * Copyright (c) 2008, ETH Zurich. All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-/*
- * eMAC.dev
- *
- * DESCRIPTION: IP blocks from Xilinx. Used as NIC in SCC board.
- *
- * Numbers in comments refer to the
- * -
- * - sccKit140_UsersGuide_Part8.pdf (By default, all numbers are from this doc)
- * https://wiki.netos.ethz.ch/BarrelFish/HWInfo?action=AttachFile&do=get&target=sccKit140_UsersGuide_Part8.pdf
- * - Xlinx eMAC user guide.pdf (When referred as "Xilinx user guide")
- * https://wiki.netos.ethz.ch/BarrelFish/HWInfo?action=AttachFile&do=get&target=Xlinx+eMAC+user+guide.pdf
- */
-
-device eMAC lsbfirst ( addr base ) "Xilinx IPblock" {
-/* Using MSB as it was used in rck.dev */
-/* FIXME: Either use absolute values 0x07000 or relative values 0x00000.
- Find out which way is correct, and use it. */
-/* FIXME: Separate the definations in register and regtype */
-
- space one_byte(idx) valuewise "Model specific register";
-
- /******** IP Configuration registers *********/
-
- /* Receiver Configuration(0) [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-2: Receiver Configuration Register (Word 0) */
- regtype eMAC_receiver_conf_0 "Flow control Configuration register (0)" {
- PAUSE_FRAME_ADDR_LOW 32 rw "Pause Frame Ethernet MAC Address [31:0]. This address is used to match the Ethernet MAC against the destination address of any incoming flow control frames. It is also used by the flow control block as the source address for any outbound flow control frames. The address is ordered so the first byte transmitted/received is the lowest positioned byte in the register; for example, a MAC address of AA-BB-CC-DD-EE-FF is stored in address [47:0] as 0xFFEEDDCCBBAA.";
- };
-
-
- /* Receiver Configuration(1) [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-3: Receiver Configuration Register (Word 1) */
- regtype eMAC_receiver_conf_1 "Flow control Configuration register (1)" {
- PAUSE_FRAME_ADDR_LOW 16 rw "Pause frame Ethernet MAC Address [47:32].";
- _ 9 mbz "Reserved";
- LT_DIS 1 rw "Length/Type Check disable. When this bit is 1, it disables the Length/Type field check on the frame.";
- HD 1 rw "Half-duplex mode. When this bit is 1, the receiver operates in half-duplex mode. When the bit is 0, the receiver operates in full-duplex mode.";
- VLAN 1 rw "VLAN enable. When this bit is 1, the receiver accepts VLAN tagged frames. The maximum payload length increases by four bytes.";
- RX 1 rw "Receive enable. When this bit is 1, the receiver block is enabled to operate. When the bit is 0, the receiver ignores activity on the physical interface receive port.";
- FCS 1 rw "In-band FCS enable. When this bit is 1, the receiver passes the FCS field up to the client. When this bit is 0, the FCS field is not passed to the client. In either case, the FCS is verified on the frame.";
- JUM 1 rw "Jumbo frame enable. When this bit is 1, the Ethernet MAC receiver accepts frames over the maximum length specified in IEEE Std 802.3-2002 specification. When this bit is 0, the receiver only accepts frames up to the specified maximum.";
- RST 1 rw "Reset. When this bit is 1, the receiver is reset. The bit automatically reverts to 0. This reset also sets all of the receiver configuration registers to their default values.";
- };
-
-
- /* Transmiter configuration [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-4: Transmiter Configuration register */
- regtype eMAC_transmiter_conf "eMAC Transmiter Configuration register" {
- _ 25 mbz "Reserved";
- IFG 1 rw "IFG adjustment enable. When this bit is 1, the transmitter reads the value of CLIENTEMAC#TXIFGDELAY at the start of frame transmission and adjusts the IFG.";
- HD 1 rw "Half-duplex mode (applicable in 10/100 Mb/s mode only). When this bit is 1, the transmitter operates in half-duplex mode. When this bit is 0, the transmitter operates in full-duplex mode.";
- VLAN 1 rw "VLAN enable. When this bit is 1, the transmitter allows transmission of the VLAN tagged frames.";
- TX 1 rw "Transmit enable. When this bit is 1, the transmitter is enabled for operation.";
- FCS 1 rw "In-band FCS enable. When this bit is 1, the Ethernet MAC transmitter is ready for the FCS field from the client.";
- JUM 1 rw "Jumbo frame enable. When this bit is 1, the transmitter sends frames greater than the maximum length specified in IEEE Std 802.3-2002. When this bit is 0, it only sends frames less than the specified maximum length.";
- RST 1 rw "Reset. When this bit is 1, the transmitter is reset. The bit automatically reverts to 0. This reset also sets all of the transmitter configuration registers to their default values.";
-
- };
-
- /* Flow control configuration [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-5: Flow control Configuration register */
- regtype eMAC_flow_control_conf "Flow control Configuration register" {
- _ 29 mbz "Reserved";
- RX_FC_enable 1 rw "Flow control enable (RX). When this bit is 1, the received flow control frames inhibit transmitter operation. When this bit is 0, the flow control frame is passed to the client.";
- TX_FC_enable 1 rw "Flow control enable (TX). When this bit is 1, the CLIENTEMAC#PAUSEREQ signal is asserted and a flow control frame is sent from the transmitter. When this bit is 0, the CLIENTEMAC#PAUSEREQ signal has no effect.";
- _ 1 mbz "Reserved";
- };
-
- /* Ethernet MAC mode [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-6: Ethernet MAC Mode Configuration Register */
- /* Attributes to Configure Fixed Mode for the Ethernet MAC */
- regtype eMAC_ethernet_mac_conf "Ethernet MAC Mode Configuration register" {
- _ 24 mbz "Reserved";
- RX16 1 ro "Receive 16-bit Client Interface enable. When this bit is 1, the receive data client interface is 16 bits wide. When this bit is 0, the receive data client interface is 8 bits wide. This bit is valid only when using 1000BASE-X PCS/PMA mode.";
- TX16 1 ro "Transmit 16-bit Client Interface enable. When this bit is 1, the transmit data client interface is 16 bits wide. When this bit is 0, the transmit data client interface is 8 bits wide. This bit is valid only when using 1000BASE-X PCS/PMA mode.";
- HOST 1 ro "Host Interface enable. When this bit is 1, the host interface is enabled. When this bit is 0, the host interface is disabled.";
- GPCS 1 ro "1000BASE-X mode enable. When this bit is 1, the Ethernet MAC is configured in 1000BASE-X mode.";
- SGMII 1 ro "SGMII mode enable. When this bit is 1, the Ethernet MAC is configured in SGMII mode.";
- RGMII 1 ro "RGMII mode enable. When this bit is 1, the Ethernet MAC is configured in RGMII mode.";
- LINK_SPEED 2 rw "Speed selection. The speed of the Ethernet MAC is defined by the following values: 10 = 1000 Mb/s, 01 = 100 Mb/s, 00 = 10 Mb/s, 11 = N/A";
- };
-
-
- /* Address Filter Mode [31:0] R/W (see Xilinx eMAC user guide) */
- /* Xilinx user guide: Table 4-13: Address Filter Mode */
- regtype eMAC_address_filter_mode "Address filter mode Configuration register" {
- _ 31 mbz "Reserved";
- PM 1 rw "Promiscuous Mode enable. When this bit is 1, the Address Filter block is disabled. When this bit is 0, the Address Filter block is enabled.";
- };
-
-
- /******* eMAC status registers ******/
-
- regtype RX_frame_dropped "RX Frame Dropped Channel" {
- status 1 rw "Set when frame dropped due to RX buffer overflow in DDR3";
- _ 31 mbz "Unused";
- };
-
- regtype TX_FIFO_buff_full "TX FIFO buffer full" {
- status 1 ro "Set in case of an overflow of TX fifo buffer in eMAC IP block";
- _ 31 mbz "Unused";
- };
-
- regtype RX_FIFO_buff_full "RX FIFO buffer full" {
- status 1 ro "Set in case of an overflow of RX fifo buffer in eMAC IP block";
- _ 31 mbz "Unused";
- };
-
- regtype TX_EMAC_Not_Ready "TX EMAC not ready" {
- status 1 ro "eMAC does not accept frames";
- _ 31 mbz "Unused";
- };
-
- regtype RX_MAC_Addr_Err "RX MAC address error" {
- status 1 ro "MAC address not found in table";
- _ 31 mbz "Unused";
- };
-
- regtype RX_MAC_Lower "RX MAC address lower part" {
- mac_low 32 ro "Lower 32 bits of MAC address that has not been found";
- };
-
- regtype RX_MAC_Higher "RX MAC address higher part" {
- mac_high 16 ro "Upper 16 bits of MAC address that has not been found";
- _ 16 mbz "Unused"; // FIXME: Should these 16 bits be commented? as they were not mentioned in the doc
- };
-
-
-
- /***** eMAC General Configuration Registers ********/
-
- regtype eMAC_MAC_base_addr_upper "eMAC config MAC base address (high)" {
- mac_upper 16 rw "Upper 16 bits of base MAC address";
- _ 16 mbz "Unused";
- };
-
- regtype eMAC_MAC_base_addr_lower "eMAC config MAC base address (low)" {
- mac_lower 32 rw "Lower 32 bits of base MAC address";
- };
-
- regtype eMAC_start_IP_SCC_network "eMAC config Start IP Address of SCC network" {
- ip 32 rw "IP Address for SCC Core 0. IPs for other cores are assigned in order";
- };
-
- regtype eMAC_host_IP_addr "eMAC config Host IP Address" {
- ip 32 rw "IP Address of Host computer where /shared is mounted";
- };
-
- regtype eMAC_host_GW_addr "eMAC config Host gateway Address" {
- ip 32 rw "Gateway of Host computer";
- };
-
-
- /****** Registers for "RX Control Registers" ******/
- regtype RX_Buffer_start_addr "RX control RX Buffer Start Address" {
- ADDR 29 rw "Upper 29 bit of physical start address [33:5] of memory buffer. Lower 5 bits are always 0 because access granularity to buffer will be always 32 bytes - one cache-line.";
- _ 3 mbz "Unused";
- };
-
- regtype RX_Buffer_read_index "RX control RX Buffer Read Index" {
- rid 16 rw "Read index of RX buffer Points to 32 byte entry in the buffer.";
- _ 16 mbz "Unused";
- };
-
- regtype RX_Buffer_write_index "RX control RX Buffer Write Index" {
- wid 16 ro "Write index of RX buffer Points to 32 byte entry in the buffer.";
- _ 16 mbz "Unused";
- };
-
- regtype RX_Buffer_last_index "RX control RX Buffer Last Index" {
- lid 16 rw "Last valid index in buffer. .Buffer size = last index * 32 bytes";
- _ 16 mbz "Unused";
- };
-/*
- regtype RX_Buffer_reserved "RX control reserved" {
- _ 32 mbz "Unused";
- };
-*/
-
- regtype RX_routing "RX control RX routing related" {
- broute 8 rw "Route to the tile where the MC for this buffer is located";
- bdest 3 rw "Defines the port at which the MC is connected";
- _ 5 mbz "Unused";
- iroute 8 rw "Route to the tile where the core for this buffer is located";
- idest 3 rw "Selects core 0 or core 1 in the tile";
- _ 5 mbz "Unused";
- };
-
-
- regtype RX_net_port_MAC_high "RX Network Port MAC Address (high)" {
- mac_hi 16 rw "Higher 16 bits of MAC addresses";
- _ 16 mbz "Unused";
- };
-
- regtype RX_net_port_MAC_low "RX Network Port MAC Address (low)" {
- mac_lo 32 rw "Lower 32 bits of MAC addresses";
- };
-
- regtype RX_net_port_enable "RX Network Port Enable" {
- enable 1 rw "1 - Enabled, 0 - Disabled";
- _ 31 mbz "Unused";
- };
-
-
-
- /****** register types for TX control registers *******/
-
-
- regtype TX_Buffer_start_addr "TX control TX Buffer Start Address" {
- ADDR 29 rw "Upper 29 bit of physical start address [33:5] of memory buffer. Lower 5 bits are always 0 because access granularity to buffer will be always 32 bytes - one cache-line.";
- _ 3 mbz "Unused";
- };
-
-
- regtype TX_Buffer_read_index "TX control TX Buffer Read Index" {
- rid 16 ro "Read index of TX buffer Points to 32 byte entry in the buffer.";
- _ 16 mbz "Unused";
- };
-
-
- regtype TX_Buffer_write_index "TX control TX Buffer Write Index" {
- wid 16 rw "Write index of TX buffer Points to 32 byte entry in the buffer.";
- _ 16 mbz "Unused";
- };
-
- regtype TX_Buffer_last_index "TX control TX Buffer Last Index" {
- lid 16 rw "Last valid index in buffer. .Buffer size = last index * 32 bytes";
- _ 16 mbz "Unused";
- };
-
-
- regtype TX_routing "TX control RX routing related" {
- broute 8 rw "Route to the tile where the MC for this buffer is located";
- bdest 3 rw "Defines the port at which the MC is connected";
- _ 21 mbz "Unused";
- };
-
-
- regtype TX_net_port_enable "TX Network Port Enable" {
- enable 1 rw "1 - Enabled, 0 - Disabled";
- _ 31 mbz "Unused";
- };
-
-
-
- /* 8.3.5.1 eMAC#0 IP Configuration Registers (03200 to 03390) */
- register eMAC0_receiver_conf_0 addr(base, 0x03200) type(eMAC_receiver_conf_0);
- register eMAC0_receiver_conf_1 addr(base, 0x03240) type(eMAC_receiver_conf_1);
- register eMAC0_transmiter_conf addr(base, 0x03280) type(eMAC_transmiter_conf);
- register eMAC0_flow_control_conf addr(base, 0x032C0) type(eMAC_flow_control_conf);
- register eMAC0_ethernet_mac_conf addr(base, 0x03300) type(eMAC_ethernet_mac_conf);
- register eMAC0_address_filter_mode addr(base, 0x03900) type(eMAC_address_filter_mode);
-
-
- /* 8.3.5.3 eMAC#1 IP Configuration Register (04200 to 04390) */
- register eMAC1_receiver_conf_0 addr(base, 0x04200) type(eMAC_receiver_conf_0);
- register eMAC1_receiver_conf_1 addr(base, 0x04240) type(eMAC_receiver_conf_1);
- register eMAC1_transmiter_conf addr(base, 0x04280) type(eMAC_transmiter_conf);
- register eMAC1_flow_control_conf addr(base, 0x042C0) type(eMAC_flow_control_conf);
- register eMAC1_ethernet_mac_conf addr(base, 0x04300) type(eMAC_ethernet_mac_conf);
- register eMAC1_address_filter_mode addr(base, 0x04900) type(eMAC_address_filter_mode);
-
-
- /* 8.3.5.5 eMAC#2 IP Configuration Registers (05200 to 05390) */
- register eMAC2_receiver_conf_0 addr(base, 0x05200) type(eMAC_receiver_conf_0);
- register eMAC2_receiver_conf_1 addr(base, 0x05240) type(eMAC_receiver_conf_1);
- register eMAC2_transmiter_conf addr(base, 0x05280) type(eMAC_transmiter_conf);
- register eMAC2_flow_control_conf addr(base, 0x052C0) type(eMAC_flow_control_conf);
- register eMAC2_ethernet_mac_conf addr(base, 0x05300) type(eMAC_ethernet_mac_conf);
- register eMAC2_address_filter_mode addr(base, 0x05900) type(eMAC_address_filter_mode);
-
-
- /* 8.3.5.7 eMAC#3 IP Configuration Registers (06200 to 06390) */
- register eMAC3_receiver_conf_0 addr(base, 0x06200) type(eMAC_receiver_conf_0);
- register eMAC3_receiver_conf_1 addr(base, 0x06240) type(eMAC_receiver_conf_1);
- register eMAC3_transmiter_conf addr(base, 0x06280) type(eMAC_transmiter_conf);
- register eMAC3_flow_control_conf addr(base, 0x062C0) type(eMAC_flow_control_conf);
- register eMAC3_ethernet_mac_conf addr(base, 0x06300) type(eMAC_ethernet_mac_conf);
- register eMAC3_address_filter_mode addr(base, 0x06900) type(eMAC_address_filter_mode);
-
-
- /* 8.3.6.1 eMAC#0 status registers (0x07000 to 0x07044) */
-// register eMAC0_RX_frame_dropped addr(base, 0x00000) type(RX_frame_dropped);
-// register eMAC0_RX_frame_dropped one_byte(0x00000) type(RX_frame_dropped);
- regarray eMAC0_RX_frame_dropped one_byte( 0x07000)[47] type(RX_frame_dropped);
- register eMAC0_TX_FIFO_BUFF_FULL addr(base, 0x07030) type(TX_FIFO_buff_full);
- register eMAC0_RX_FIFO_BUFF_FULL addr(base, 0x07034) type(RX_FIFO_buff_full);
- register eMAC0_TX_EMAC_NOT_READY addr(base, 0x07038) type(TX_EMAC_Not_Ready);
- register eMAC0_RX_MAC_ADDR_ERR addr(base, 0x0703C) type(RX_MAC_Addr_Err);
- register eMAC0_RX_MAC_LOWER addr(base, 0x07040) type(RX_MAC_Lower);
- register eMAC0_RX_MAC_HIGHER addr(base, 0x07044) type(RX_MAC_Higher);
-
- /* 8.3.6.2 eMAC#1 status registers (0x07100 to 0x07144) */
- regarray eMAC1_RX_frame_dropped one_byte( 0x07100)[47] type(RX_frame_dropped);
- register eMAC1_TX_FIFO_BUFF_FULL addr(base, 0x07130) type(TX_FIFO_buff_full);
- register eMAC1_RX_FIFO_BUFF_FULL addr(base, 0x07134) type(RX_FIFO_buff_full);
- register eMAC1_TX_EMAC_NOT_READY addr(base, 0x07138) type(TX_EMAC_Not_Ready);
- register eMAC1_RX_MAC_ADDR_ERR addr(base, 0x0713C) type(RX_MAC_Addr_Err);
- register eMAC1_RX_MAC_LOWER addr(base, 0x07140) type(RX_MAC_Lower);
- register eMAC1_RX_MAC_HIGHER addr(base, 0x07144) type(RX_MAC_Higher);
-
- /* 8.3.6.3 eMAC#2 status registers (0x07200 to 0x07244) */
- regarray eMAC2_RX_frame_dropped one_byte( 0x07200)[47] type(RX_frame_dropped);
- register eMAC2_TX_FIFO_BUFF_FULL addr(base, 0x07230) type(TX_FIFO_buff_full);
- register eMAC2_RX_FIFO_BUFF_FULL addr(base, 0x07234) type(RX_FIFO_buff_full);
- register eMAC2_TX_EMAC_NOT_READY addr(base, 0x07238) type(TX_EMAC_Not_Ready);
- register eMAC2_RX_MAC_ADDR_ERR addr(base, 0x0723C) type(RX_MAC_Addr_Err);
- register eMAC2_RX_MAC_LOWER addr(base, 0x07240) type(RX_MAC_Lower);
- register eMAC2_RX_MAC_HIGHER addr(base, 0x07244) type(RX_MAC_Higher);
-
- /* 8.3.6.4 eMAC#3 status registers (0x07300 to 0x07344) */
- regarray eMAC3_RX_frame_dropped one_byte( 0x07300)[47] type(RX_frame_dropped);
- register eMAC3_TX_FIFO_BUFF_FULL addr(base, 0x07330) type(TX_FIFO_buff_full);
- register eMAC3_RX_FIFO_BUFF_FULL addr(base, 0x07334) type(RX_FIFO_buff_full);
- register eMAC3_TX_EMAC_NOT_READY addr(base, 0x07338) type(TX_EMAC_Not_Ready);
- register eMAC3_RX_MAC_ADDR_ERR addr(base, 0x0733C) type(RX_MAC_Addr_Err);
- register eMAC3_RX_MAC_LOWER addr(base, 0x07340) type(RX_MAC_Lower);
- register eMAC3_RX_MAC_HIGHER addr(base, 0x07344) type(RX_MAC_Higher);
-
- /* 8.3.6.5 eMAC General Configuration Registers (0x07e00 to 0x07e10) */
- register eMAC_MAC_base_addr_upper_reg addr(base, 0x07e00) type(eMAC_MAC_base_addr_upper);
- register eMAC_MAC_base_addr_lower_reg addr(base, 0x07e04) type(eMAC_MAC_base_addr_lower);
- register eMAC_start_IP_SCC_network_reg addr(base, 0x07e08) type(eMAC_start_IP_SCC_network);
- register eMAC_host_IP_addr_reg addr(base, 0x07e0c) type(eMAC_host_IP_addr);
- register eMAC_host_GW_addr_reg addr(base, 0x07e10) type(eMAC_host_GW_addr);
-
-
- /* 8.3.6.6 eMAC#0 RX Control Registers (09000 to 098BC) */
- regarray eMAC0_RX_Buffer_start_addr addr(base, 0x09000)[48] type(RX_Buffer_start_addr);
- regarray eMAC0_RX_Buffer_read_index addr(base, 0x09100)[48] type(RX_Buffer_read_index);
- regarray eMAC0_RX_Buffer_write_index addr(base, 0x09200)[48] type(RX_Buffer_write_index);
- regarray eMAC0_RX_Buffer_last_index addr(base, 0x09300)[48] type(RX_Buffer_last_index);
-// regarray eMAC0_RX_Buffer_reserved addr(base, 0x09400)[48] type(RX_Buffer_reserved);
- regarray eMAC0_RX_routing addr(base, 0x09500)[48] type(RX_routing);
- regarray eMAC0_RX_net_port_MAC_high addr(base, 0x09600)[48] type(RX_net_port_MAC_high);
- regarray eMAC0_RX_net_port_MAC_low addr(base, 0x09700)[48] type(RX_net_port_MAC_low);
- regarray eMAC0_RX_net_port_enable addr(base, 0x09800)[48] type(RX_net_port_enable);
-
-
- /* 8.3.6.7 eMAC#0 TX Control Registers (09900 to 09EBC) */
- regarray eMAC0_TX_Buffer_start_addr addr(base, 0x09900)[48] type(TX_Buffer_start_addr);
- regarray eMAC0_TX_Buffer_read_index addr(base, 0x09A00)[48] type(TX_Buffer_read_index);
- regarray eMAC0_TX_Buffer_write_index addr(base, 0x09B00)[48] type(TX_Buffer_write_index);
- regarray eMAC0_TX_Buffer_last_index addr(base, 0x09C00)[48] type(TX_Buffer_last_index);
- regarray eMAC0_TX_routing addr(base, 0x09D00)[48] type(TX_routing);
- regarray eMAC0_TX_net_port_enable addr(base, 0x09E00)[48] type(TX_net_port_enable);
-
- /* 8.3.6.8 eMAC#1 RX Control Registers (0A000 to 0A8BC) */
- regarray eMAC1_RX_Buffer_start_addr addr(base, 0x0A000)[48] type(RX_Buffer_start_addr);
- regarray eMAC1_RX_Buffer_read_index addr(base, 0x0A100)[48] type(RX_Buffer_read_index);
- regarray eMAC1_RX_Buffer_write_index addr(base, 0x0A200)[48] type(RX_Buffer_write_index);
- regarray eMAC1_RX_Buffer_last_index addr(base, 0x0A300)[48] type(RX_Buffer_last_index);
-// regarray eMAC1_RX_Buffer_reserved addr(base, 0x0A400)[48] type(RX_Buffer_reserved);
- regarray eMAC1_RX_routing addr(base, 0x0A500)[48] type(RX_routing);
- regarray eMAC1_RX_net_port_MAC_high addr(base, 0x0A600)[48] type(RX_net_port_MAC_high);
- regarray eMAC1_RX_net_port_MAC_low addr(base, 0x0A700)[48] type(RX_net_port_MAC_low);
- regarray eMAC1_RX_net_port_enable addr(base, 0x0A800)[48] type(RX_net_port_enable);
-
-
- /* 8.3.6.9 eMAC#1 TX Control Registers (0A900 to 0AEBC) */
- regarray eMAC1_TX_Buffer_start_addr addr(base, 0x0A900)[48] type(TX_Buffer_start_addr);
- regarray eMAC1_TX_Buffer_read_index addr(base, 0x0AA00)[48] type(TX_Buffer_read_index);
- regarray eMAC1_TX_Buffer_write_index addr(base, 0x0AB00)[48] type(TX_Buffer_write_index);
- regarray eMAC1_TX_Buffer_last_index addr(base, 0x0AC00)[48] type(TX_Buffer_last_index);
- regarray eMAC1_TX_routing addr(base, 0x0AD00)[48] type(TX_routing);
- regarray eMAC1_TX_net_port_enable addr(base, 0x0AE00)[48] type(TX_net_port_enable);
-
- /* 8.3.6.10 eMAC#2 RX Control Registers (0B000 to 0B8BC) */
- regarray eMAC2_RX_Buffer_start_addr addr(base, 0x0B000)[48] type(RX_Buffer_start_addr);
- regarray eMAC2_RX_Buffer_read_index addr(base, 0x0B100)[48] type(RX_Buffer_read_index);
- regarray eMAC2_RX_Buffer_write_index addr(base, 0x0B200)[48] type(RX_Buffer_write_index);
- regarray eMAC2_RX_Buffer_last_index addr(base, 0x0B300)[48] type(RX_Buffer_last_index);
-// regarray eMAC2_RX_Buffer_reserved addr(base, 0x0B400)[48] type(RX_Buffer_reserved);
- regarray eMAC2_RX_routing addr(base, 0x0B500)[48] type(RX_routing);
- regarray eMAC2_RX_net_port_MAC_high addr(base, 0x0B600)[48] type(RX_net_port_MAC_high);
- regarray eMAC2_RX_net_port_MAC_low addr(base, 0x0B700)[48] type(RX_net_port_MAC_low);
- regarray eMAC2_RX_net_port_enable addr(base, 0x0B800)[48] type(RX_net_port_enable);
-
-
- /* 8.3.6.11 eMAC#2 TX Control Registers (0B900 to 0BEBC) */
- regarray eMAC2_TX_Buffer_start_addr addr(base, 0x0B900)[48] type(TX_Buffer_start_addr);
- regarray eMAC2_TX_Buffer_read_index addr(base, 0x0BA00)[48] type(TX_Buffer_read_index);
- regarray eMAC2_TX_Buffer_write_index addr(base, 0x0BB00)[48] type(TX_Buffer_write_index);
- regarray eMAC2_TX_Buffer_last_index addr(base, 0x0BC00)[48] type(TX_Buffer_last_index);
- regarray eMAC2_TX_routing addr(base, 0x0BD00)[48] type(TX_routing);
- regarray eMAC2_TX_net_port_enable addr(base, 0x0BE00)[48] type(TX_net_port_enable);
-
- /* 8.3.6.12 eMAC#3 RX Control Registers (0C000 to 0C8BC) */
- regarray eMAC3_RX_Buffer_start_addr addr(base, 0x0C000)[48] type(RX_Buffer_start_addr);
- regarray eMAC3_RX_Buffer_read_index addr(base, 0x0C100)[48] type(RX_Buffer_read_index);
- regarray eMAC3_RX_Buffer_write_index addr(base, 0x0C200)[48] type(RX_Buffer_write_index);
- regarray eMAC3_RX_Buffer_last_index addr(base, 0x0C300)[48] type(RX_Buffer_last_index);
-// regarray eMAC3_RX_Buffer_reserved addr(base, 0x0C400)[48] type(RX_Buffer_reserved);
- regarray eMAC3_RX_routing addr(base, 0x0C500)[48] type(RX_routing);
- regarray eMAC3_RX_net_port_MAC_high addr(base, 0x0C600)[48] type(RX_net_port_MAC_high);
- regarray eMAC3_RX_net_port_MAC_low addr(base, 0x0C700)[48] type(RX_net_port_MAC_low);
- regarray eMAC3_RX_net_port_enable addr(base, 0x0C800)[48] type(RX_net_port_enable);
-
-
- /* 8.3.6.13 eMAC#3 TX Control Registers (0C900 to 0CEBC) */
- regarray eMAC3_TX_Buffer_start_addr addr(base, 0x0C900)[48] type(TX_Buffer_start_addr);
- regarray eMAC3_TX_Buffer_read_index addr(base, 0x0CA00)[48] type(TX_Buffer_read_index);
- regarray eMAC3_TX_Buffer_write_index addr(base, 0x0CB00)[48] type(TX_Buffer_write_index);
- regarray eMAC3_TX_Buffer_last_index addr(base, 0x0CC00)[48] type(TX_Buffer_last_index);
- regarray eMAC3_TX_routing addr(base, 0x0CD00)[48] type(TX_routing);
- regarray eMAC3_TX_net_port_enable addr(base, 0x0CE00)[48] type(TX_net_port_enable);
-
- // regtype irq_status "Interrupt Status" {
- // _ 5 ro "Reserved";
- // };
-
- regarray PIC_irq_status addr(base, 0xd000)[48] type(uint64);
- regarray PIC_irq_mask addr(base, 0xd200)[48] type(uint64);
- regarray PIC_irq_reset addr(base, 0xd400)[48] type(uint64);
- regarray PIC_ipi_request addr(base, 0xd600)[48] type(uint64);
-
-/*
- regarray PIC_irq_status addr(base, 0xd000)[96] type(uint32);
- regarray PIC_irq_mask addr(base, 0xd200)[96] type(uint32);
- regarray PIC_irq_reset addr(base, 0xd400)[96] type(uint32);
- regarray PIC_ipi_request addr(base, 0xd600)[96] type(uint32);
-*/
- regarray PIC_irq_config addr(base, 0xd800)[48] type(uint32);
-
- register PIC_irq_request_mcpc addr(base, 0xd900) type(uint64);
-
-}; /* end device: eMAC */
-
-
-/*
-// 8.3.6.1 eMAC#0 status registers (0x07000 to 0x07044)
-
- regarray eMAC0_RX_frame_dropped one_byte( 0x00000)[47] type(RX_frame_dropped);
- register eMAC0_TX_FIFO_BUFF_FULL addr(base, 0x00030) type(TX_FIFO_buff_full);
- register eMAC0_RX_FIFO_BUFF_FULL addr(base, 0x00034) type(RX_FIFO_buff_full);
- register eMAC0_TX_EMAC_NOT_READY addr(base, 0x00038) type(TX_EMAC_Not_Ready);
- register eMAC0_RX_MAC_ADDR_ERR addr(base, 0x0003C) type(RX_MAC_Addr_Err);
- register eMAC0_RX_MAC_LOWER addr(base, 0x00040) type(RX_MAC_Lower);
- register eMAC0_RX_MAC_HIGHER addr(base, 0x00044) type(RX_MAC_Higher);
-
-
-// 8.3.6.2 eMAC#1 status registers (0x07100 to 0x07144)
-
- regarray eMAC1_RX_frame_dropped one_byte( 0x00100)[47] type(RX_frame_dropped);
- register eMAC1_TX_FIFO_BUFF_FULL addr(base, 0x00130) type(TX_FIFO_buff_full);
- register eMAC1_RX_FIFO_BUFF_FULL addr(base, 0x00134) type(RX_FIFO_buff_full);
- register eMAC1_TX_EMAC_NOT_READY addr(base, 0x00138) type(TX_EMAC_Not_Ready);
- register eMAC1_RX_MAC_ADDR_ERR addr(base, 0x0013C) type(RX_MAC_Addr_Err);
- register eMAC1_RX_MAC_LOWER addr(base, 0x00140) type(RX_MAC_Lower);
- register eMAC1_RX_MAC_HIGHER addr(base, 0x00144) type(RX_MAC_Higher);
-
-
-// 8.3.6.3 eMAC#2 status registers (0x07200 to 0x07244)
- regarray eMAC2_RX_frame_dropped one_byte( 0x00200)[47] type(RX_frame_dropped);
- register eMAC2_TX_FIFO_BUFF_FULL addr(base, 0x00230) type(TX_FIFO_buff_full);
- register eMAC2_RX_FIFO_BUFF_FULL addr(base, 0x00234) type(RX_FIFO_buff_full);
- register eMAC2_TX_EMAC_NOT_READY addr(base, 0x00238) type(TX_EMAC_Not_Ready);
- register eMAC2_RX_MAC_ADDR_ERR addr(base, 0x0023C) type(RX_MAC_Addr_Err);
- register eMAC2_RX_MAC_LOWER addr(base, 0x00240) type(RX_MAC_Lower);
- register eMAC2_RX_MAC_HIGHER addr(base, 0x00244) type(RX_MAC_Higher);
-
-
-// 8.3.6.4 eMAC#3 status registers (0x07300 to 0x07344)
-
- regarray eMAC3_RX_frame_dropped one_byte( 0x00300)[47] type(RX_frame_dropped);
- register eMAC3_TX_FIFO_BUFF_FULL addr(base, 0x00330) type(TX_FIFO_buff_full);
- register eMAC3_RX_FIFO_BUFF_FULL addr(base, 0x00334) type(RX_FIFO_buff_full);
- register eMAC3_TX_EMAC_NOT_READY addr(base, 0x00338) type(TX_EMAC_Not_Ready);
- register eMAC3_RX_MAC_ADDR_ERR addr(base, 0x0033C) type(RX_MAC_Addr_Err);
- register eMAC3_RX_MAC_LOWER addr(base, 0x00340) type(RX_MAC_Lower);
- register eMAC3_RX_MAC_HIGHER addr(base, 0x00344) type(RX_MAC_Higher);
-
-
-// 8.3.6.5 eMAC General Configuration Registers (0x07e00 to 0x07e10)
-
- register eMAC_MAC_base_addr_upper rw addr(base, 0x00e00) "eMAC config MAC base address (high)" {
- _ 16 mbz "Unused";
- mac_upper 16 rw "Upper 16 bits of base MAC address";
- };
-
-
- register eMAC_MAC_base_addr_lower addr(base, 0x00e04) "eMAC config MAC base address (low)" {
- mac_lower 32 rw "Lower 32 bits of base MAC address";
- };
-
- register eMAC_start_IP_SCC_network addr(base, 0x00e08) "eMAC config Start IP Address of SCC network" {
- ip 32 rw "IP Address for SCC Core 0. IPs for other cores are assigned in order";
- };
-
- register eMAC_host_IP_addr addr(base, 0x00e0c) "eMAC config Host IP Address" {
- ip 32 rw "IP Address of Host computer where /shared is mounted";
- };
-
- register eMAC_host_GW_addr addr(base, 0x00e10) "eMAC config Host gateway Address" {
- ip 32 rw "Gateway of Host computer";
- };
-
-
-// 8.3.6.6 eMAC#0 RX Control Registers (09000 to 098BC)
- regarray eMAC0_RX_Buffer_start_addr addr(base, 0x02000)[48] type(RX_Buffer_start_addr);
- regarray eMAC0_RX_Buffer_read_index addr(base, 0x02100)[48] type(RX_Buffer_read_index);
- regarray eMAC0_RX_Buffer_write_index addr(base, 0x02200)[48] type(RX_Buffer_write_index);
- regarray eMAC0_RX_Buffer_last_index addr(base, 0x02300)[48] type(RX_Buffer_last_index);
-// regarray eMAC0_RX_Buffer_reserved addr(base, 0x02400)[48] type(RX_Buffer_reserved);
- regarray eMAC0_RX_routing addr(base, 0x02500)[48] type(RX_routing);
- regarray eMAC0_RX_net_port_MAC_high addr(base, 0x02600)[48] type(RX_net_port_MAC_high);
- regarray eMAC0_RX_net_port_MAC_low addr(base, 0x02700)[48] type(RX_net_port_MAC_low);
- regarray eMAC0_RX_net_port_enable addr(base, 0x02800)[48] type(RX_net_port_enable);
-
-
-// 8.3.6.7 eMAC#0 TX Control Registers (09900 to 09EBC)
- regarray eMAC0_TX_Buffer_start_addr addr(base, 0x02900)[48] type(TX_Buffer_start_addr);
- regarray eMAC0_TX_Buffer_read_index addr(base, 0x02A00)[48] type(TX_Buffer_read_index);
- regarray eMAC0_TX_Buffer_write_index addr(base, 0x02B00)[48] type(TX_Buffer_write_index);
- regarray eMAC0_TX_Buffer_last_index addr(base, 0x02C00)[48] type(TX_Buffer_last_index);
- regarray eMAC0_TX_routing addr(base, 0x02D00)[48] type(TX_routing);
- regarray eMAC0_TX_net_port_enable addr(base, 0x02E00)[48] type(TX_net_port_enable);
-
-
-// 8.3.6.8 eMAC#1 RX Control Registers (0A000 to 0A8BC)
- regarray eMAC1_RX_Buffer_start_addr addr(base, 0x03000)[48] type(RX_Buffer_start_addr);
- regarray eMAC1_RX_Buffer_read_index addr(base, 0x03100)[48] type(RX_Buffer_read_index);
- regarray eMAC1_RX_Buffer_write_index addr(base, 0x03200)[48] type(RX_Buffer_write_index);
- regarray eMAC1_RX_Buffer_last_index addr(base, 0x03300)[48] type(RX_Buffer_last_index);
-// regarray eMAC1_RX_Buffer_reserved addr(base, 0x03400)[48] type(RX_Buffer_reserved);
- regarray eMAC1_RX_routing addr(base, 0x03500)[48] type(RX_routing);
- regarray eMAC1_RX_net_port_MAC_high addr(base, 0x03600)[48] type(RX_net_port_MAC_high);
- regarray eMAC1_RX_net_port_MAC_low addr(base, 0x03700)[48] type(RX_net_port_MAC_low);
- regarray eMAC1_RX_net_port_enable addr(base, 0x03800)[48] type(RX_net_port_enable);
-
-
-// 8.3.6.9 eMAC#1 TX Control Registers (0A900 to 0AEBC)
- regarray eMAC1_TX_Buffer_start_addr addr(base, 0x03900)[48] type(TX_Buffer_start_addr);
- regarray eMAC1_TX_Buffer_read_index addr(base, 0x03A00)[48] type(TX_Buffer_read_index);
- regarray eMAC1_TX_Buffer_write_index addr(base, 0x03B00)[48] type(TX_Buffer_write_index);
- regarray eMAC1_TX_Buffer_last_index addr(base, 0x03C00)[48] type(TX_Buffer_last_index);
- regarray eMAC1_TX_routing addr(base, 0x03D00)[48] type(TX_routing);
- regarray eMAC1_TX_net_port_enable addr(base, 0x03E00)[48] type(TX_net_port_enable);
-
-// 8.3.6.10 eMAC#2 RX Control Registers (0B000 to 0B8BC)
- regarray eMAC2_RX_Buffer_start_addr addr(base, 0x04000)[48] type(RX_Buffer_start_addr);
- regarray eMAC2_RX_Buffer_read_index addr(base, 0x04100)[48] type(RX_Buffer_read_index);
- regarray eMAC2_RX_Buffer_write_index addr(base, 0x04200)[48] type(RX_Buffer_write_index);
- regarray eMAC2_RX_Buffer_last_index addr(base, 0x04300)[48] type(RX_Buffer_last_index);
-// regarray eMAC2_RX_Buffer_reserved addr(base, 0x04400)[48] type(RX_Buffer_reserved);
- regarray eMAC2_RX_routing addr(base, 0x04500)[48] type(RX_routing);
- regarray eMAC2_RX_net_port_MAC_high addr(base, 0x04600)[48] type(RX_net_port_MAC_high);
- regarray eMAC2_RX_net_port_MAC_low addr(base, 0x04700)[48] type(RX_net_port_MAC_low);
- regarray eMAC2_RX_net_port_enable addr(base, 0x04800)[48] type(RX_net_port_enable);
-
-
-// 8.3.6.11 eMAC#2 TX Control Registers (0B900 to 0BEBC)
- regarray eMAC2_TX_Buffer_start_addr addr(base, 0x04900)[48] type(TX_Buffer_start_addr);
- regarray eMAC2_TX_Buffer_read_index addr(base, 0x04A00)[48] type(TX_Buffer_read_index);
- regarray eMAC2_TX_Buffer_write_index addr(base, 0x04B00)[48] type(TX_Buffer_write_index);
- regarray eMAC2_TX_Buffer_last_index addr(base, 0x04C00)[48] type(TX_Buffer_last_index);
- regarray eMAC2_TX_routing addr(base, 0x04D00)[48] type(TX_routing);
- regarray eMAC2_TX_net_port_enable addr(base, 0x04E00)[48] type(TX_net_port_enable);
-
-// 8.3.6.12 eMAC#3 RX Control Registers (0C000 to 0C8BC)
- regarray eMAC3_RX_Buffer_start_addr addr(base, 0x05000)[48] type(RX_Buffer_start_addr);
- regarray eMAC3_RX_Buffer_read_index addr(base, 0x05100)[48] type(RX_Buffer_read_index);
- regarray eMAC3_RX_Buffer_write_index addr(base, 0x05200)[48] type(RX_Buffer_write_index);
- regarray eMAC3_RX_Buffer_last_index addr(base, 0x05300)[48] type(RX_Buffer_last_index);
-// regarray eMAC3_RX_Buffer_reserved addr(base, 0x05400)[48] type(RX_Buffer_reserved);
- regarray eMAC3_RX_routing addr(base, 0x05500)[48] type(RX_routing);
- regarray eMAC3_RX_net_port_MAC_high addr(base, 0x05600)[48] type(RX_net_port_MAC_high);
- regarray eMAC3_RX_net_port_MAC_low addr(base, 0x05700)[48] type(RX_net_port_MAC_low);
- regarray eMAC3_RX_net_port_enable addr(base, 0x05800)[48] type(RX_net_port_enable);
-
-
-// 8.3.6.13 eMAC#3 TX Control Registers (0C900 to 0CEBC)
- regarray eMAC3_TX_Buffer_start_addr addr(base, 0x05900)[48] type(TX_Buffer_start_addr);
- regarray eMAC3_TX_Buffer_read_index addr(base, 0x05A00)[48] type(TX_Buffer_read_index);
- regarray eMAC3_TX_Buffer_write_index addr(base, 0x05B00)[48] type(TX_Buffer_write_index);
- regarray eMAC3_TX_Buffer_last_index addr(base, 0x05C00)[48] type(TX_Buffer_last_index);
- regarray eMAC3_TX_routing addr(base, 0x05D00)[48] type(TX_routing);
- regarray eMAC3_TX_net_port_enable addr(base, 0x05E00)[48] type(TX_net_port_enable);
-
-*/
+++ /dev/null
-/*
- * Copyright (c) 2010, ETH Zurich. All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-/*
- * rck.dev
- *
- * DESCRIPTION: Intel Rock Creek (Single Chip Cloud Computer) tile registers
- *
- * Numbers in comments refer to the "Intel Rock Creek External
- * Architecture Specification" (EAS) Revision 0.91, September 16, 2009
- * (Contacts: Yatin Hoskote and Greg Ruhl). See also: "Rock Creek
- * Platform - Quick Reference Guide" (QRG), Michael Riepen, Intel
- * Braunschweig, September 2009.
- *
- * Updated based on the "Intel SCC External Architecture Specification"
- * (EAS) Revision 0.97, June 21, 2010.
- *
- */
-
-device rck msbfirst ( addr base ) "Intel Rock Creek Tile registers" {
-
- // 3.2.6.1.2
- regarray glcfg addr(base, 0x0010)[2;0x8] "Gauss Lake (core) config" {
- _ 6 mbz;
- bp3 1 ro "Breakpoint 3 detected";
- bp2 1 ro "Breakpoint 2 detected";
- bp1 1 ro "Breakpoint 1 or CTR1 PM event detected";
- bp0 1 ro "Breakpoint 0 or CTR0 PM event detected";
- ierr 1 rwc "0 if internal error detected";
- ferr 1 rwc "0 if FPU error detected";
- prdy 1 ro "Processor in probe mode";
- smiact 1 ro "0 if System Mgmt Mode active";
- shutdown 1 rwc "Shutdown captured on internal FSB";
- flushc 1 rwc "Flush captured on internal FSB";
- halt 1 rwc "Halt captured on internal FSB";
- wrback 1 rwc "Write back captured on internal FSB";
- flushack 1 rwc "Flush ack captured on internal FSB";
- btrcmsg 1 rwc "Branch Trace Msg captured on internal FSB";
- apic1en 1 rw "Core 1 APIC enable";
- apic0en 1 rw "Core 0 APIC enable";
- cputyp 1 rw "Dual processor mode (do not use!)";
- a20m 1 rw "Disable physical A20 mask";
- smi 1 rw "SMI disable";
- stpclk 1 rw "Enable processor clock";
- rs 1 rw "Normal mode (0=probe mode)";
- ignne 1 rw "Core freezes on FP error";
- flush 1 rw "Flush is inactive";
- init 1 rw "Soft-reset active";
- intr 1 rw "Maskable interrupt active";
- nmi 1 rw "NMI active";
- };
-
- // 3.2.6.1.3
- regarray l2cfg rw addr(base, 0x0020)[2;0x8] "L2 cache config" {
- _ 18 mbz;
- stopl2ccclk 1 "Clock gates the cache controller";
- stopl2arrayclk 1 "Clock gates the data/tag array prtn";
- blfloaten 1 "Bit line float enable (to save power)";
- wlslpen 1 "Word line driver sleep enable";
- wtslpen 1 "Write bit line driver sleep enable";
- flipen 1 "UNUSED";
- dataeccen 1 "Enable data ECC";
- tageccen 1 "Enable tag ECC";
- slpbypass 1 "Disable sleep";
- waydisable 1 "Disable L2 cache";
- bbl2slppgm 4 "Programmable sleep state";
- };
-
- // The two documents seem at odds here. Both agree on a sensor
- // control register, the fields are from QRG:
- register sensor rw addr(base, 0x0040) "Sensor register" {
- _ 18 mbz;
- en 1 "Sensor enable";
- pulsecnt 13 "Gate pulse counter";
- };
- // ... but only the EAS has a value register here, without defining
- // it:
- register sensval rw addr(base, 0x0048) "Sensor value" {
- _ 6 mbz;
- val 26 "Sensor value";
- };
-
- // 3.2.6.1.1
- register gcbcfg rw addr(base, 0x0080) "Global Clock Unit Config" {
- _ 6 mbz;
- rcrs 7 "Router clock ratio setting";
- tcrs 7 "Tile clock ratio setting";
- tcds 4 "Tile clock divider setting";
- srel20 1 "Synch. reset enable for L2 0";
- srel21 1 "Synch. reset enable for L2 1";
- srec1 1 "Synch. reset enable for core 1";
- srec0 1 "Synch. reset enable for core 0";
- resl21 1 "Reset for L2 1";
- resl20 1 "Reset for L2 0";
- resc1 1 "Reset for core 1";
- resc0 1 "Reset for core 0";
- };
-
- constants subid "Tile port identifiers" {
- core0 = 0b000 "Core 0 or RTG";
- core1 = 0b001 "Core 1";
- crb = 0b010 "CRB";
- mpb = 0b011 "MPB";
- east = 0b100 "East";
- south = 0b101 "South";
- west = 0b110 "West";
- north = 0b111 "North";
- };
-
- // Defined in the QRG:
- register tileid ro addr(base, 0x0100) "Tile id" {
- _ 21;
- y 4 "Y coordinate of tile";
- x 4 "X coordinate of tile";
- reqid 3 type(subid) "Requester sub-id";
- };
-
- // Define in both EAS and QRG:
- regarray tas rwc addr(base, 0x0200)[2;0x200] "Test and Set" {
- _ 31 mbz;
- val 1 rwc "Test-and-set bit";
- };
-
- // Lookup table entries
- constants mcdests "Memory controller tile identifiers" {
- mc1_tile = 0x00 "Tile of MC 1";
- mc2_tile = 0x50 "Tile of MC 2";
- mc3_tile = 0x02 "Tile of MC 3";
- mc4_tile = 0x52 "Tile of MC 4";
- sif_tile = 0x30 "Tile of System Interface";
- // FIXME: This is probably wrong!
- rpc_tile = 0x32 "Tile of Rock Creek Power Controller";
- };
- constants mcsubdests "Subdestinations for memory controllers" {
- mc1_sd = 0b110 "MC1: West of 0,0";
- mc2_sd = 0b100 "MC2: East of 5,0";
- // FIXME: Need values for commented out parts
-// mc3_sd = 0b110 "MC3: West of 0,2";
-// mc4_sd = 0b100 "MC4: East of 5,2";
- sif_sd = 0b101 "System Interface: South of 3,0";
-// rpc_sd = 0b101 "RPC Interface: South of 0,0";
- };
-
- regtype lute "Lookup table entry" {
- _ 10 mbz;
- bypass 1 "Bypass";
- route 8 "Core identifier (x,y)";
- subdest 3 type(subid) "Destination sub-id";
- addrbits 10 "Top 10 bits of new 34-bit physical address";
- };
- regarray lut0 rw addr(base, 0x0800)[256;8] "Core 0 lookup table" type(lute);
- regarray lut1 rw addr(base, 0x1000)[256;8] "Core 1 lookup table" type(lute);
-
-
- // 3.2.9. Writing the RPC actually requires a large physical
- // address, since you need to route a request across the fabric to
- // it. See the QRG for (some) details.
- constants visland "Voltage island identifier" {
- vi_ul = 0b000 "Upper left group of 4";
- vi_um = 0b001 "Upper middle group of 4";
- vi_rs = 0b010 "Router supply";
- vi_ur = 0b011 "Upper right group of 4";
- vi_ll = 0b100 "Lower left group of 4";
- vi_lm = 0b101 "Lower middle group of 4";
- vi_ur_ = 0b110 "Router supply";
- vi_lr = 0b111 "Lower right group of 4";
- };
-
- regtype rpc "Rock Creek power controller" {
- _ 18 mbz;
- _ 1 mb1;
- _ 2;
- vid 3 wo type(visland) "Voltage island";
- val 8 wo "Value (x 6.25mV)";
- };
-
-};
// Time synchronization errors
failure SYNC_MISS "Missed synchronization phase",
- // SCC driver errors
- failure CROSS_MC "Frame crosses memory controllers",
-
// ID capability
failure ID_SPACE_EXHAUSTED "ID space exhausted",
-----------
Later:
-data Arch = ARM | Beehive | SCC | X86_32 | X86_64
+data Arch = ARM | Beehive | X86_32 | X86_64
sbin/angler \
sbin/sshd \
sbin/lshw \
- sbin/sif \
sbin/slideshow \
sbin/vbe \
sbin/vmkitmon \
call bind_monitor_request(coreid core_id, caprep cap);
response bind_monitor_reply(errval err);
- message bind_monitor_request_scc(coreid core_id,
- caprep cap,
- chanid chan_id,
- coreid from_core_id);
- message bind_monitor_reply_scc(errval err,
- chanid chan_id,
- coreid core_id);
- message bind_monitor_proxy_scc(coreid dst_core_id,
- caprep cap,
- chanid chan_id,
- coreid core_id);
message bind_ump_request(iref iref,
mon_id mon_id,
uint32 channel_length_in,
__asm volatile("clflush %0" :: "m" (line));
}
-#ifndef __scc__
-# define CACHE_LINE_SIZE 64 /* bytes */
-#else
-# define CACHE_LINE_SIZE 32 /* bytes */
-#endif
+#define CACHE_LINE_SIZE 64 /* bytes */
#ifndef __cplusplus
/* flush a range of memory from the cache */
__asm volatile("clflush %0" :: "m" (line));
}
-#ifndef __scc__
-# define CACHE_LINE_SIZE 64 /* bytes */
-#else
-# define CACHE_LINE_SIZE 32 /* bytes */
-#endif
+#define CACHE_LINE_SIZE 64 /* bytes */
#ifndef __cplusplus
/* flush a range of memory from the cache */
}
#endif
-#ifdef __scc__
-static inline void cl1flushmb(void)
-{
- __asm volatile ( ".byte 0x0f; .byte 0x0a;\n" ); // CL1FLUSHMB
-}
-#endif
-
#endif // __ASSEMBLER__
#endif // ARCH_X86_BARRELFISH_KPI_X86_H
#ifndef X86_32_BARRELFISH_CPU_H
#define X86_32_BARRELFISH_CPU_H
-#ifndef __scc__
-# define CURRENT_CPU_TYPE CPU_X86_32
-#else
-# define CURRENT_CPU_TYPE CPU_SCC
-#endif
+#define CURRENT_CPU_TYPE CPU_X86_32
#endif
}
-#ifdef __scc__
-/**
- * \brief Return the physical address and size of a frame capability
- *
- * \param frame CSpace address of frame capability
- * \param ret frame_identity struct filled in with relevant data
- *
- * \return Error code
- */
-static inline errval_t invoke_scc_frame_identify(struct capref frame,
- struct scc_frame_identity *ret)
-{
- uint8_t invoke_bits = get_cap_valid_bits(frame);
- capaddr_t invoke_cptr = get_cap_addr(frame) >> (CPTR_BITS - invoke_bits);
-
- struct sysret sysret =
- syscall2((invoke_bits << 16) | (FrameCmd_SCC_Identify << 8)
- | SYSCALL_INVOKE, invoke_cptr);
-
- assert(ret != NULL);
- if (err_is_ok(sysret.error)) {
- ret->route = sysret.value & 0xff;
- ret->subdest = (sysret.value >> 8) & 0xff;
- ret->addrbits = sysret.value >> 16;
- return sysret.error;
- }
-
- return sysret.error;
-}
-#endif
-
static inline errval_t invoke_iocap_in(struct capref iocap, enum io_cmd cmd,
uint16_t port, uint32_t *data)
{
uint8_t *regs = fpustate->registers;
regs += 16 - ((uintptr_t)regs % 16);
- // XXX: Should really be detected at run-time (and it's not SCC-specific)
-#ifdef __scc__
- __asm volatile("fnsave %0; fwait" : "=m" (*regs));
-#else
__asm volatile("fxsave %0" : "=m" (*regs));
-#endif
}
static inline void fpu_restore(struct registers_fpu_x86_32 *fpustate)
uint8_t *regs = fpustate->registers;
regs += 16 - ((uintptr_t)regs % 16);
- // XXX: Should really be detected at run-time (and it's not SCC-specific)
-#ifdef __scc__
- __asm volatile ("frstor %0" :: "m" (*regs));
-#else
__asm volatile ("fxrstor %0" :: "m" (*regs));
-#endif
}
#endif // __ASSEMBLER__
+++ /dev/null
-/**
- * \file
- * \brief scc shared memory
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, 2011, 2012, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef ARCH_SCC_BARRELFISH_KPI_SHARED_MEM_H
-#define ARCH_SCC_BARRELFISH_KPI_SHARED_MEM_H
-
-#ifdef __scc__
-#define SHARED_MEM_MIN 0x80000000
-#define SHARED_MEM_MAX 0xc0000000
-#define SHARED_MEM_SIZE 0x40000000
-#define PERCORE_MEM_SIZE 0x1000000
-
-#define PRIVATE_MEM_MAX 0x27000000
-
-#define EXTRA_SHARED_MEM_MIN 0x70000000
-#define EXTRA_SHARED_MEM_MAX 0x80000000
-
-#endif
-
-#endif // ARCH_SCC_BARRELFISH_KPI_SHARED_MEM_H
errval_t bulk_init(void *mem, size_t size, size_t block_size,
struct bulk_transfer *bt);
errval_t bulk_create(size_t size, size_t block_size, struct capref *shared_mem,
- struct bulk_transfer *bt, bool LMP_only);
+ struct bulk_transfer *bt);
struct bulk_buf *bulk_alloc(struct bulk_transfer *bt);
errval_t bulk_free(struct bulk_transfer *bt, uintptr_t id);
#ifdef CONFIG_QEMU_NETWORK
-#if !defined(__scc__)
/// Size of (static) heap memory
#ifndef MEM_SIZE
#define MEM_SIZE (60*1024*1024)
#define MEM_CONF_LOC "for_qemu"
#endif // MEM_CONF_LOC
-#else // !defined(__scc__)
-
-/************** SCC machine ******************/
-/// Size of (static) heap memory
-#ifndef MEM_SIZE
-#define MEM_SIZE (60*1024)
-#endif // MEM_SIZE
-
-/// Number of PBUF structs available
-#ifndef MEMP_NUM_PBUF
-#define MEMP_NUM_PBUF 4024
-#endif // MEMP_NUM_PBUF
-
-/// Number of PBUF buffers available
-#ifndef PBUF_POOL_SIZE
-#define PBUF_POOL_SIZE 4024
-#endif // PBUF_POOL_SIZE
-
-/* Used in the ethersrv.c and the driver. */
-#define RECEIVE_BUFFERS 2024
-#define TRANSMIT_BUFFERS 1024 //< Number of transmit descriptors
- //< (must be multiple of 8)
-
-/// the size of the pool
-#ifndef PBUF_POOL_BUFSIZE
-#define PBUF_POOL_BUFSIZE (2048)
-#endif // PBUF_POOL_BUFSIZE
-
-/* from where the memory conf is coming? */
-#ifndef MEM_CONF_LOC
-#define MEM_CONF_LOC "for_scc"
-#endif // MEM_CONF_LOC
-
-
-#endif // !defined(__scc__)
-
-
#else // CONFIG_QEMU_NETWORK
// ##################################################################
// XXX Should be from SKB or whatever. On Arm this is variable and you need
// to read the coproc to see what size it is.
#if defined(__x86_64__) || defined(__i386__)
-# if defined(__scc__)
-# define CACHELINE_BYTES 32
-# else
# define CACHELINE_BYTES 64
-# endif
#elif defined(__arm__)
# define CACHELINE_BYTES 32
#elif defined(__aarch64__)
KernelCmd_Retype,
KernelCmd_Has_descendants,
KernelCmd_Sync_timer,
- KernelCmd_Spawn_SCC_Core,
KernelCmd_IPI_Register,
KernelCmd_IPI_Delete,
KernelCmd_GetGlobalPhys,
*/
enum frame_cmd {
FrameCmd_Identify, ///< Return physical address of frame
- FrameCmd_SCC_Identify, ///< Return MC route to frame
FrameCmd_ModifyFlags, ///< Modify flags for (part of) the mapped region of frame
};
uint8_t type; ///< Type of VNode
};
-#ifdef __scc__
-struct scc_frame_identity {
- uint8_t route, subdest;
- uint16_t addrbits;
-};
-#endif
-
#endif // __ASSEMBLER__
#endif // BARRELFISH_CAPABILITIES_H
CPU_K1OM,
CPU_X86_64,
CPU_X86_32,
- CPU_SCC,
CPU_ARM7,
CPU_ARM5,
CPU_ARM8,
static inline const char *cpu_type_to_archstr(enum cpu_type cpu_type)
{
- STATIC_ASSERT(CPU_TYPE_NUM == 7, "knowledge of all CPU types here");
+ STATIC_ASSERT(CPU_TYPE_NUM == 6, "knowledge of all CPU types here");
switch(cpu_type) {
case CPU_K1OM: return "k1om";
case CPU_X86_64: return "x86_64";
case CPU_X86_32: return "x86_32";
- case CPU_SCC: return "scc";
case CPU_ARM7: return "armv7";
case CPU_ARM5: return "armv5";
case CPU_ARM8: return "armv8";
static inline const enum cpu_type archstr_to_cputype(char* archstr)
{
- STATIC_ASSERT(CPU_TYPE_NUM == 7, "knowledge of all CPU types here");
+ STATIC_ASSERT(CPU_TYPE_NUM == 6, "knowledge of all CPU types here");
if(strcmp("k1om", archstr) == 0) return CPU_K1OM;
if(strcmp("x86_64", archstr) == 0) return CPU_X86_64;
if(strcmp("x86_32", archstr) == 0) return CPU_X86_32;
- if(strcmp("scc", archstr) == 0) return CPU_SCC;
if(strcmp("armv7", archstr) == 0) return CPU_ARM7;
if(strcmp("armv5", archstr) == 0) return CPU_ARM5;
if(strcmp("armv8", archstr) == 0) return CPU_ARM8;
/// Emit memory barrier needed between writing UMP payload and header
static inline void flounder_stub_ump_barrier(void)
{
-#if defined(__i386__) || defined(__x86_64__) || defined(__scc__)
+#if defined(__i386__) || defined(__x86_64__)
/* the x86 memory model ensures ordering of stores, so all we need to do
* is prevent the compiler from reordering the instructions */
__asm volatile ("" : : : "memory");
#ifndef _STRING_H_
#define _STRING_H_
-#if defined(__scc__)
- // Enable optimized memcpy for scc
-//#define SCC_MEMCPY 1
-#endif // defined(__scc__)
-
#include <stddef.h>
/* 7.21.2 Copying functions */
void *memcpy(void *s1, const void *s2, size_t n);
-#if defined(__scc__) && defined(SCC_MEMCPY)
-// memcpy implementations optimized for SCC
-void *memcpy_scc1(void *dest, const void *src, size_t count);
-void *memcpy_scc2(void *dest, const void *src, size_t count);
-#endif // defined(__scc__) && defined(SCC_MEMCPY)
-
void *memmove(void *s1, const void *s2, size_t n);
char *strcpy(char *s1, const char *s2);
char *strncpy(char *s1, const char *s2, size_t n);
#ifndef PROCON_H_
#define PROCON_H_
-#ifdef __scc__
-#define CACHESIZE 32
-#else
#define CACHESIZE 64
-#endif
#define SLOT_PADDING ((CACHESIZE) - ((sizeof(struct slot_data))%(CACHESIZE)))
struct xeon_phi_boot_params *bp;
uint8_t xeon_phi_id;
#endif
-
-#ifdef __scc__
- struct x86_coredata_modinfo modinfo[10];
- struct x86_coredata_mmap mmap[20];
-
- char sh[2048];
- char strings[1024];
-#endif
} __attribute__ ((packed));
#define X86_CORE_DATA_PAGES 1100
#else
# define X86_32_PTABLE_EXECUTE_DISABLE ((paging_x86_32_flags_t)0)
#endif
-#ifndef __scc__
-# define X86_32_PTABLE_GLOBAL_PAGE (((paging_x86_32_flags_t)1) << 8)
-# define X86_32_PTABLE_ATTR_INDEX (((paging_x86_32_flags_t)1) << 7)
-#else
-# define X86_32_PTABLE_GLOBAL_PAGE ((paging_x86_32_flags_t)0)
-# define SCC_PTABLE_MESSAGE_BUFFER (((paging_x86_32_flags_t)1) << 7)
-# define X86_32_PTABLE_ATTR_INDEX (((paging_x86_32_flags_t)1) << 7)
-#endif
+#define X86_32_PTABLE_GLOBAL_PAGE (((paging_x86_32_flags_t)1) << 8)
+#define X86_32_PTABLE_ATTR_INDEX (((paging_x86_32_flags_t)1) << 7)
#define X86_32_PTABLE_DIRTY (((paging_x86_32_flags_t)1) << 6)
#define X86_32_PTABLE_ACCESSED (((paging_x86_32_flags_t)1) << 5)
#define X86_32_PTABLE_CACHE_DISABLED (((paging_x86_32_flags_t)1) << 4)
*/
void apic_init(void)
{
-#if !defined(__scc__)
ia32_apic_base_t apic_base_msr = ia32_apic_base_rd(NULL);
lpaddr_t apic_phys = ((lpaddr_t)apic_base_msr) & APIC_BASE_ADDRESS_MASK;
lvaddr_t apic_base = paging_map_device(apic_phys, APIC_PAGE_SIZE);
-#else
- lpaddr_t apic_phys = (lpaddr_t)0xfee00000;
- lvaddr_t apic_base = paging_map_device((lpaddr_t)0xfee00000, APIC_PAGE_SIZE);
-#endif
if(apic_base == 0) {
panic("apic_init(): could not map APIC registers");
xapic_initialize(&apic, (void *)apic_base);
-#if !defined(__scc__)
apic_id = apic_get_id();
debug(SUBSYS_APIC, "APIC ID=%hhu\n", apic_id);
if (ia32_apic_base_bsp_extract(apic_base_msr)) {
debug(SUBSYS_APIC, "APIC: application processor\n");
apic_bsp = false;
}
-#endif
// initialize spurious interrupt register
// no focus, software enabled
/*
* TODO: How are the local intercore interrups handled using the APIC?
*/
-#if defined(__scc__) // || defined(__k1om__)
- //LINT0: inter-core interrupt
- //generate fixed int
- {
- xapic_lvt_lint_t t = xapic_lvt_lint0_initial;
- t = xapic_lvt_lint_vector_insert( t, APIC_INTER_CORE_VECTOR);
- t = xapic_lvt_lint_dlv_mode_insert( t, xapic_fixed);
- t = xapic_lvt_lint_trig_mode_insert(t, xapic_edge);
- t = xapic_lvt_lint_mask_insert( t, xapic_not_masked);
- xapic_lvt_lint0_wr(&apic, t);
-
- //LINT1: usually used to generate an NMI
- //generate device interrupt
- t = xapic_lvt_lint1_initial;
- t = xapic_lvt_lint_vector_insert( t, 32);
- t = xapic_lvt_lint_dlv_mode_insert( t, xapic_fixed);
- t = xapic_lvt_lint_trig_mode_insert(t, xapic_edge);
- t = xapic_lvt_lint_mask_insert( t, xapic_not_masked);
- xapic_lvt_lint1_wr(&apic, t);
- }
-#else
//LINT0: external interrupts, delivered by the 8259 PIC
//generate extInt as if INTR pin were activated
//disabled (we use IOAPICs exclusively)
t = xapic_lvt_lint_mask_insert( t, xapic_masked);
xapic_lvt_lint1_wr(&apic, t);
}
-#endif
//error interrupt register
{
}
#endif
-#if !defined(__scc__)
// enable the thing, if it wasn't already!
if (!(ia32_apic_base_global_extract(apic_base_msr))) {
apic_base_msr = ia32_apic_base_global_insert(apic_base_msr, 1);
ia32_apic_base_wr(NULL,apic_base_msr);
}
-#endif
}
/** \brief This function sends an IPI
#include <elf/elf.h>
#include <kernel_multiboot.h>
#include <target/x86/barrelfish_kpi/coredata_target.h>
-#ifdef __scc__
-# include <rck.h>
-# include <init.h>
-#endif
struct x86_core_data *glbl_core_data = NULL;
#include <arch/x86/startup_x86.h>
#include <dev/ia32_dev.h>
-#ifdef __scc__
-# include <rck.h>
-#endif
-
/// Optional core ID to use for the BSP core (command-line argument)
static int bsp_coreid;
{"logmask", ArgType_Int, { .integer = &kernel_log_subsystem_mask }},
{"ticks", ArgType_Bool, { .boolean = &kernel_ticks_enabled }},
{"timeslice", ArgType_Int, { .integer = &kernel_timeslice }},
-#ifndef __scc__ // FIXME: why not?
{"serial", ArgType_Int, { .integer = &serial_portbase }},
-#endif
{"bsp_coreid", ArgType_Int, { .integer = &bsp_coreid }},
{NULL, 0, {NULL}}
};
# define BSP_INIT_MODULE_PATH BF_BINARY_PREFIX "k1om/sbin/init"
#elif defined(__x86_64__)
# define BSP_INIT_MODULE_PATH BF_BINARY_PREFIX "x86_64/sbin/init"
-#elif defined(__scc__)
-# define BSP_INIT_MODULE_PATH BF_BINARY_PREFIX "scc/sbin/init"
#elif defined(__i386__)
# define BSP_INIT_MODULE_PATH BF_BINARY_PREFIX "x86_32/sbin/init"
#else
#include <string.h>
#include <kernel.h>
#include <arch/x86/apic.h>
-#ifndef __scc__
-# include <arch/x86/rtc.h>
-# include <arch/x86/pit.h>
-#endif
+#include <arch/x86/rtc.h>
+#include <arch/x86/pit.h>
#include <arch/x86/global.h>
#include <arch/x86/timing.h>
static uint32_t tickspersec = 0;
static uint64_t tscperms = 0;
-#if !defined(__scc__) && !defined(__k1om__)
+#if !defined(__k1om__)
/**
* \brief Calibrates local APIC timer against RTC.
* \return Local APIC timer ticks per RTC second.
// Wait until start of new second
/*
- * The Intel® Xeon PhiTM coprocessor has a SBox MMIO register that provides
+ * The Intel Xeon PhiTM coprocessor has a SBox MMIO register that provides
* the current CPU frequency, which can be used to calibrate the LAPIC timer.
* The TOD clock has to be emulated in software to query the host OS for the
* time at bootup and then using the LAPIC timer interrupt to update it.
}
#endif
-#ifndef __scc__
/// Number of measurement iterations
#define MAX_ITERATIONS 100
tpms, MAX_ITERATIONS - 1, avgdistance);
return tpms;
}
-#endif
void timing_apic_timer_set_ms(unsigned int ms)
{
tickspersec = 31250000;
tscperms = tickspersec/1000;
} else {
-#ifndef __scc__
if(apic_is_bsp()) {
#ifdef __k1om__
tickspersec = calibrate_apic_timer_k1om();
tickspersec = global->tickspersec;
tscperms = global->tscperms;
}
-
-#else
- // SCC timer rate (we just know it)
- tickspersec = 400000000; // XXX: APIC timer ticks faster than fits in a 32bit value
- tscperms = 533000;
-#endif
}
}
halt();
}
-#if defined(__scc__) && defined(NO_INTERRUPT)
-# include <rck.h>
-# include <dispatch.h>
-#endif
-
/**
* \brief Halt processor until an interrupt arrives
*
*/
void __attribute__ ((noreturn)) wait_for_interrupt(void)
{
-#if defined(__scc__) && defined(NO_INTERRUPT)
-# error Revisit for new scheduling
- for(;;) {
- rck_handle_notification();
-
- struct dcb *next = schedule();
- if(next) {
- dispatch(next);
- }
- }
-
-#else
-
__asm volatile("mov %[x86_32_kernel_stack], %%esp\n\t"
"addl %[stack_size], %%esp\n\t"
"sti \n\t"
[x86_32_kernel_stack] "r" (&x86_32_kernel_stack),
[stack_size] "i" (X86_32_KERNEL_STACK_SIZE)
: "esp" );
-#endif
panic("hlt should not return");
}
#include <trace/trace.h>
#include <trace_definitions/trace_defs.h>
#include <exec.h>
-#ifdef __scc__
-# include <rck.h>
-#else
-# include <arch/x86/ipi_notify.h>
-#endif
+#include <arch/x86/ipi_notify.h>
#include <arch/x86/timing.h>
#include <arch/x86/syscall.h>
#include <barrelfish_kpi/cpu_arch.h>
apic_eoi();
} else if (vector == APIC_INTER_CORE_VECTOR) {
apic_eoi();
-#ifdef __scc__
- rck_handle_notification();
-#else
ipi_handle_notify();
-#endif
}
#if 0
else if (irq >= 0 && irq <= 15) { // classic PIC device interrupt
else { // APIC device interrupt (or IPI)
//printk(LOG_NOTE, "interrupt %d vector %d!\n", irq, vector);
apic_eoi();
-#ifdef __scc__
- // Gotta reset the line
- rck_reset_lint1();
-#endif
send_user_interrupt(irq);
}
#include <barrelfish_kpi/paging_arch.h>
#include <barrelfish_kpi/syscalls.h>
#include <target/x86/barrelfish_kpi/coredata_target.h>
-#ifdef __scc__
-# include <rck.h>
-#endif
#include <arch/x86/startup_x86.h>
/// Quick way to find the base address of a cnode capability
{
errval_t err;
-#ifndef __scc__
// map first meg of RAM, which contains lots of crazy BIOS tables
err = create_caps_to_cnode(0, X86_32_START_KERNEL_PHYS,
RegionType_PlatformData, &spawn_state, bootinfo);
assert(err_is_ok(err));
-#endif
/* Walk multiboot MMAP structure, and create appropriate caps for memory */
char *mmap_addr = MBADDR_ASSTRING(glbl_core_data->mmap_addr);
}
#endif
-#ifndef __scc__
// XXX: Do not create ram caps for memory the kernel cannot
// address to prevent kernel objects from being created there
if(base_addr >= PADDR_SPACE_LIMIT) {
if (end_addr > PADDR_SPACE_LIMIT) {
end_addr = PADDR_SPACE_LIMIT;
}
-#endif
debug(SUBSYS_STARTUP, "RAM %llx--%llx\n", base_addr, end_addr);
const char *argv[6] = { "init", bootinfochar };
int argc = 2;
-#ifdef __scc__
- if(glbl_core_data->urpc_frame_base != 0) {
- char coreidchar[10];
- snprintf(coreidchar, sizeof(coreidchar), "%d",
- glbl_core_data->src_core_id);
- argv[argc++] = coreidchar;
-
- char chan_id_char[30];
- snprintf(chan_id_char, sizeof(chan_id_char), "chanid=%"PRIu32,
- glbl_core_data->chan_id);
- argv[argc++] = chan_id_char;
-
- char urpc_frame_base_char[30];
- snprintf(urpc_frame_base_char, sizeof(urpc_frame_base_char),
- "frame=%" PRIuGENPADDR, glbl_core_data->urpc_frame_base);
- argv[argc++] = urpc_frame_base_char;
- }
-#endif
-
struct dcb *init_dcb = spawn_init_common(&spawn_state, name, argc, argv,
bootinfo_phys, alloc_phys);
/* bootinfo->regions[i].mr_bits); */
/* } */
-#if 0
- // If app core, map (static) URPC channel
- if(kernel_scckernel != 0) {
- printf("SCC app kernel, frame at: 0x%x\n", kernel_scckernel);
-#define TASKCN_SLOT_MON_URPC (TASKCN_SLOTS_USER+6) ///< Frame cap for urpc comm.
-
- err = caps_create_new(ObjType_Frame, kernel_scckernel, 13, 13,
- caps_locate_slot(CNODE(taskcn), TASKCN_SLOT_MON_URPC));
- assert(err_is_ok(err));
- }
-#endif
-
return init_dcb;
}
const char *argv[5] = { name, coreidchar, chanidchar, archidchar };
int argc = 4;
-#ifdef __scc__
- char urpc_frame_base_char[30];
- snprintf(urpc_frame_base_char, sizeof(urpc_frame_base_char),
- "frame=%" PRIuGENPADDR, core_data->urpc_frame_base);
- argv[argc++] = urpc_frame_base_char;
-#endif
-
struct dcb *init_dcb = spawn_init_common(&spawn_state, name, argc, argv,
0, alloc_phys);
#include <fpu.h>
#include <mdb/mdb_tree.h>
#include <useraccess.h>
-#ifdef __scc__
-# include <rck.h>
-#else
-# include <arch/x86/perfmon_amd.h>
-# include <arch/x86/ipi_notify.h>
-#endif
+#include <arch/x86/perfmon_amd.h>
+#include <arch/x86/ipi_notify.h>
/* FIXME: lots of missing argument checks in this function */
static struct sysret handle_dispatcher_setup(struct capability *to,
return sys_monitor_register(ep_caddr);
}
-#ifdef __scc__
-static struct sysret monitor_spawn_scc_core(struct capability *kernel_cap,
- int cmd, uintptr_t *args)
-{
- uint8_t id = args[1] >> 24;
- genpaddr_t urpcframe_base = args[0];
- uint8_t urpcframe_bits = (args[1] >> 16) & 0xff;
- int chanid = args[1] & 0xffff;
-
- int r = rck_start_core(id, urpcframe_base, urpcframe_bits, chanid);
-
- if (r != 0) {
- return SYSRET(SYS_ERR_CORE_NOT_FOUND);
- }
-
- return SYSRET(SYS_ERR_OK);
-}
-#endif
-
static struct sysret monitor_get_core_id(struct capability *kernel_cap,
int cmd, uintptr_t *args)
{
};
}
-#ifdef __scc__
-static struct sysret handle_frame_scc_identify(struct capability *to,
- int cmd, uintptr_t *args)
-{
- // Return with physical base address of frame
- // XXX: pack size into bottom bits of base address
- assert(to->type == ObjType_Frame || to->type == ObjType_DevFrame);
- assert((to->u.frame.base & BASE_PAGE_MASK) == 0);
- assert(to->u.frame.bits < BASE_PAGE_SIZE);
-
- uint8_t route, subdest;
- uint16_t addrbits;
-
- errval_t err = rck_get_route(to->u.frame.base, 1 << to->u.frame.bits,
- &route, &subdest, &addrbits);
- if(err_is_fail(err)) {
- return SYSRET(err);
- }
-
- return (struct sysret) {
- .error = SYS_ERR_OK,
- .value = (addrbits << 16) | (subdest << 8) | route,
- };
-}
-#endif
-
static struct sysret handle_io(struct capability *to, int cmd, uintptr_t *args)
{
uint32_t port = args[0];
return sysret;
}
-#ifdef __scc__
-static struct sysret kernel_rck_register(struct capability *cap,
- int cmd, uintptr_t *args)
-{
- capaddr_t ep = args[0];
- int chanid = args[1];
- return SYSRET(rck_register_notification(ep, chanid));
-}
-
-static struct sysret kernel_rck_delete(struct capability *cap,
- int cmd, uintptr_t *args)
-{
- int chanid = args[0];
- return SYSRET(rck_delete_notification(chanid));
-}
-
-static struct sysret handle_rck_notify_send(struct capability *cap,
- int cmd, uintptr_t *args)
-{
- assert(cap->type == ObjType_Notify_RCK);
- rck_send_notification(cap->u.notify_rck.coreid, cap->u.notify_rck.chanid);
- return SYSRET(SYS_ERR_OK);
-}
-
-#else
-
static struct sysret kernel_ipi_register(struct capability *cap,
int cmd, uintptr_t *args)
{
assert(cap->type == ObjType_Notify_IPI);
return ipi_raise_notify(cap->u.notify_ipi.coreid, cap->u.notify_ipi.chanid);
}
-#endif
static struct sysret dispatcher_dump_ptables(struct capability *cap,
int cmd, uintptr_t *args)
[ObjType_Frame] = {
[FrameCmd_Identify] = handle_frame_identify,
[FrameCmd_ModifyFlags] = handle_frame_modify_flags,
-#ifdef __scc__
- [FrameCmd_SCC_Identify] = handle_frame_scc_identify
-#endif
},
[ObjType_DevFrame] = {
[FrameCmd_Identify] = handle_frame_identify,
[FrameCmd_ModifyFlags] = handle_frame_modify_flags,
-#ifdef __scc__
- [FrameCmd_SCC_Identify] = handle_frame_scc_identify
-#endif
},
[ObjType_CNode] = {
[CNodeCmd_Copy] = handle_copy,
[KernelCmd_Delete_step] = monitor_handle_delete_step,
[KernelCmd_Clear_step] = monitor_handle_clear_step,
[KernelCmd_Sync_timer] = monitor_handle_sync_timer,
-#ifdef __scc__
- [KernelCmd_Spawn_SCC_Core] = monitor_spawn_scc_core,
- [KernelCmd_IPI_Register] = kernel_rck_register,
- [KernelCmd_IPI_Delete] = kernel_rck_delete,
-#else
[KernelCmd_IPI_Register] = kernel_ipi_register,
[KernelCmd_IPI_Delete] = kernel_ipi_delete,
-#endif
[KernelCmd_GetGlobalPhys] = kernel_get_global_phys,
[KernelCmd_Add_kcb] = kernel_add_kcb,
[KernelCmd_Remove_kcb] = kernel_remove_kcb,
[ObjType_ID] = {
[IDCmd_Identify] = handle_idcap_identify
},
-#ifdef __scc__
- [ObjType_Notify_RCK] = {
- [NotifyCmd_Send] = handle_rck_notify_send
- }
-#else
[ObjType_Notify_IPI] = {
[NotifyCmd_Send] = handle_ipi_notify_send
}
-#endif
};
/* syscall C entry point; called only from entry.S so no prototype in header */
}
}
-#ifdef __scc__
-struct dcb *run_next = NULL;
-#endif
-
#if CONFIG_TRACE && NETWORK_STACK_BENCHMARK
#define TRACE_N_BM 1
#endif // CONFIG_TRACE && NETWORK_STACK_BENCHMARK
wait_for_interrupt();
}
- // XXX: run_next scheduling hack
-#ifdef __scc__
- if(run_next != NULL) {
- dcb = run_next;
- run_next = NULL;
- }
-#endif
-
// Don't context switch if we are current already
if (dcb_current != dcb) {
void conio_putchar(char c);
void conio_relocate_vidmem(lvaddr_t newaddr);
-#ifdef __scc__
-void klog_init(void);
-#endif
-
#endif
static inline int
kputchar(int c)
{
-#ifndef __scc__
if (c == '\n') {
serial_console_putchar('\r');
//delay(200000000);
}
conio_putchar(c);
-#endif
serial_console_putchar(c);
return c;
}
#define DISPATCHER_BASE (ARGS_BASE + ARGS_SIZE)
#define MON_URPC_BASE (DISPATCHER_BASE + DISPATCHER_SIZE)
-#ifdef __scc__
-extern int kernel_scckernel;
-#endif
-
errval_t startup_map_init(lvaddr_t vbase, lpaddr_t base, size_t size,
uint32_t flags);
errval_t startup_alloc_init(void *state, genvaddr_t gvbase, size_t size,
local_phys_to_mem((lpaddr_t)&x86_64_init_ap_wait - ((lpaddr_t)&x86_64_start_ap) +
X86_64_REAL_MODE_LINEAR_OFFSET);
#elif defined (__i386__)
-# if !defined(__scc__)
volatile uint32_t *ap_wait = (volatile uint32_t *)
local_phys_to_mem((lpaddr_t)&x86_32_init_ap_wait - ((lpaddr_t)&x86_32_start_ap) +
X86_32_REAL_MODE_LINEAR_OFFSET);
-# endif
#else
#error "Architecture not supported"
#endif
static inline void enable_fpu(void)
{
uint32_t cr0;
-#ifndef __scc__
uint32_t cr4;
-#endif
__asm__ __volatile__("mov %%cr0, %%eax" : "=a" (cr0) : );
//clear EM
cr0 &= ~(1 << 2);
cr0 &= ~(1 << 3);
#endif
__asm__ __volatile__("mov %%eax,%%cr0" : : "a" (cr0));
-#ifndef __scc__
//set OSFXSR
__asm__ __volatile__("mov %%cr4, %%eax" : "=a" (cr4) : );
cr4 |= (1 << 9);
__asm__ __volatile__("mov %%eax,%%cr4" : : "a" (cr4));
-#endif
#ifndef FPU_LAZY_CONTEXT_SWITCH
__asm volatile ("finit");
+++ /dev/null
-/**
- * \file
- * \brief Data sent to a newly booted SCC kernel by the bootloader
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, 2011, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef DITEINFO_H
-#define DITEINFO_H
-
-#ifndef __ASSEMBLER__
-
-struct diteinfo_modinfo {
- uint32_t mod_start;
- uint32_t mod_end;
- uint32_t string;
- uint32_t reserved;
-};
-
-struct diteinfo_mmap {
- uint32_t size;
- uint64_t base_addr;
- uint64_t length;
- uint32_t type;
-} __attribute__ ((packed));
-
-struct diteinfo_elf {
- uint32_t num;
- uint32_t size;
- uint32_t addr;
- uint32_t shndx;
-};
-
-struct diteinfo {
- struct diteinfo_elf elf;
- uint32_t cmdline;
- uint32_t mods_count;
- uint32_t mods_addr;
- uint32_t mmap_length;
- uint32_t mmap_addr;
- uint32_t start_free_ram;
-
- // XXX: Remove this once app core boot protocol stabilizes
- genpaddr_t urpc_frame_base;
- uint8_t urpc_frame_bits;
- coreid_t src_core_id;
- uint32_t chan_id;
-
- struct diteinfo_modinfo modinfo[20];
- struct diteinfo_mmap mmap[20];
-
- char sh[2048];
- char strings[1024];
-} __attribute__ ((packed));
-
-#endif
-
-#define DITEINFO_SIZE 4096
-
-#define DITE_BOOT_MAGIC 0xd11eb001
-
-#endif
* for a bigger device address space. We set this to one page, so the APIC
* driver can do its job.
*/
-#ifdef __scc__
-//# define X86_32_DEVICE_SPACE_LIMIT (148 * X86_32_MEM_PAGE_SIZE)
-# define X86_32_DEVICE_SPACE_LIMIT (196 * X86_32_MEM_PAGE_SIZE)
-#else
-# define X86_32_DEVICE_SPACE_LIMIT (1 * X86_32_MEM_PAGE_SIZE)
-#endif
+#define X86_32_DEVICE_SPACE_LIMIT (1 * X86_32_MEM_PAGE_SIZE)
/**
* Static virtual address space limit for the init user-space
#include <stdio.h>
#include <string.h>
#include <barrelfish/bulk_transfer.h>
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-#endif
/**
* \brief Destroy bulk data transport on shared memory region
* \param block_size Size in bytes of a buffer block
* \param shared_mem Return parameter to allocated shared memory capability
* \param bt Pointer to bulk transfer state to be filled
- * \param LMP_only States that this bulk transfer will be used on in LMP (
- * Only applicable to SCC )
*
* \return Error value.
*/
errval_t bulk_create(size_t size, size_t block_size, struct capref *shared_mem,
- struct bulk_transfer *bt, bool LMP_only)
+ struct bulk_transfer *bt)
{
// Create a Frame Capability
size_t allocated_size;
-#ifdef __scc__
- if (LMP_only) {
- ram_set_affinity(0x0, PRIVATE_MEM_MAX);
- } else {
-
- ram_set_affinity(SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-/* printf("^^^^ bulk transfer affinities %"PRIx32", %"PRIx32" \n",
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-*/
- }
-
-#endif
errval_t r = frame_alloc(shared_mem, size, &allocated_size);
-#ifdef __scc__
- ram_set_affinity(0, 0);
-#endif
if (err_is_fail(r)) {
return err_push(r, LIB_ERR_FRAME_ALLOC);
}
// Map the frame in local memory
void *pool;
-#ifdef __scc__
- r = vspace_map_one_frame_attr(&pool, allocated_size, *shared_mem,
- VREGION_FLAGS_READ_WRITE_MPB, NULL, NULL);
-#else
r = vspace_map_one_frame(&pool, allocated_size, *shared_mem, NULL, NULL);
-#endif
if (err_is_fail(r)) {
cap_destroy(*shared_mem);
return err_push(r, LIB_ERR_VSPACE_MAP);
#endif
#if defined(__GNUC__) && !defined(__clang__) && !defined(__ICC) \
- && (defined(__x86_64__) || (defined(__i386__) && !defined(__scc__)))
+ && (defined(__x86_64__) || (defined(__i386__)))
// Disable SSE/MMX -- this code context switches those registers
# pragma GCC target ("no-mmx,no-sse,no-sse2,no-sse3,no-sse4.1,no-sse4.2,no-sse4,no-sse4a,no-3dnow")
#endif
// PA4 is configured as write-combining
pmap_flags |= PTABLE_ATTR_INDEX;
}
-#ifdef __scc__
- if (vregion_flags & VREGION_FLAGS_MPB) {
- pmap_flags |= SCC_PTABLE_MESSAGE_BUFFER;
- pmap_flags |= X86_32_PTABLE_WRITE_THROUGH;
- }
-#endif
}
return pmap_flags;
#include <barrelfish/idc_export.h>
#include <if/monitor_defs.h>
-/* UMP channels need to be mapped non-cacheable on SCC */
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-/* # define UMP_MAP_ATTR VREGION_FLAGS_READ_WRITE_NOCACHE */
-# define UMP_MAP_ATTR VREGION_FLAGS_READ_WRITE_MPB
-#else
-# define UMP_MAP_ATTR VREGION_FLAGS_READ_WRITE
-#endif
+#define UMP_MAP_ATTR VREGION_FLAGS_READ_WRITE
#ifndef CONFIG_INTERCONNECT_DRIVER_UMP
#error "This file shouldn't be compiled without CONFIG_INTERCONNECT_DRIVER_UMP"
// compute size of frame needed and allocate it
size_t framesize = inchanlen + outchanlen;
-#ifdef __scc__
- ram_set_affinity(SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-#endif
err = frame_alloc(&uc->frame, framesize, &framesize);
if (err_is_fail(err)) {
return err_push(err, LIB_ERR_FRAME_ALLOC);
}
-#ifdef __scc__
- ram_set_affinity(0, 0);
-#endif
// map it in
void *buf;
#define MACHINE_CLK_UNIT (1000000)
-#if !defined(__scc__)
#define MACHINE_CLOCK_SPEED (2800)
-#else
-#define MACHINE_CLOCK_SPEED (533)
-#endif // !defined(__scc__)
#define IN_SECONDS(x) (((x)/(MACHINE_CLOCK_SPEED))/(MACHINE_CLK_UNIT))
#define CONVERT_TO_SEC
/* FIXME: hardcoding the NIC card right now, will do smarter detection
in future. */
-#ifndef __scc__
#ifdef CONFIG_QEMU_NETWORK
card_name = "rtl8029";
#else
//card_name = "e10k";
//card_name = "vmkitmon_eth";
#endif // CONFIG_QEMU_NETWORK
-#else
- static char cid[100];
-
- snprintf(cid, sizeof(cid), "eMAC2_%u", disp_get_core_id());
- card_name = cid;
-#endif // __scc__
return lwip_init_ex(card_name, default_queueid, opt_waitset, opt_mutex);
} // end function: lwip_init_auto_ex
DEBUG("-> picked %" PRIuCSLOT " (%" PRIxGENPADDR "-%" PRIxGENPADDR ")\n", nchild,
*nodebase, *nodebase + UNBITS_GENPA(*nodesizebits));
-#ifdef __scc__
- // XXX: Debug in case memory allocation blows up on SCC
- if(minbase + UNBITS_GENPA(sizebits) > *nodebase + UNBITS_GENPA(*nodesizebits)) {
- printf("minbase = 0x%" PRIxGENPADDR ", size = %" PRIuGENPADDR
- ", nodebase = 0x%" PRIxGENPADDR ", nodesize = %" PRIuGENPADDR
- ", left sum = 0x%" PRIxGENPADDR ", right sum = %" PRIxGENPADDR "\n",
- minbase, UNBITS_GENPA(sizebits), *nodebase, UNBITS_GENPA(*nodesizebits),
- minbase + UNBITS_GENPA(sizebits), *nodebase + UNBITS_GENPA(*nodesizebits));
- }
-#endif
-
assert(minbase + UNBITS_GENPA(sizebits) <= *nodebase + UNBITS_GENPA(*nodesizebits));
assert(maxlimit - UNBITS_GENPA(sizebits) >= *nodebase);
assert(retnode != NULL);
NDM_DEBUG("SCMWFM: allocating %lu bytes of memory.\n", size);
-#ifdef __scc__
- err = bulk_create(total_size, size, &frame, &bt_filter_tx, true);
-#else
- err = bulk_create(total_size, size, &frame, &bt_filter_tx, false);
-#endif
+ err = bulk_create(total_size, size, &frame, &bt_filter_tx);
assert(err_is_ok(err));
buffer->pa = pa.base;
buffer->bits = pa.bits;
-#ifdef __scc__
- err = vspace_map_one_frame_attr(&buffer->va, (1L << buffer->bits), cap,
- VREGION_FLAGS_READ_WRITE_MPB, NULL, NULL);
-#else
err = vspace_map_one_frame(&buffer->va, (1L << buffer->bits), cap,
NULL, NULL);
-#endif
/*
err = vspace_map_one_frame_attr(&buffer->va, (1L << buffer->bits), cap,
void *
memcpy_fast(void *dst0, const void *src0, size_t length)
{
-// return memcpy(dst0, src0, length);
-#if defined(__scc__) && defined(SCC_MEMCPY)
- return memcpy_scc2(dst0, src0, length);
-#else // defined(__scc__) && defined(SCC_MEMCPY)
return memcpy(dst0, src0, length);
-#endif // defined(__scc__) && defined(SCC_MEMCPY)
}
-
-#include <string.h>
-#include <stdint.h>
-
-
-#if defined(__scc__)
-#ifdef SCC_MEMCPY
-/// XXX: Compile without -fPIE !
-
-/****************************************************************************************
- * Put data into communication buffer.
- ****************************************************************************************
- *
- * Author: Stefan Lankes, Carsten Clauss
- * Chair for Operating Systems, RWTH Aachen University
- * Date: 11/03/2010
- *
- ****************************************************************************************
- *
- * Written by the Chair for Operating Systems, RWTH Aachen University
- *
- * NO Copyright (C) 2010, Stefan Lankes, Carsten Clauss,
- * consider these trivial functions to be public domain.
- *
- * These functions are distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- */
-
-/*
- * A write access, which cache line is not present, doesn't perform (on the
- * current SCC architecture) a cache line fill. Therefore, the core writes
- * in this case directly to the memory.
- *
- * The following function copies from the on-die memory (MPB) to the off-die
- * memory and prefetchs its destintation. Therefore, the function avoids the
- * bad behavior of a "write miss".
- */
-void *memcpy_scc1(void *dest, const void *src, size_t count)
-{
- int h, i, j, k, l, m;
-
- __asm volatile ("cld;\n\t"
- "1: cmpl $0, %%eax ; je 2f\n\t"
- "movl (%%edi), %%edx\n\t"
- "movl 0(%%esi), %%ecx\n\t"
- "movl 4(%%esi), %%edx\n\t"
- "movl %%ecx, 0(%%edi)\n\t"
- "movl %%edx, 4(%%edi)\n\t"
- "movl 8(%%esi), %%ecx\n\t"
- "movl 12(%%esi), %%edx\n\t"
- "movl %%ecx, 8(%%edi)\n\t"
- "movl %%edx, 12(%%edi)\n\t"
- "movl 16(%%esi), %%ecx\n\t"
- "movl 20(%%esi), %%edx\n\t"
- "movl %%ecx, 16(%%edi)\n\t"
- "movl %%edx, 20(%%edi)\n\t"
- "movl 24(%%esi), %%ecx\n\t"
- "movl 28(%%esi), %%edx\n\t"
- "movl %%ecx, 24(%%edi)\n\t"
- "movl %%edx, 28(%%edi)\n\t"
- "addl $32, %%esi\n\t"
- "addl $32, %%edi\n\t"
- "dec %%eax ; jmp 1b\n\t"
- "2: movl %%ebx, %%ecx\n\t"
- "movl (%%edi), %%edx\n\t"
- "andl $31, %%ecx\n\t"
- "rep ; movsb\n\t":"=&a" (h), "=&D"(i), "=&S"(j), "=&b"(k),
- "=&c"(l), "=&d"(m)
- :"0"(count / 32), "1"(dest), "2"(src),
- "3"(count):"memory");
-
- return dest;
-}
-
-/*
- * If the destination is located on on-die memory (MPB), classical prefetching
- * techniques will be used to increase the performance.
- */
-void *memcpy_scc2(void *dest, const void *src, size_t count)
-{
- int i, j, k, l;
-
- /*
- * We use the floating point registers to
- * prefetch up to 4096 = (DCACE_SIZE (16KB) / 4) bytes.
- */
- __asm volatile ("cmpl $63,%%ecx\n\t"
- "jbe 1f\n\t"
- "4: pushl %%ecx\n\t"
- "cmpl $4096, %%ecx\n\t"
- "jbe 2f\n\t"
- "movl $4096,%%ecx\n\t"
- "2: subl %%ecx,0(%%esp)\n\t"
- "cmpl $256,%%ecx\n\t"
- "jb 5f\n\t"
- "pushl %%esi\n\t"
- "pushl %%ecx\n\t"
- ".align 4,0x90\n\t"
- "3: movl 0(%%esi),%%eax\n\t"
- "movl 32(%%esi),%%eax\n\t"
- "movl 64(%%esi),%%eax\n\t"
- "movl 96(%%esi),%%eax\n\t"
- "movl 128(%%esi),%%eax\n\t"
- "movl 160(%%esi),%%eax\n\t"
- "movl 192(%%esi),%%eax\n\t"
- "movl 224(%%esi),%%eax\n\t"
- "addl $256,%%esi\n\t"
- "subl $256,%%ecx\n\t"
- "cmpl $256,%%ecx\n\t"
- "jae 3b\n\t"
- "popl %%ecx\n\t"
- "popl %%esi\n\t"
- ".align 2,0x90\n\t"
- "5: fildq 0(%%esi)\n\t"
- "fildq 8(%%esi)\n\t"
- "fildq 16(%%esi)\n\t"
- "fildq 24(%%esi)\n\t"
- "fildq 32(%%esi)\n\t"
- "fildq 40(%%esi)\n\t"
- "fildq 48(%%esi)\n\t"
- "fildq 56(%%esi)\n\t"
- "fistpq 56(%%edi)\n\t"
- "fistpq 48(%%edi)\n\t"
- "fistpq 40(%%edi)\n\t"
- "fistpq 32(%%edi)\n\t"
- "fistpq 24(%%edi)\n\t"
- "fistpq 16(%%edi)\n\t"
- "fistpq 8(%%edi)\n\t"
- "fistpq 0(%%edi)\n\t"
- "addl $-64,%%ecx\n\t"
- "addl $64,%%esi\n\t"
- "addl $64,%%edi\n\t"
- "cmpl $63,%%ecx\n\t"
- "ja 5b\n\t"
- "popl %%eax\n\t"
- "addl %%eax,%%ecx\n\t"
- "cmpl $64,%%ecx\n\t"
- "jae 4b\n\t"
- "1: movl %%ecx,%%eax\n\t"
- "shrl $2,%%ecx\n\t"
- "cld ; rep ; movsl\n\t"
- "movl %%eax,%%ecx\n\t"
- "andl $3,%%ecx\n\t"
- "rep ; movsb\n\t":"=&c" (i), "=&D"(j), "=&S"(k), "=&a"(l)
- :"0"(count), "1"(dest), "2"(src)
- :"memory");
-
- return dest;
-}
-
-#endif // SCC_MEMCPY
-#endif // defined(__scc__)
-
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
-//#include <string.h>
-//#include <stdint.h>
+#include <string.h>
+#include <stdint.h>
/*
* sizeof(word) MUST BE A POWER OF TWO
# define CURRENT_CPU_TYPE_STR "x86_64"
#elif CURRENT_CPU_TYPE == CPU_X86_32
# define CURRENT_CPU_TYPE_STR "x86_32"
-#elif CURRENT_CPU_TYPE == CPU_SCC
-# define CURRENT_CPU_TYPE_STR "scc"
#elif CURRENT_CPU_TYPE == CPU_ARM5
# define CURRENT_CPU_TYPE_STR "armv5"
#elif CURRENT_CPU_TYPE == CPU_ARM7
mfence();
#endif
/*
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(reg, CACHESIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
*/
}
// 3 mfence
// been modified to suit the shared buffer allocation
// FIXME: code repetation with mem_barrelfish_alloc_and_register
struct bulk_transfer bt_sp;
-#ifdef __scc__
- err = bulk_create(mem_size, sizeof(union slot), &(spp->cap), &bt_sp, true);
-#else
- err = bulk_create(mem_size, sizeof(union slot), &(spp->cap), &bt_sp, false);
-#endif
+ err = bulk_create(mem_size, sizeof(union slot), &(spp->cap), &bt_sp);
if (err_is_fail(err)) {
DEBUG_ERR(err, "bulk_create failed.");
return NULL;
#endif
// copy the s into shared_pool
#if 0
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[id], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
#endif // 0
}
sp_copy_slot_data(&spp->sp->slot_list[wi].d, d);
#if 0
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[wi], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
#endif // 0
// Incrementing write pointer
sp_copy_slot_data(&spp->sp->slot_list[idx].d, d);
#if 0
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[idx], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
#endif // 0
// Incrementing write pointer
spp->ghost_write_id = (idx + 1) % spp->c_size;
// Copying the slot data contents into provided slot
/*
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[spp->ghost_read_id], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
*/
sp_copy_slot_data(dst, &spp->sp->slot_list[spp->ghost_read_id].d);
/* printf("After copying data from id %"PRIu64"\n", spp->ghost_read_id);
// swapping the slot_data contents between ri and new_slot
struct slot_data tmp;
#if 0
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[ri], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
#endif // 0
sp_copy_slot_data(&tmp, &spp->sp->slot_list[ri].d);
sp_copy_slot_data(&spp->sp->slot_list[ri].d, new_slot);
sp_copy_slot_data(new_slot, &tmp);
#if 0
-#if !defined(__scc__) && !defined(__i386__)
+#if !defined(__i386__)
cache_flush_range(&spp->sp->slot_list[ri], SLOT_SIZE);
-#endif // !defined(__scc__) && !defined(__i386__)
+#endif // !defined(__i386__)
#endif // 0
// Incrementing read index
if(!sp_set_read_index(spp, ((ri + 1) % spp->c_size))) {
#include <barrelfish/barrelfish.h>
#include <barrelfish/nameservice_client.h>
#include <barrelfish/spawn_client.h>
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-#endif
#include "internal.h"
// Create a Frame Capability
size_t allocated_size;
struct capref shared_mem;
-#ifdef __scc__
- ram_set_affinity(SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-#endif
errval_t r = frame_alloc(&shared_mem, BULK_SIZE * 2, &allocated_size);
assert(err_is_ok(r));
-#ifdef __scc__
- ram_set_affinity(0, 0);
-#endif
// Map the frame in local memory
void *pool;
break;
case CPU_X86_32:
- case CPU_SCC:
#ifdef CONFIG_PAE
err = vnode_create(si->vtree, ObjType_VNode_x86_32_pdpt);
#else
strcat(args, vaddr_char);
strcat(args, " ");
-#ifdef __scc__
- if(si->codeword == 0xcafebabe) {
- strcat(args, si->append_args);
- strcat(args, " ");
- }
-
- if(!strcmp(name, "scc/sbin/monitor")) {
- printf("starting monitor as '%s'\n", args);
- }
-#endif
-
// Multiboot args
char *multiboot_args;
err = spawn_get_cmdline_args(module, &multiboot_args);
#include <barrelfish/nameservice_client.h>
#include <barrelfish/bulk_transfer.h>
#include <vfs/vfs_path.h>
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-#endif
#include "vfs_backends.h"
#include "vfs_blockdevfs.h"
#include <if/trivfs_defs.h>
#include <if/trivfs_rpcclient_defs.h>
#include <if/monitor_defs.h>
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-#endif
#include "vfs_backends.h"
// Init bulk data lib
struct capref shared_frame;
err = bulk_create(BULK_MEM_SIZE, BULK_BLOCK_SIZE, &shared_frame,
- &client->bulk, false);
+ &client->bulk);
if(err_is_fail(err)) {
USER_PANIC_ERR(err, "bulk_create");
}
--
-- This file is distributed under the terms in the attached LICENSE file.
-- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Universitätstr. 6, CH-8092 Zurich. Attn: Systems Group.
+-- ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group.
--
-- Hakefile for /platforms/
--
"rtl8029",
"serial",
"sfxge",
- "sif",
"slideshow",
"sshd",
"vbe",
+++ /dev/null
-----------------------------------------------------------------------
--- Copyright (c) 2009, 2010, 2011, ETH Zurich.
--- All rights reserved.
---
--- This file is distributed under the terms in the attached LICENSE file.
--- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
---
--- Hakefile for dite
---
-----------------------------------------------------------------------
-
-[ compileNativeC "dite" ["dite.c", "elf32.c", "elf64.c"] ["-std=gnu99", "-g"] [] ]
+++ /dev/null
-/**
- * \file
- * \brief Boot image generation tool for non-Multiboot platforms.
- *
- * Not to be confused with the old UNSW/NICTA "dite" (DIT extended) tool, which
- * served a vaguely similar purpose but otherwise has nothing in common.
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, 2011, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <stdbool.h>
-#include <string.h>
-#include <assert.h>
-#include <ctype.h>
-#include <inttypes.h>
-#include <errno.h>
-
-typedef uint8_t coreid_t;
-
-#include "elf.h"
-#include "../../kernel/include/diteinfo.h"
-
-struct diteinfo cd;
-uint32_t cdbase;
-
-typedef union {
- struct Elf32_Ehdr *head32;
- struct Elf64_Ehdr *head64;
- void *ptr;
-} elf_ehdr_ptr_t;
-
-static genvaddr_t elf32_virtual_base(elf_ehdr_ptr_t ptr)
-{
- struct Elf32_Ehdr *ehead = ptr.head32;
- struct Elf32_Phdr *phead =
- (struct Elf32_Phdr *)((uintptr_t)ehead + (uintptr_t)ehead->e_phoff);
-
- genvaddr_t retval = 0;
- int i;
-
- for (i = 0; i < ehead->e_phnum; i++) {
- struct Elf32_Phdr *p = &phead[i];
- if (p->p_type == PT_LOAD) {
- if(retval == 0) {
- retval = p->p_vaddr;
- }
- retval = p->p_vaddr < retval ? p->p_vaddr : retval;
- }
- }
-
- return retval;
-}
-
-static genvaddr_t elf64_virtual_base(elf_ehdr_ptr_t ptr)
-{
- struct Elf64_Ehdr *ehead = ptr.head64;
- struct Elf64_Phdr *phead =
- (struct Elf64_Phdr *)((uintptr_t)ehead + (uintptr_t)ehead->e_phoff);
-
- genvaddr_t retval = 0;
- int i;
-
- for (i = 0; i < ehead->e_phnum; i++) {
- struct Elf64_Phdr *p = &phead[i];
- if (p->p_type == PT_LOAD) {
- if(retval == 0) {
- retval = p->p_vaddr;
- }
- retval = p->p_vaddr < retval ? p->p_vaddr : retval;
- }
- }
-
- return retval;
-}
-
-static size_t elf32_virtual_size(elf_ehdr_ptr_t ptr)
-{
- struct Elf32_Ehdr *ehead = ptr.head32;
- struct Elf32_Phdr *phead =
- (struct Elf32_Phdr *)((uintptr_t)ehead + (uintptr_t)ehead->e_phoff);
-
- size_t retval = 0;
- int i;
-
- for (i = 0; i < ehead->e_phnum; i++) {
- struct Elf32_Phdr *p = &phead[i];
- if (p->p_type == PT_LOAD) {
- retval = p->p_vaddr + p->p_memsz;
- }
- }
-
- return retval - elf32_virtual_base(ptr);
-}
-
-static size_t elf64_virtual_size(elf_ehdr_ptr_t ptr)
-{
- struct Elf64_Ehdr *ehead = ptr.head64;
- struct Elf64_Phdr *phead =
- (struct Elf64_Phdr *)((uintptr_t)ehead + (uintptr_t)ehead->e_phoff);
-
- size_t retval = 0;
- int i;
-
- for (i = 0; i < ehead->e_phnum; i++) {
- struct Elf64_Phdr *p = &phead[i];
- if (p->p_type == PT_LOAD) {
- retval = p->p_vaddr + p->p_memsz;
- }
- }
-
- return retval - elf64_virtual_base(ptr);
-}
-
-static void elf32_fill_diteinfo(char *fbuf, genvaddr_t elfbase)
-{
- cd.elf.size = sizeof(struct Elf32_Shdr);
- struct Elf32_Ehdr *head32 = (struct Elf32_Ehdr *)fbuf;
- cd.elf.num = head32->e_shnum;
- cd.elf.addr = elfbase - DITEINFO_SIZE + __builtin_offsetof(struct diteinfo, sh);
-
- size_t sh_size = cd.elf.size * cd.elf.num;
- if(sh_size < 2048) {
- memcpy(cd.sh, fbuf + (uintptr_t)head32->e_shoff, sh_size);
- } else {
- printf("section header too big (size %lu)\n", sh_size);
- exit(1);
- }
-}
-
-static void elf64_fill_diteinfo(char *fbuf, genvaddr_t elfbase)
-{
- cd.elf.size = sizeof(struct Elf64_Shdr);
- struct Elf64_Ehdr *head64 = (struct Elf64_Ehdr *)fbuf;
- cd.elf.num = head64->e_shnum;
- cd.elf.addr = elfbase - DITEINFO_SIZE + __builtin_offsetof(struct diteinfo, sh);
-
- size_t sh_size = cd.elf.size * cd.elf.num;
- if(sh_size < 2048) {
- memcpy(cd.sh, fbuf + (uintptr_t)head64->e_shoff, sh_size);
- } else {
- printf("section header too big (size %lu)\n", sh_size);
- exit(1);
- }
-}
-
-struct monitor_allocate_state {
- void *vbase;
- genvaddr_t elfbase;
-};
-
-static errval_t elf_allocate(void *state, genvaddr_t base,
- size_t size, uint32_t flags,
- void **retbase)
-{
- struct monitor_allocate_state *s = state;
-
- *retbase = s->vbase + base - s->elfbase;
- return 0;
-}
-
-struct elf_funcs {
- genvaddr_t (*virtual_base)(elf_ehdr_ptr_t ehead);
- size_t (*virtual_size)(elf_ehdr_ptr_t ehead);
- errval_t (*load)(elf_allocator_fn allocate_func, void *state, lvaddr_t base,
- size_t size, genvaddr_t *retentry);
- void (*fill_diteinfo)(char *fbuf, genvaddr_t elfbase);
-};
-
-static const struct elf_funcs elf_funcs_32 = {
- .virtual_base = elf32_virtual_base,
- .virtual_size = elf32_virtual_size,
- .load = elf32_load,
- .fill_diteinfo = elf32_fill_diteinfo,
-};
-
-static const struct elf_funcs elf_funcs_64 = {
- .virtual_base = elf64_virtual_base,
- .virtual_size = elf64_virtual_size,
- .load = elf64_load,
- .fill_diteinfo = elf64_fill_diteinfo,
-};
-
-static const struct elf_funcs *elf_funcs;
-
-static void *preload_kernel(const char *filename, size_t *outsize)
-{
- // Preload kernel image
- FILE *f = fopen(filename, "r");
- assert(f != NULL);
- fseek(f, 0, SEEK_END);
- size_t filesize = ftell(f);
- fseek(f, 0, SEEK_SET);
- char *fbuf = malloc(filesize);
- fread(fbuf, filesize, 1, f);
- fclose(f);
-
- elf_ehdr_ptr_t ehdrp = { .ptr = fbuf };
- size_t size = elf_funcs->virtual_size(ehdrp);
- char *kernelbuf = malloc(size);
- struct monitor_allocate_state state = {
- .vbase = kernelbuf,
- .elfbase = elf_funcs->virtual_base(ehdrp)
- };
-
- genvaddr_t entry;
- int err = elf_funcs->load(elf_allocate, &state, (lvaddr_t)fbuf,
- filesize, &entry);
- if(err != 0) {
- printf("error! %d\n", err);
- exit(1);
- } else {
- printf("kernel entry point: 0x%" PRIx64 "\n", entry);
- printf("load image at: 0x%" PRIx64 "\n",
- state.elfbase - DITEINFO_SIZE);
- }
-
- elf_funcs->fill_diteinfo(fbuf, state.elfbase);
- cdbase = state.elfbase - DITEINFO_SIZE;
-
- free(fbuf);
- *outsize = size;
- return kernelbuf;
-}
-
-static void *load_module(const char *filename, size_t *outsize)
-{
- // Read file
- FILE *mbf = fopen(filename, "r");
- if(mbf == NULL) {
- fprintf(stderr, "file %s not found\n", filename);
- exit(EXIT_FAILURE);
- }
- fseek(mbf, 0, SEEK_END);
- size_t fsize = ftell(mbf);
- fseek(mbf, 0, SEEK_SET);
-
- void *dstbuf = malloc(fsize);
-
- // Load multiboot module
- fread(dstbuf, fsize, 1, mbf);
- fclose(mbf);
-
- *outsize = fsize;
- return dstbuf;
-}
-
-#define MAX_MODULES 20
-
-int main(int argc, char *argv[])
-{
- assert(sizeof(struct diteinfo) <= DITEINFO_SIZE);
-
- void *kernelbuf = NULL;
- char *image_output = NULL;
- /* char *header_output = NULL; */
- char *input = NULL;
-
- for (int i = 1; i < argc; i++) {
- if (strcmp(argv[i], "-32") == 0) {
- elf_funcs = &elf_funcs_32;
- } else if (strcmp(argv[i], "-64") == 0) {
- elf_funcs = &elf_funcs_64;
- } else if (strcmp(argv[i], "-o") == 0) {
- if (i == argc - 1) {
- goto usage;
- }
- image_output = argv[++i];
- /* } else if (strcmp(argv[i], "-h") == 0) { */
- /* if (i == argc - 1) { */
- /* goto usage; */
- /* } */
- /* header_output = argv[++i]; */
- } else if (argv[i][0] == '-') {
- goto usage;
- } else {
- input = argv[i];
- }
- }
-
- if (image_output == NULL || input == NULL || elf_funcs == NULL) {
-usage:
- printf("Usage: %s <-32|-64> [-o output] menu.lst\n", argv[0]);
- return -1;
- }
-
- FILE *f = fopen(input, "r");
- if(f == NULL) {
- fprintf(stderr, "%s: Could not open '%s': %s\n", argv[0], argv[1],
- strerror(errno));
- exit(EXIT_FAILURE);
- }
- char cmd[1024], args[1024], image[1024];
- void *module[MAX_MODULES];
- size_t sizemodule[MAX_MODULES], sizekernel, posmodule[MAX_MODULES];
- int modules = 0, mmaps = 0, fakemodules = 0;
- size_t bufsize = DITEINFO_SIZE;
- size_t fakebufsize = 0;
-
- while(!feof(f)) {
- char line[1024];
-
- cmd[0] = args[0] = image[0] = line[0] = '\0';
-
- fgets(line, 1024, f);
- sscanf(line, "%s %s %[^\n]", cmd, image, args);
-
- if(!strcmp(cmd, "kernel")) {
- kernelbuf = preload_kernel(image + 1, &sizekernel);
- bufsize += sizekernel;
-
- // Fill commandline args
- strcat(cd.strings, "\1");
- cd.cmdline = cdbase + __builtin_offsetof(struct diteinfo, strings) + strlen(cd.strings);
- strcat(cd.strings, image);
- strcat(cd.strings, " ");
- strcat(cd.strings, args);
- } else if(!strcmp(cmd, "module")) {
- assert(modules < MAX_MODULES);
- module[modules] = load_module(image + 1, &sizemodule[modules]);
- if(bufsize % 4096 != 0) {
- bufsize += 4096 - (bufsize % 4096);
- }
- posmodule[modules] = bufsize;
- bufsize += sizemodule[modules];
-
- struct diteinfo_modinfo *mi = &cd.modinfo[modules];
- mi->mod_start = posmodule[modules] + cdbase;
- mi->mod_end = bufsize - 1 + cdbase;
-
- // Fill commandline args
- strcat(cd.strings, "\1");
- mi->string = cdbase + __builtin_offsetof(struct diteinfo, strings) + strlen(cd.strings);
- strcat(cd.strings, image);
- if(strlen(args) > 0) {
- strcat(cd.strings, " ");
- strcat(cd.strings, args);
- }
-
- printf("Adding multiboot module '%s', args '%s' at [0x%x:0x%x]\n",
- image, args, mi->mod_start, mi->mod_end);
-
- modules++;
- } else if(!strcmp(cmd, "fake")) {
- if(fakemodules == 0) {
- fakemodules = modules;
- }
-
- assert(fakemodules < MAX_MODULES);
- module[fakemodules] = load_module(image + 1, &sizemodule[fakemodules]);
-
- if(fakebufsize == 0) {
- fakebufsize = bufsize;
- }
-
- if(fakebufsize % 4096 != 0) {
- fakebufsize += 4096 - (fakebufsize % 4096);
- }
-
- posmodule[fakemodules] = fakebufsize;
- fakebufsize += sizemodule[fakemodules];
-
- struct diteinfo_modinfo *mi = &cd.modinfo[fakemodules];
- mi->mod_start = posmodule[fakemodules] + cdbase;
- mi->mod_end = fakebufsize - 1 + cdbase;
-
- // Fill commandline args
- strcat(cd.strings, "\1");
- mi->string = cdbase + __builtin_offsetof(struct diteinfo, strings) + strlen(cd.strings);
- strcat(cd.strings, image);
- if(strlen(args) > 0) {
- strcat(cd.strings, " ");
- strcat(cd.strings, args);
- }
-
- printf("Faking multiboot module '%s', args '%s' at [0x%x:0x%x]\n",
- image, args, mi->mod_start, mi->mod_end);
-
- fakemodules++;
- } else if(!strcmp(cmd, "orig")) {
- unsigned int orig;
- sscanf(args, "%x", &orig);
- printf("New origin: 0x%x\n", orig);
- assert(bufsize + cdbase <= orig);
- bufsize = orig - cdbase;
- } else if(!strcmp(cmd, "mmap")) {
- if(mmaps >= 20) {
- printf("too many MMAPs\n");
- exit(1);
- }
-
- sscanf(args, "%" SCNi64 " %" SCNi64 " %i",
- &cd.mmap[mmaps].base_addr,
- &cd.mmap[mmaps].length,
- &cd.mmap[mmaps].type);
- cd.mmap[mmaps].size = sizeof(struct diteinfo_mmap) - 4;
-
- printf("Inserting MMAP %d: [0x%" PRIx64 ", 0x%" PRIx64 "], type %d\n",
- mmaps,
- cd.mmap[mmaps].base_addr,
- cd.mmap[mmaps].length,
- cd.mmap[mmaps].type);
-
- mmaps++;
- } else if(!strcmp(cmd, "output")) {
- printf("Warning: output statements are no longer supported; ignored\n");
- } else {
- bool iscmd = false;
- for(int i = 0; i < strlen(cmd); i++) {
- if(cmd[i] == '#') {
- break;
- }
- if(!isspace(cmd[i])) {
- iscmd = true;
- break;
- }
- }
- if(iscmd) {
- printf("Ignoring command '%s'\n", cmd);
- }
- }
- }
-
- fclose(f);
-
- // Concatenate all images
- char *dstbuf = malloc(bufsize);
- char *pos = dstbuf + DITEINFO_SIZE;
-
- if(fakebufsize == 0) {
- fakebufsize = bufsize;
- fakemodules = modules;
- }
-
- // Setup rest of core_data
- struct diteinfo *ccd = (struct diteinfo *)dstbuf;
- /* cd.multiboot_flags = MULTIBOOT_INFO_FLAG_HAS_ELF_SYMS | MULTIBOOT_INFO_FLAG_HAS_MEMINFO */
- /* | MULTIBOOT_INFO_FLAG_HAS_CMDLINE | MULTIBOOT_INFO_FLAG_HAS_MODS | MULTIBOOT_INFO_FLAG_HAS_MMAP; */
- cd.mmap_addr = cdbase + __builtin_offsetof(struct diteinfo, mmap);
- cd.mmap_length = sizeof(struct diteinfo_mmap) * mmaps;
- cd.mods_count = fakemodules;
- cd.mods_addr = cdbase + __builtin_offsetof(struct diteinfo, modinfo);
- cd.start_free_ram = cdbase + fakebufsize;
- if(cd.start_free_ram & 4095) {
- cd.start_free_ram += 4096 - (cd.start_free_ram & 4095);
- }
- assert(strlen(cd.strings) < 1024);
- for(int i = 0; i < 1024; i++) {
- if(cd.strings[i] == '\1') {
- cd.strings[i] = '\0';
- }
- }
- *ccd = cd;
-
- // Copy kernel
- memcpy(pos, kernelbuf, sizekernel);
-
- printf("writing %d modules ...\n", modules);
-
- // Concatenate all multiboot modules
- for(int i = 0; i < modules; i++) {
- pos = dstbuf + posmodule[i];
- memcpy(pos, module[i], sizemodule[i]);
- }
-
- if(image_output == NULL) {
- printf("No output image specified!\n");
- exit(1);
- }
-
- // Write output
- FILE *out = fopen(image_output, "w");
- assert(out != NULL);
- fwrite(dstbuf, bufsize, 1, f);
- fclose(out);
-
- free(dstbuf);
- return 0;
-}
+++ /dev/null
-/** \file
- * \brief ELF file format definitions
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-/*-
- * Copyright (c) 1998 John D. Polstra.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD: src/sys/sys/elf_common.h,v 1.23 2007/12/02 00:05:18 jb Exp $
- */
-
-#ifndef ELF_H
-#define ELF_H
-
-typedef uintptr_t lvaddr_t;
-typedef uint64_t genvaddr_t;
-typedef uint64_t genpaddr_t;
-typedef uintptr_t errval_t;
-
-#define PTABLE_USER_SUPERVISOR 0
-#define PTABLE_READ_WRITE 0
-#define PTABLE_EXECUTE_DISABLE 0
-
-/* Indexes into the e_ident array. Keep synced with
- http://www.sco.com/developers/gabi/latest/ch4.eheader.html */
-#define EI_MAG0 0 /* Magic number, byte 0. */
-#define EI_MAG1 1 /* Magic number, byte 1. */
-#define EI_MAG2 2 /* Magic number, byte 2. */
-#define EI_MAG3 3 /* Magic number, byte 3. */
-#define EI_CLASS 4 /* Class of machine. */
-#define EI_DATA 5 /* Data format. */
-#define EI_VERSION 6 /* ELF format version. */
-#define EI_OSABI 7 /* Operating system / ABI identification */
-#define EI_ABIVERSION 8 /* ABI version */
-#define OLD_EI_BRAND 8 /* Start of architecture identification. */
-#define EI_PAD 9 /* Start of padding (per SVR4 ABI). */
-#define EI_NIDENT 16 /* Size of e_ident array. */
-
-/* Values for the magic number bytes. */
-#define ELFMAG0 0x7f
-#define ELFMAG1 'E'
-#define ELFMAG2 'L'
-#define ELFMAG3 'F'
-#define ELFMAG "\177ELF" /* magic string */
-#define SELFMAG 4 /* magic string size */
-
-/* Values for e_ident[EI_VERSION] and e_version. */
-#define EV_NONE 0
-#define EV_CURRENT 1
-
-/* Values for e_ident[EI_CLASS]. */
-#define ELFCLASSNONE 0 /* Unknown class. */
-#define ELFCLASS32 1 /* 32-bit architecture. */
-#define ELFCLASS64 2 /* 64-bit architecture. */
-
-/* Values for e_ident[EI_DATA]. */
-#define ELFDATANONE 0 /* Unknown data format. */
-#define ELFDATA2LSB 1 /* 2's complement little-endian. */
-#define ELFDATA2MSB 2 /* 2's complement big-endian. */
-
-/* Values for e_ident[EI_OSABI]. */
-#define ELFOSABI_NONE 0 /* UNIX System V ABI */
-#define ELFOSABI_HPUX 1 /* HP-UX operating system */
-#define ELFOSABI_NETBSD 2 /* NetBSD */
-#define ELFOSABI_LINUX 3 /* GNU/Linux */
-#define ELFOSABI_HURD 4 /* GNU/Hurd */
-#define ELFOSABI_86OPEN 5 /* 86Open common IA32 ABI */
-#define ELFOSABI_SOLARIS 6 /* Solaris */
-#define ELFOSABI_AIX 7 /* AIX */
-#define ELFOSABI_IRIX 8 /* IRIX */
-#define ELFOSABI_FREEBSD 9 /* FreeBSD */
-#define ELFOSABI_TRU64 10 /* TRU64 UNIX */
-#define ELFOSABI_MODESTO 11 /* Novell Modesto */
-#define ELFOSABI_OPENBSD 12 /* OpenBSD */
-#define ELFOSABI_OPENVMS 13 /* Open VMS */
-#define ELFOSABI_NSK 14 /* HP Non-Stop Kernel */
-#define ELFOSABI_ARM 97 /* ARM */
-#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
-
-#define ELFOSABI_SYSV ELFOSABI_NONE /* symbol used in old spec */
-#define ELFOSABI_MONTEREY ELFOSABI_AIX /* Monterey */
-
-/* e_ident */
-#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
- (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
- (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
- (ehdr).e_ident[EI_MAG3] == ELFMAG3)
-
-/* Values for e_type. */
-#define ET_NONE 0 /* Unknown type. */
-#define ET_REL 1 /* Relocatable. */
-#define ET_EXEC 2 /* Executable. */
-#define ET_DYN 3 /* Shared object. */
-#define ET_CORE 4 /* Core file. */
-#define ET_LOOS 0xfe00 /* First operating system specific. */
-#define ET_HIOS 0xfeff /* Last operating system-specific. */
-#define ET_LOPROC 0xff00 /* First processor-specific. */
-#define ET_HIPROC 0xffff /* Last processor-specific. */
-
-/* Values for e_machine. */
-#define EM_NONE 0 /* Unknown machine. */
-#define EM_M32 1 /* AT&T WE32100. */
-#define EM_SPARC 2 /* Sun SPARC. */
-#define EM_386 3 /* Intel i386. */
-#define EM_68K 4 /* Motorola 68000. */
-#define EM_88K 5 /* Motorola 88000. */
-#define EM_860 7 /* Intel i860. */
-#define EM_MIPS 8 /* MIPS R3000 Big-Endian only. */
-#define EM_S370 9 /* IBM System/370. */
-#define EM_MIPS_RS3_LE 10 /* MIPS R3000 Little-Endian. */
-#define EM_PARISC 15 /* HP PA-RISC. */
-#define EM_VPP500 17 /* Fujitsu VPP500. */
-#define EM_SPARC32PLUS 18 /* SPARC v8plus. */
-#define EM_960 19 /* Intel 80960. */
-#define EM_PPC 20 /* PowerPC 32-bit. */
-#define EM_PPC64 21 /* PowerPC 64-bit. */
-#define EM_S390 22 /* IBM System/390. */
-#define EM_V800 36 /* NEC V800. */
-#define EM_FR20 37 /* Fujitsu FR20. */
-#define EM_RH32 38 /* TRW RH-32. */
-#define EM_RCE 39 /* Motorola RCE. */
-#define EM_ARM 40 /* ARM. */
-#define EM_SH 42 /* Hitachi SH. */
-#define EM_SPARCV9 43 /* SPARC v9 64-bit. */
-#define EM_TRICORE 44 /* Siemens TriCore embedded processor. */
-#define EM_ARC 45 /* Argonaut RISC Core. */
-#define EM_H8_300 46 /* Hitachi H8/300. */
-#define EM_H8_300H 47 /* Hitachi H8/300H. */
-#define EM_H8S 48 /* Hitachi H8S. */
-#define EM_H8_500 49 /* Hitachi H8/500. */
-#define EM_IA_64 50 /* Intel IA-64 Processor. */
-#define EM_MIPS_X 51 /* Stanford MIPS-X. */
-#define EM_COLDFIRE 52 /* Motorola ColdFire. */
-#define EM_68HC12 53 /* Motorola M68HC12. */
-#define EM_MMA 54 /* Fujitsu MMA. */
-#define EM_PCP 55 /* Siemens PCP. */
-#define EM_NCPU 56 /* Sony nCPU. */
-#define EM_NDR1 57 /* Denso NDR1 microprocessor. */
-#define EM_STARCORE 58 /* Motorola Star*Core processor. */
-#define EM_ME16 59 /* Toyota ME16 processor. */
-#define EM_ST100 60 /* STMicroelectronics ST100 processor. */
-#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ processor. */
-#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
-#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
-
-/* Non-standard or deprecated. */
-#define EM_486 6 /* Intel i486. */
-#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */
-#define EM_ALPHA_STD 41 /* Digital Alpha (standard value). */
-#define EM_ALPHA 0x9026 /* Alpha (written in the absence of an ABI) */
-
-/* Special section indexes. */
-#define SHN_UNDEF 0 /* Undefined, missing, irrelevant. */
-#define SHN_LORESERVE 0xff00 /* First of reserved range. */
-#define SHN_LOPROC 0xff00 /* First processor-specific. */
-#define SHN_HIPROC 0xff1f /* Last processor-specific. */
-#define SHN_LOOS 0xff20 /* First operating system-specific. */
-#define SHN_HIOS 0xff3f /* Last operating system-specific. */
-#define SHN_ABS 0xfff1 /* Absolute values. */
-#define SHN_COMMON 0xfff2 /* Common data. */
-#define SHN_XINDEX 0xffff /* Escape -- index stored elsewhere. */
-#define SHN_HIRESERVE 0xffff /* Last of reserved range. */
-
-/* sh_type */
-#define SHT_NULL 0 /* inactive */
-#define SHT_PROGBITS 1 /* program defined information */
-#define SHT_SYMTAB 2 /* symbol table section */
-#define SHT_STRTAB 3 /* string table section */
-#define SHT_RELA 4 /* relocation section with addends */
-#define SHT_HASH 5 /* symbol hash table section */
-#define SHT_DYNAMIC 6 /* dynamic section */
-#define SHT_NOTE 7 /* note section */
-#define SHT_NOBITS 8 /* no space section */
-#define SHT_REL 9 /* relocation section - no addends */
-#define SHT_SHLIB 10 /* reserved - purpose unknown */
-#define SHT_DYNSYM 11 /* dynamic symbol table section */
-#define SHT_INIT_ARRAY 14 /* Initialization function pointers. */
-#define SHT_FINI_ARRAY 15 /* Termination function pointers. */
-#define SHT_PREINIT_ARRAY 16 /* Pre-initialization function ptrs. */
-#define SHT_GROUP 17 /* Section group. */
-#define SHT_SYMTAB_SHNDX 18 /* Section indexes (see SHN_XINDEX). */
-#define SHT_LOOS 0x60000000 /* First of OS specific semantics */
-#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */
-#define SHT_LOPROC 0x70000000 /* reserved range for processor */
-#define SHT_AMD64_UNWIND 0x70000001 /* unwind information */
-#define SHT_HIPROC 0x7fffffff /* specific section header types */
-#define SHT_LOUSER 0x80000000 /* reserved range for application */
-#define SHT_HIUSER 0xffffffff /* specific indexes */
-
-/* Flags for sh_flags. */
-#define SHF_WRITE 0x1 /* Section contains writable data. */
-#define SHF_ALLOC 0x2 /* Section occupies memory. */
-#define SHF_EXECINSTR 0x4 /* Section contains instructions. */
-#define SHF_MERGE 0x10 /* Section may be merged. */
-#define SHF_STRINGS 0x20 /* Section contains strings. */
-#define SHF_INFO_LINK 0x40 /* sh_info holds section index. */
-#define SHF_LINK_ORDER 0x80 /* Special ordering requirements. */
-#define SHF_OS_NONCONFORMING 0x100 /* OS-specific processing required. */
-#define SHF_GROUP 0x200 /* Member of section group. */
-#define SHF_TLS 0x400 /* Section contains TLS data. */
-#define SHF_MASKOS 0x0ff00000 /* OS-specific semantics. */
-#define SHF_MASKPROC 0xf0000000 /* Processor-specific semantics. */
-
-/* Values for p_type. */
-#define PT_NULL 0 /* Unused entry. */
-#define PT_LOAD 1 /* Loadable segment. */
-#define PT_DYNAMIC 2 /* Dynamic linking information segment. */
-#define PT_INTERP 3 /* Pathname of interpreter. */
-#define PT_NOTE 4 /* Auxiliary information. */
-#define PT_SHLIB 5 /* Reserved (not used). */
-#define PT_PHDR 6 /* Location of program header itself. */
-#define PT_TLS 7 /* Thread local storage segment */
-#define PT_LOOS 0x60000000 /* First OS-specific. */
-#define PT_SUNW_UNWIND 0x6464e550 /* amd64 UNWIND program header */
-#define PT_GNU_EH_FRAME 0x6474e550
-#define PT_LOSUNW 0x6ffffffa
-#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */
-#define PT_SUNWSTACK 0x6ffffffb /* describes the stack segment */
-#define PT_SUNWDTRACE 0x6ffffffc /* private */
-#define PT_SUNWCAP 0x6ffffffd /* hard/soft capabilities segment */
-#define PT_HISUNW 0x6fffffff
-#define PT_HIOS 0x6fffffff /* Last OS-specific. */
-#define PT_LOPROC 0x70000000 /* First processor-specific type. */
-#define PT_HIPROC 0x7fffffff /* Last processor-specific type. */
-
-/* Values for p_flags. */
-#define PF_X 0x1 /* Executable. */
-#define PF_W 0x2 /* Writable. */
-#define PF_R 0x4 /* Readable. */
-#define PF_MASKOS 0x0ff00000 /* Operating system-specific. */
-#define PF_MASKPROC 0xf0000000 /* Processor-specific. */
-
-/* Extended program header index. */
-#define PN_XNUM 0xffff
-
-/* Values for d_tag. */
-#define DT_NULL 0 /* Terminating entry. */
-#define DT_NEEDED 1 /* String table offset of a needed shared
- library. */
-#define DT_PLTRELSZ 2 /* Total size in bytes of PLT relocations. */
-#define DT_PLTGOT 3 /* Processor-dependent address. */
-#define DT_HASH 4 /* Address of symbol hash table. */
-#define DT_STRTAB 5 /* Address of string table. */
-#define DT_SYMTAB 6 /* Address of symbol table. */
-#define DT_RELA 7 /* Address of ElfNN_Rela relocations. */
-#define DT_RELASZ 8 /* Total size of ElfNN_Rela relocations. */
-#define DT_RELAENT 9 /* Size of each ElfNN_Rela relocation entry. */
-#define DT_STRSZ 10 /* Size of string table. */
-#define DT_SYMENT 11 /* Size of each symbol table entry. */
-#define DT_INIT 12 /* Address of initialization function. */
-#define DT_FINI 13 /* Address of finalization function. */
-#define DT_SONAME 14 /* String table offset of shared object
- name. */
-#define DT_RPATH 15 /* String table offset of library path. [sup] */
-#define DT_SYMBOLIC 16 /* Indicates "symbolic" linking. [sup] */
-#define DT_REL 17 /* Address of ElfNN_Rel relocations. */
-#define DT_RELSZ 18 /* Total size of ElfNN_Rel relocations. */
-#define DT_RELENT 19 /* Size of each ElfNN_Rel relocation. */
-#define DT_PLTREL 20 /* Type of relocation used for PLT. */
-#define DT_DEBUG 21 /* Reserved (not used). */
-#define DT_TEXTREL 22 /* Indicates there may be relocations in
- non-writable segments. [sup] */
-#define DT_JMPREL 23 /* Address of PLT relocations. */
-#define DT_BIND_NOW 24 /* [sup] */
-#define DT_INIT_ARRAY 25 /* Address of the array of pointers to
- initialization functions */
-#define DT_FINI_ARRAY 26 /* Address of the array of pointers to
- termination functions */
-#define DT_INIT_ARRAYSZ 27 /* Size in bytes of the array of
- initialization functions. */
-#define DT_FINI_ARRAYSZ 28 /* Size in bytes of the array of
- terminationfunctions. */
-#define DT_RUNPATH 29 /* String table offset of a null-terminated
- library search path string. */
-#define DT_FLAGS 30 /* Object specific flag values. */
-#define DT_ENCODING 32 /* Values greater than or equal to DT_ENCODING
- and less than DT_LOOS follow the rules for
- the interpretation of the d_un union
- as follows: even == 'd_ptr', even == 'd_val'
- or none */
-#define DT_PREINIT_ARRAY 32 /* Address of the array of pointers to
- pre-initialization functions. */
-#define DT_PREINIT_ARRAYSZ 33 /* Size in bytes of the array of
- pre-initialization functions. */
-#define DT_MAXPOSTAGS 34 /* number of positive tags */
-#define DT_LOOS 0x6000000d /* First OS-specific */
-#define DT_SUNW_AUXILIARY 0x6000000d /* symbol auxiliary name */
-#define DT_SUNW_RTLDINF 0x6000000e /* ld.so.1 info (private) */
-#define DT_SUNW_FILTER 0x6000000f /* symbol filter name */
-#define DT_SUNW_CAP 0x60000010 /* hardware/software */
-#define DT_HIOS 0x6ffff000 /* Last OS-specific */
-
-/*
- * DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
- * Dyn.d_un.d_val field of the Elf*_Dyn structure.
- */
-#define DT_VALRNGLO 0x6ffffd00
-#define DT_CHECKSUM 0x6ffffdf8 /* elf checksum */
-#define DT_PLTPADSZ 0x6ffffdf9 /* pltpadding size */
-#define DT_MOVEENT 0x6ffffdfa /* move table entry size */
-#define DT_MOVESZ 0x6ffffdfb /* move table size */
-#define DT_FEATURE_1 0x6ffffdfc /* feature holder */
-#define DT_POSFLAG_1 0x6ffffdfd /* flags for DT_* entries, effecting */
- /* the following DT_* entry. */
- /* See DF_P1_* definitions */
-#define DT_SYMINSZ 0x6ffffdfe /* syminfo table size (in bytes) */
-#define DT_SYMINENT 0x6ffffdff /* syminfo entry size (in bytes) */
-#define DT_VALRNGHI 0x6ffffdff
-
-/*
- * DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
- * Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
- *
- * If any adjustment is made to the ELF object after it has been
- * built, these entries will need to be adjusted.
- */
-#define DT_ADDRRNGLO 0x6ffffe00
-#define DT_CONFIG 0x6ffffefa /* configuration information */
-#define DT_DEPAUDIT 0x6ffffefb /* dependency auditing */
-#define DT_AUDIT 0x6ffffefc /* object auditing */
-#define DT_PLTPAD 0x6ffffefd /* pltpadding (sparcv9) */
-#define DT_MOVETAB 0x6ffffefe /* move table */
-#define DT_SYMINFO 0x6ffffeff /* syminfo table */
-#define DT_ADDRRNGHI 0x6ffffeff
-
-#define DT_VERSYM 0x6ffffff0 /* Address of versym section. */
-#define DT_RELACOUNT 0x6ffffff9 /* number of RELATIVE relocations */
-#define DT_RELCOUNT 0x6ffffffa /* number of RELATIVE relocations */
-#define DT_FLAGS_1 0x6ffffffb /* state flags - see DF_1_* defs */
-#define DT_VERDEF 0x6ffffffc /* Address of verdef section. */
-#define DT_VERDEFNUM 0x6ffffffd /* Number of elems in verdef section */
-#define DT_VERNEED 0x6ffffffe /* Address of verneed section. */
-#define DT_VERNEEDNUM 0x6fffffff /* Number of elems in verneed section */
-
-#define DT_LOPROC 0x70000000 /* First processor-specific type. */
-#define DT_DEPRECATED_SPARC_REGISTER 0x7000001
-#define DT_AUXILIARY 0x7ffffffd /* shared library auxiliary name */
-#define DT_USED 0x7ffffffe /* ignored - same as needed */
-#define DT_FILTER 0x7fffffff /* shared library filter name */
-#define DT_HIPROC 0x7fffffff /* Last processor-specific type. */
-
-/* Values for DT_FLAGS */
-#define DF_ORIGIN 0x0001 /* Indicates that the object being loaded may
- make reference to the $ORIGIN substitution
- string */
-#define DF_SYMBOLIC 0x0002 /* Indicates "symbolic" linking. */
-#define DF_TEXTREL 0x0004 /* Indicates there may be relocations in
- non-writable segments. */
-#define DF_BIND_NOW 0x0008 /* Indicates that the dynamic linker should
- process all relocations for the object
- containing this entry before transferring
- control to the program. */
-#define DF_STATIC_TLS 0x0010 /* Indicates that the shared object or
- executable contains code using a static
- thread-local storage scheme. */
-
-/* Values for n_type. Used in core files. */
-#define NT_PRSTATUS 1 /* Process status. */
-#define NT_FPREGSET 2 /* Floating point registers. */
-#define NT_PRPSINFO 3 /* Process state info. */
-
-/* Symbol Binding - ELFNN_ST_BIND - st_info */
-#define STB_LOCAL 0 /* Local symbol */
-#define STB_GLOBAL 1 /* Global symbol */
-#define STB_WEAK 2 /* like global - lower precedence */
-#define STB_LOOS 10 /* Reserved range for operating system */
-#define STB_HIOS 12 /* specific semantics. */
-#define STB_LOPROC 13 /* reserved range for processor */
-#define STB_HIPROC 15 /* specific semantics. */
-
-/* Symbol type - ELFNN_ST_TYPE - st_info */
-#define STT_NOTYPE 0 /* Unspecified type. */
-#define STT_OBJECT 1 /* Data object. */
-#define STT_FUNC 2 /* Function. */
-#define STT_SECTION 3 /* Section. */
-#define STT_FILE 4 /* Source file. */
-#define STT_COMMON 5 /* Uninitialized common block. */
-#define STT_TLS 6 /* TLS object. */
-#define STT_NUM 7
-#define STT_LOOS 10 /* Reserved range for operating system */
-#define STT_HIOS 12 /* specific semantics. */
-#define STT_LOPROC 13 /* reserved range for processor */
-#define STT_HIPROC 15 /* specific semantics. */
-
-/* Symbol visibility - ELFNN_ST_VISIBILITY - st_other */
-#define STV_DEFAULT 0x0 /* Default visibility (see binding). */
-#define STV_INTERNAL 0x1 /* Special meaning in relocatable objects. */
-#define STV_HIDDEN 0x2 /* Not visible. */
-#define STV_PROTECTED 0x3 /* Visible but not preemptible. */
-
-/* Special symbol table indexes. */
-#define STN_UNDEF 0 /* Undefined symbol index. */
-
-/* Symbol versioning flags. */
-#define VER_DEF_CURRENT 1
-#define VER_DEF_IDX(x) VER_NDX(x)
-
-#define VER_FLG_BASE 0x01
-#define VER_FLG_WEAK 0x02
-
-#define VER_NEED_CURRENT 1
-#define VER_NEED_WEAK (1u << 15)
-#define VER_NEED_HIDDEN VER_NDX_HIDDEN
-#define VER_NEED_IDX(x) VER_NDX(x)
-
-#define VER_NDX_LOCAL 0
-#define VER_NDX_GLOBAL 1
-#define VER_NDX_GIVEN 2
-
-#define VER_NDX_HIDDEN (1u << 15)
-#define VER_NDX(x) ((x) & ~(1u << 15))
-
-#define CA_SUNW_NULL 0
-#define CA_SUNW_HW_1 1 /* first hardware capabilities entry */
-#define CA_SUNW_SF_1 2 /* first software capabilities entry */
-
-/*
- * Syminfo flag values
- */
-#define SYMINFO_FLG_DIRECT 0x0001 /* symbol ref has direct association */
- /* to object containing defn. */
-#define SYMINFO_FLG_PASSTHRU 0x0002 /* ignored - see SYMINFO_FLG_FILTER */
-#define SYMINFO_FLG_COPY 0x0004 /* symbol is a copy-reloc */
-#define SYMINFO_FLG_LAZYLOAD 0x0008 /* object containing defn should be */
- /* lazily-loaded */
-#define SYMINFO_FLG_DIRECTBIND 0x0010 /* ref should be bound directly to */
- /* object containing defn. */
-#define SYMINFO_FLG_NOEXTDIRECT 0x0020 /* don't let an external reference */
- /* directly bind to this symbol */
-#define SYMINFO_FLG_FILTER 0x0002 /* symbol ref is associated to a */
-#define SYMINFO_FLG_AUXILIARY 0x0040 /* standard or auxiliary filter */
-
-/*
- * Syminfo.si_boundto values.
- */
-#define SYMINFO_BT_SELF 0xffff /* symbol bound to self */
-#define SYMINFO_BT_PARENT 0xfffe /* symbol bound to parent */
-#define SYMINFO_BT_NONE 0xfffd /* no special symbol binding */
-#define SYMINFO_BT_EXTERN 0xfffc /* symbol defined as external */
-#define SYMINFO_BT_LOWRESERVE 0xff00 /* beginning of reserved entries */
-
-/*
- * Syminfo version values.
- */
-#define SYMINFO_NONE 0 /* Syminfo version */
-#define SYMINFO_CURRENT 1
-#define SYMINFO_NUM 2
-
-#define ELF64_R_SYM(i) ((i) >> 32)
-#define ELF64_R_TYPE(i) ((i) & 0xffffffffL)
-
-#define ELF32_R_SYM(i) ((i)>>8)
-#define ELF32_R_TYPE(i) ((uint8_t)(i))
-#define ELF32_R_INFO(s,t) (((s)<<8)+(uint8_t)(t))
-
-/* AMD x86-64 relocations. */
-#define R_X86_64_NONE 0 /* No relocation. */
-#define R_X86_64_64 1 /* Add 64 bit symbol value. */
-#define R_X86_64_PC32 2 /* PC-relative 32 bit signed sym value. */
-#define R_X86_64_GOT32 3 /* PC-relative 32 bit GOT offset. */
-#define R_X86_64_PLT32 4 /* PC-relative 32 bit PLT offset. */
-#define R_X86_64_COPY 5 /* Copy data from shared object. */
-#define R_X86_64_GLOB_DAT 6 /* Set GOT entry to data address. */
-#define R_X86_64_JMP_SLOT 7 /* Set GOT entry to code address. */
-#define R_X86_64_RELATIVE 8 /* Add load address of shared object. */
-#define R_X86_64_GOTPCREL 9 /* Add 32 bit signed pcrel offset to GOT. */
-#define R_X86_64_32 10 /* Add 32 bit zero extended symbol value */
-#define R_X86_64_32S 11 /* Add 32 bit sign extended symbol value */
-#define R_X86_64_16 12 /* Add 16 bit zero extended symbol value */
-#define R_X86_64_PC16 13 /* Add 16 bit signed extended pc relative symbol value */
-#define R_X86_64_8 14 /* Add 8 bit zero extended symbol value */
-#define R_X86_64_PC8 15 /* Add 8 bit signed extended pc relative symbol value */
-#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */
-#define R_X86_64_DTPOFF64 17 /* Offset in TLS block */
-#define R_X86_64_TPOFF64 18 /* Offset in static TLS block */
-#define R_X86_64_TLSGD 19 /* PC relative offset to GD GOT entry */
-#define R_X86_64_TLSLD 20 /* PC relative offset to LD GOT entry */
-#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */
-#define R_X86_64_GOTTPOFF 22 /* PC relative offset to IE GOT entry */
-#define R_X86_64_TPOFF32 23 /* Offset in static TLS block */
-
-/* i386 relocations. */
-#define R_386_NONE 0 /* No relocation. */
-#define R_386_32 1 /* Add symbol value. */
-#define R_386_PC32 2 /* Add PC-relative symbol value. */
-#define R_386_GOT32 3 /* Add PC-relative GOT offset. */
-#define R_386_PLT32 4 /* Add PC-relative PLT offset. */
-#define R_386_COPY 5 /* Copy data from shared object. */
-#define R_386_GLOB_DAT 6 /* Set GOT entry to data address. */
-#define R_386_JMP_SLOT 7 /* Set GOT entry to code address. */
-#define R_386_RELATIVE 8 /* Add load address of shared object. */
-#define R_386_GOTOFF 9 /* Add GOT-relative symbol address. */
-#define R_386_GOTPC 10 /* Add PC-relative GOT table address. */
-#define R_386_TLS_TPOFF 14 /* Negative offset in static TLS block */
-#define R_386_TLS_IE 15 /* Absolute address of GOT for -ve static TLS */
-#define R_386_TLS_GOTIE 16 /* GOT entry for negative static TLS block */
-#define R_386_TLS_LE 17 /* Negative offset relative to static TLS */
-#define R_386_TLS_GD 18 /* 32 bit offset to GOT (index,off) pair */
-#define R_386_TLS_LDM 19 /* 32 bit offset to GOT (index,zero) pair */
-#define R_386_TLS_GD_32 24 /* 32 bit offset to GOT (index,off) pair */
-#define R_386_TLS_GD_PUSH 25 /* pushl instruction for Sun ABI GD sequence */
-#define R_386_TLS_GD_CALL 26 /* call instruction for Sun ABI GD sequence */
-#define R_386_TLS_GD_POP 27 /* popl instruction for Sun ABI GD sequence */
-#define R_386_TLS_LDM_32 28 /* 32 bit offset to GOT (index,zero) pair */
-#define R_386_TLS_LDM_PUSH 29 /* pushl instruction for Sun ABI LD sequence */
-#define R_386_TLS_LDM_CALL 30 /* call instruction for Sun ABI LD sequence */
-#define R_386_TLS_LDM_POP 31 /* popl instruction for Sun ABI LD sequence */
-#define R_386_TLS_LDO_32 32 /* 32 bit offset from start of TLS block */
-#define R_386_TLS_IE_32 33 /* 32 bit offset to GOT static TLS offset entry */
-#define R_386_TLS_LE_32 34 /* 32 bit offset within static TLS block */
-#define R_386_TLS_DTPMOD32 35 /* GOT entry containing TLS index */
-#define R_386_TLS_DTPOFF32 36 /* GOT entry containing TLS offset */
-#define R_386_TLS_TPOFF32 37 /* GOT entry of -ve static TLS offset */
-
-/**
- * \brief ELF64 file header.
- */
-struct Elf64_Ehdr {
- uint8_t e_ident[EI_NIDENT];
- uint16_t e_type;
- uint16_t e_machine;
- uint32_t e_version;
- uint64_t e_entry;
- uint64_t e_phoff;
- uint64_t e_shoff;
- uint32_t e_flags;
- uint16_t e_ehsize;
- uint16_t e_phentsize;
- uint16_t e_phnum;
- uint16_t e_shentsize;
- uint16_t e_shnum;
- uint16_t e_shstrndx;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF64 program header.
- */
-struct Elf64_Phdr {
- uint32_t p_type;
- uint32_t p_flags;
- uint64_t p_offset;
- uint64_t p_vaddr;
- uint64_t p_paddr;
- uint64_t p_filesz;
- uint64_t p_memsz;
- uint64_t p_align;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF64 section header.
- */
-struct Elf64_Shdr {
- uint32_t sh_name;
- uint32_t sh_type;
- uint64_t sh_flags;
- uint64_t sh_addr;
- uint64_t sh_offset;
- uint64_t sh_size;
- uint32_t sh_link;
- uint32_t sh_info;
- uint64_t sh_addralign;
- uint64_t sh_entsize;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF64 relocation entry.
- */
-struct Elf64_Rela {
- uint64_t r_offset;
- uint64_t r_info;
- int64_t r_addend;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF64 symbol table entry.
- */
-struct Elf64_Sym {
- uint32_t st_name;
- uint8_t st_info;
- uint8_t st_other;
- uint16_t st_shndx;
- uint64_t st_value;
- uint64_t st_size;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF64 Dynamic section entry
- */
-struct Elf64_Dyn {
- int64_t d_tag;
- union {
- uint64_t d_val;
- uint64_t d_ptr;
- } d_un;
-} __attribute__ ((packed));
-
-/**
- * \brief ELF32 file header.
- */
-struct Elf32_Ehdr {
- uint8_t e_ident[EI_NIDENT]; // 00
- uint16_t e_type; // 16
- uint16_t e_machine; // 18
- uint32_t e_version; // 20
- uint32_t e_entry; // 24
- uint32_t e_phoff; // 28
- uint32_t e_shoff; // 32
- uint32_t e_flags; // 36
- uint16_t e_ehsize; // 40
- uint16_t e_phentsize; // 42
- uint16_t e_phnum; // 44
- uint16_t e_shentsize; // 46
- uint16_t e_shnum; // 48
- uint16_t e_shstrndx; // 50
-};
-
-/**
- * \brief ELF32 program header.
- */
-struct Elf32_Phdr {
- uint32_t p_type; // 0
- uint32_t p_offset; // 4
- uint32_t p_vaddr; // 8
- uint32_t p_paddr; // 12
- uint32_t p_filesz; // 16
- uint32_t p_memsz; // 20
- uint32_t p_flags; // 24
- uint32_t p_align; // 28
-};
-
-/**
- * \brief ELF32 section header.
- */
-struct Elf32_Shdr {
- uint32_t sh_name; // 0
- uint32_t sh_type; // 4
- uint32_t sh_flags; // 8
- uint32_t sh_addr; // 12
- uint32_t sh_offset; // 16
- uint32_t sh_size; // 20
- uint32_t sh_link; // 24
- uint32_t sh_info; // 28
- uint32_t sh_addralign; // 32
- uint32_t sh_entsize; // 36
-};
-
-/**
- * \brief ELF32 relocation entry.
- */
-struct Elf32_Rel {
- uint32_t r_offset;
- uint32_t r_info;
-};
-
-/**
- * \brief ELF32 relocation entry with addend.
- */
-struct Elf32_Rela {
- uint32_t r_offset;
- uint32_t r_info;
- int32_t r_addend;
-};
-
-/**
- * \brief ELF32 symbol table entry.
- */
-struct Elf32_Sym {
- uint32_t st_name;
- uint32_t st_value;
- uint32_t st_size;
- uint8_t st_info;
- uint8_t st_other;
- uint16_t st_shndx;
-};
-
-
-struct Elf32_Dyn {
- int32_t d_tag;
- union {
- uint32_t d_val;
- uint32_t d_ptr;
- } d_un;
-} __attribute__ ((packed));
-
-struct Elf32_Shdr *
-elf32_find_section_header_type(struct Elf32_Shdr *shdr,
- uint32_t entries, uint32_t type);
-
-void elf32_relocate(genvaddr_t dst, genvaddr_t src,
- struct Elf32_Rel *rela, size_t size,
- struct Elf32_Sym *symtab, size_t symsize,
- genvaddr_t start, void *vbase);
-
-typedef errval_t (*elf_allocator_fn)(void *state, genvaddr_t base,
- size_t size, uint32_t flags, void **ret);
-
-errval_t elf32_load(elf_allocator_fn allocate_func, void *state, lvaddr_t base,
- size_t size, genvaddr_t *retentry);
-
-errval_t elf64_load(elf_allocator_fn allocate_func,
- void *state, lvaddr_t base, size_t size,
- genvaddr_t *retentry);
-
-#endif // ELF_H
+++ /dev/null
-/**
- * \file
- * \brief Rudimentary ELF32 loader and handling routines.
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <assert.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <string.h>
-
-#include "elf.h"
-
-/**
- * \brief Return pointer to relocation section ELF header.
- *
- * This function finds and returns a pointer to the first ELF section
- * header of type 'type'.
- *
- * \param shdr Pointer to head of ELF section header table.
- * \param entries Number of entries in the ELF section header table.
- * \param type ELF section header type to look for.
- *
- * \return Pointer to first ELF section header of type 'type', or NULL.
- */
-struct Elf32_Shdr *
-elf32_find_section_header_type(struct Elf32_Shdr *shdr,
- uint32_t entries, uint32_t type)
-{
- int i;
-
- for(i = 0; i < entries; i++) {
- struct Elf32_Shdr *s = &shdr[i];
-
- if(s->sh_type == type) {
- return s;
- }
- }
-
- return NULL;
-}
-
-/**
- * \brief Return pointer to relocation section ELF header.
- *
- * This function finds and returns a pointer to the first ELF section
- * header at virtual address 'addr'.
- *
- * \param shdr Pointer to head of ELF section header table.
- * \param entries Number of entries in the ELF section header table.
- * \param addr Virtual address to look for
- *
- * \return Pointer to first ELF section header loaded at 'addr', or NULL.
- */
-static struct Elf32_Shdr *
-elf32_find_section_header_vaddr(struct Elf32_Shdr *shdr,
- uint32_t entries, genvaddr_t addr)
-{
- int i;
-
- for(i = 0; i < entries; i++) {
- struct Elf32_Shdr *s = &shdr[i];
-
- if(s->sh_addr == addr) {
- return s;
- }
- }
-
- return NULL;
-}
-
-/**
- * \brief Relocates the ELF image from src to dst.
- *
- * This function processes the ELF relocation section 'rela' of size 'size' of
- * the ELF image, formerly located at 'src', to the new location 'dst'.
- * Relocation is necessary for certain variables that cannot be coded as
- * position-independent code.
- *
- * \param dst Address to relocate to.
- * \param src Former base address of the ELF image.
- * \param rela Pointer to relocation section of the ELF image.
- * \param size Size in bytes of the ELF relocation section.
- * \param symtab Pointer to ELF symbol table.
- * \param symsize Size in bytes of the ELF symbol table.
- * \param start Original base address of the ELF image.
- * \param vbase Pointer to ELF image in virtual memory.
- */
-void elf32_relocate(genvaddr_t dst, genvaddr_t src,
- struct Elf32_Rel *rel, size_t size,
- struct Elf32_Sym *symtab, size_t symsize,
- genvaddr_t start, void *vbase)
-{
- genvaddr_t base = dst - src, abase = dst - start;
-
- for(int i = 0; i < size / sizeof(struct Elf32_Rel); i++) {
- struct Elf32_Rel *r = &rel[i];
- uint32_t type = ELF32_R_TYPE(r->r_info);
- uint32_t *addr = vbase + r->r_offset - start;
-
- switch(type) {
- case R_386_32:
- {
- uint32_t sym = ELF32_R_SYM(r->r_info);
- assert(sym < symsize / sizeof(struct Elf32_Sym));
- /* assert(symtab[sym].st_value != 0); */
- *addr = abase + symtab[sym].st_value;
- }
- break;
-
- case R_386_RELATIVE:
- *addr += base;
- break;
-
- default:
- printf("elf_relocate: relocation %d type %d\n", i, type);
- assert(!"Unimplemented: Cannot handle relocation type");
- break;
- }
- }
-}
-
-/**
- * \brief Load ELF64 binary image into memory
- *
- * This function loads an ELF64 binary image, based at 'base' and of size
- * 'size' into the memory provided by 'allocate'
- *
- * \param allocate Memory allocation function.
- * \param state Pointer to state for allocation function.
- * \param base Base address of ELF64 binary image in memory.
- * \param size Size of ELF64 binary image in bytes.
- * \param retentry Used to return entry point address
- */
-errval_t elf32_load(elf_allocator_fn allocate_func, void *state, lvaddr_t base,
- size_t size, genvaddr_t *retentry)
-{
- struct Elf32_Ehdr *head = (struct Elf32_Ehdr *)base;
- errval_t err;
- int i;
-
- // Check for valid file size
- if (size < sizeof(struct Elf32_Ehdr)) {
- return -1;
- }
-
- // Check for compatible ELF32 header
- if (!IS_ELF(*head)
- || head->e_ident[EI_CLASS] != ELFCLASS32
- || head->e_ident[EI_DATA] != ELFDATA2LSB
- || head->e_ident[EI_VERSION] != EV_CURRENT
- || head->e_ident[EI_OSABI] != ELFOSABI_SYSV
- || head->e_ident[EI_ABIVERSION] != 0
- || (head->e_type != ET_EXEC && head->e_type != ET_DYN)
- || head->e_machine != EM_386
- || head->e_version != EV_CURRENT) {
- return -2;
- }
-
- // More sanity checks
- if (head->e_phoff + head->e_phentsize * head->e_phnum > size
- || head->e_phentsize != sizeof(struct Elf32_Phdr)) {
- return -3;
- }
-
- struct Elf32_Shdr *shead =
- (struct Elf32_Shdr *)(base + (uintptr_t)head->e_shoff);
- struct Elf32_Shdr *rela =
- elf32_find_section_header_type(shead, head->e_shnum, SHT_REL);
- struct Elf32_Shdr *symtab =
- elf32_find_section_header_type(shead, head->e_shnum, SHT_SYMTAB);
-
- size_t rela_size = rela ? rela->sh_size : 0, new_rela_size = 0;
- struct Elf32_Shdr *new_rela = NULL;
-
- // Find dynamic program header, if any
- struct Elf32_Phdr *phead =
- (struct Elf32_Phdr *)(base + (uintptr_t)head->e_phoff);
- for (i = 0; i < head->e_phnum; i++) {
- struct Elf32_Phdr *p = &phead[i];
-
- if (p->p_type == PT_DYNAMIC) {
- struct Elf32_Dyn *dynamic = (void *)(base + (uintptr_t)p->p_offset);
- int n_dynamic = p->p_filesz / sizeof(struct Elf32_Dyn);
- for (int j = 0; j < n_dynamic; j++) {
- switch (dynamic[j].d_tag) {
- case DT_RELA:
- // virtual address of relocations, look for matching section
- new_rela =
- elf32_find_section_header_vaddr(shead, head->e_shnum,
- dynamic[j].d_un.d_val);
- break;
-
- case DT_RELASZ:
- // store size of relocations, as they may cover more than
- // one section
- new_rela_size = dynamic[j].d_un.d_val;
- break;
-
- case DT_SYMTAB:
- // virtual address of symtab, look for matching section
- symtab =
- elf32_find_section_header_vaddr(shead, head->e_shnum,
- dynamic[j].d_un.d_val);
- break;
-
- case DT_SYMENT:
- assert(dynamic[j].d_un.d_val == sizeof(struct Elf32_Sym));
- break;
- }
- }
-
- if (new_rela != NULL) {
- assert(new_rela_size != 0);
- rela = new_rela;
- rela_size = new_rela_size;
- }
- break;
- }
- }
-
- // Process program headers to load file
- for (i = 0; i < head->e_phnum; i++) {
- struct Elf32_Phdr *p = &phead[i];
-
- if (p->p_type == PT_LOAD) {
- //printf("Loading segment: start=0x%lx, size=%lu, flags=%d\n",
- // p->p_vaddr, p->p_memsz, p->p_flags);
-
- // Map segment in user-space memory
- void *dest = NULL;
- err = allocate_func(state, (genvaddr_t)p->p_vaddr,
- p->p_memsz, p->p_flags, &dest);
- if (err != 0) {
- return -4;
- }
- assert(dest != NULL);
-
- // Copy file segment into memory
- memcpy(dest, (void *)(base + (uintptr_t)p->p_offset), p->p_filesz);
-
- // Initialize rest of memory segment (ie. BSS) with all zeroes
- memset(dest + p->p_filesz, 0, p->p_memsz - p->p_filesz);
-
- // Apply relocations
- if (rela != NULL && symtab != NULL) {
- elf32_relocate(p->p_vaddr, p->p_vaddr,
- (struct Elf32_Rel *)
- (base + (uintptr_t)rela->sh_offset),
- rela_size,
- (struct Elf32_Sym *)
- (base + (uintptr_t)symtab->sh_offset),
- symtab->sh_size, p->p_vaddr, dest);
- }
- }
- }
-
- if (retentry != NULL) {
- *retentry = head->e_entry;
- }
-
- return 0;
-}
+++ /dev/null
-/**
- * \file
- * \brief Rudimentary ELF64 loader and handling routines.
- *
- * Note that on 32-bit platforms, this loader is only able to load
- * ELF64 files that it can address (ie. those that are not bigger than
- * what fits into a 32-bit address space).
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, 2011, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <assert.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <string.h>
-#include "elf.h"
-
-/**
- * \brief Return pointer to relocation section ELF header.
- *
- * This function finds and returns a pointer to the first ELF section
- * header of type 'type'.
- *
- * \param shdr Pointer to head of ELF section header table.
- * \param entries Number of entries in the ELF section header table.
- * \param type ELF section header type to look for.
- *
- * \return Pointer to first ELF section header of type 'type', or NULL.
- */
-static struct Elf64_Shdr *
-elf64_find_section_header_type(struct Elf64_Shdr * shdr,
- uint32_t entries, uint32_t type)
-{
- int i;
-
- for(i = 0; i < entries; i++) {
- struct Elf64_Shdr *s = &shdr[i];
-
- if(s->sh_type == type) {
- return s;
- }
- }
-
- return NULL;
-}
-
-/**
- * \brief Return pointer to relocation section ELF header.
- *
- * This function finds and returns a pointer to the first ELF section
- * header at virtual address 'addr'.
- *
- * \param shdr Pointer to head of ELF section header table.
- * \param entries Number of entries in the ELF section header table.
- * \param addr Virtual address to look for
- *
- * \return Pointer to first ELF section header loaded at 'addr', or NULL.
- */
-static struct Elf64_Shdr *
-elf64_find_section_header_vaddr(struct Elf64_Shdr * shdr,
- uint32_t entries, genvaddr_t addr)
-{
- int i;
-
- for(i = 0; i < entries; i++) {
- struct Elf64_Shdr *s = &shdr[i];
-
- if(s->sh_addr == addr) {
- return s;
- }
- }
-
- return NULL;
-}
-
-/**
- * \brief Relocates the ELF image from src to dst.
- *
- * This function processes the ELF relocation section 'rela' of size 'size' of
- * the ELF image, formerly located at 'src', to the new location 'dst'.
- * Relocation is necessary for certain variables that cannot be coded as
- * position-independent code.
- *
- * \param dst Address to relocate to.
- * \param src Former base address of the ELF image.
- * \param rela Pointer to relocation section of the ELF image.
- * \param size Size in bytes of the ELF relocation section.
- * \param symtab Pointer to ELF symbol table.
- * \param symsize Size in bytes of the ELF symbol table.
- * \param start Original base address of the ELF image (needed for
- * symbol-table-based relocations -- we don't touch the symbol table).
- * \param vbase Pointer to ELF image in virtual memory.
- */
-void elf64_relocate(genvaddr_t dst, genvaddr_t src,
- struct Elf64_Rela *rela, size_t size,
- struct Elf64_Sym *symtab, size_t symsize,
- genvaddr_t start, void *vbase)
-{
- genvaddr_t base = dst - src, abase = dst - start;
-
- for(int i = 0; i < size / sizeof(struct Elf64_Rela); i++) {
- struct Elf64_Rela *r = &rela[i];
- uint32_t type = ELF64_R_TYPE(r->r_info);
- uint64_t *addr = (uint64_t *)((char *)vbase + r->r_offset - start);
-
- switch(type) {
- case R_X86_64_NONE:
- // Do nothing
- break;
-
- case R_X86_64_64:{
- uint32_t sym = ELF64_R_SYM(r->r_info);
- assert(sym < symsize / sizeof(struct Elf64_Sym));
-#if 0 // XXX: symbols should be 0 but this fires sometimes
- assert(symtab[sym].st_value != 0);
-#endif
- *addr = abase + symtab[sym].st_value + r->r_addend;
- break;}
-
- case R_X86_64_RELATIVE:
- // FIXME: why doesn't the following work? -AB
- // I don't think this makes sense. It is a relative
- // relocation from the old position. Thus, base and not
- // abase should be used. Further, since r->r_addend is not
- // updated between relocations, this will fail as soon as
- // a binary is relocated more than once. -SP
- //*addr = abase + r->r_addend;
- *addr += base;
- break;
-
- default:
- printf("elf_relocate: relocation %d type %d\n", i, type);
- assert(!"Unimplemented: Cannot handle relocation type");
- break;
- }
- }
-}
-
-/**
- * \brief Load ELF64 binary image into memory
- *
- * This function loads an ELF64 binary image, based at 'base' and of size
- * 'size' into the memory provided by 'allocate'
- *
- * \param allocate Memory allocation function.
- * \param state Pointer to state for allocation function.
- * \param base Base address of ELF64 binary image in memory.
- * \param size Size of ELF64 binary image in bytes.
- * \param retentry Used to return entry point address
- */
-errval_t elf64_load(elf_allocator_fn allocate_func,
- void *state, lvaddr_t base, size_t size,
- genvaddr_t *retentry)
-{
- struct Elf64_Ehdr *head = (struct Elf64_Ehdr *)base;
- errval_t err;
- int i;
-
- // Check for valid file size
- if (size < sizeof(struct Elf64_Ehdr)) {
- return -1;
- }
-
- // Check for compatible ELF64 header
- if (!IS_ELF(*head)
- || head->e_ident[EI_CLASS] != ELFCLASS64
- || head->e_ident[EI_DATA] != ELFDATA2LSB
- || head->e_ident[EI_VERSION] != EV_CURRENT
- || head->e_ident[EI_OSABI] != ELFOSABI_SYSV
- || head->e_ident[EI_ABIVERSION] != 0
- || (head->e_type != ET_EXEC && head->e_type != ET_DYN)
- || head->e_version != EV_CURRENT) {
- return -2;
- }
-
- // More sanity checks
- if (head->e_phoff + head->e_phentsize * head->e_phnum > size
- || head->e_phentsize != sizeof(struct Elf64_Phdr)) {
- return -3;
- }
-
- struct Elf64_Shdr *shead =
- (struct Elf64_Shdr *)(base + (uintptr_t)head->e_shoff);
- struct Elf64_Shdr *rela =
- elf64_find_section_header_type(shead, head->e_shnum, SHT_RELA);
- struct Elf64_Shdr *symtab =
- elf64_find_section_header_type(shead, head->e_shnum, SHT_SYMTAB);
-
- size_t rela_size = rela ? rela->sh_size : 0, new_rela_size = 0;
- struct Elf64_Shdr *new_rela = NULL;
-
- // Find dynamic program header, if any
- struct Elf64_Phdr *phead =
- (struct Elf64_Phdr *)(base + (uintptr_t)head->e_phoff);
- for (i = 0; i < head->e_phnum; i++) {
- struct Elf64_Phdr *p = &phead[i];
-
- if (p->p_type == PT_DYNAMIC) {
- struct Elf64_Dyn *dynamic = (void *)(base + (uintptr_t)p->p_offset);
- int n_dynamic = p->p_filesz / sizeof(struct Elf64_Dyn);
- for (int j = 0; j < n_dynamic; j++) {
- switch (dynamic[j].d_tag) {
- case DT_RELA:
- // virtual address of relocations, look for matching section
- new_rela =
- elf64_find_section_header_vaddr(shead, head->e_shnum,
- dynamic[j].d_un.d_val);
- break;
-
- case DT_RELASZ:
- // store size of relocations, as they may cover more than
- // one section
- new_rela_size = dynamic[j].d_un.d_val;
- break;
-
- case DT_SYMTAB:
- // virtual address of symtab, look for matching section
- symtab =
- elf64_find_section_header_vaddr(shead, head->e_shnum,
- dynamic[j].d_un.d_val);
- break;
-
- case DT_SYMENT:
- assert(dynamic[j].d_un.d_val == sizeof(struct Elf64_Sym));
- break;
- }
- }
-
- if (new_rela != NULL) {
- assert(new_rela_size != 0);
- rela = new_rela;
- rela_size = new_rela_size;
- }
- break;
- }
- }
-
- // Process program headers to load file
- for (i = 0; i < head->e_phnum; i++) {
- struct Elf64_Phdr *p = &phead[i];
-
- if (p->p_type == PT_LOAD) {
- //printf("Loading segment: start=0x%lx, size=%lu, flags=%d\n",
- //p->p_vaddr, p->p_memsz, p->p_flags);
-
- // Map segment in user-space memory
- void *dest = NULL;
- err = allocate_func(state, (genvaddr_t)p->p_vaddr, p->p_memsz, p->p_flags, &dest);
- if (err != 0) {
- return -4;
- }
- assert(dest != NULL);
-
- // Copy file segment into memory
- memcpy(dest, (void *)(base + (uintptr_t)p->p_offset), p->p_filesz);
-
- // Initialize rest of memory segment (ie. BSS) with all zeroes
- memset((char *)dest + p->p_filesz, 0, p->p_memsz - p->p_filesz);
-
- // Apply relocations
- if (rela != NULL && symtab != NULL) {
- elf64_relocate(p->p_vaddr, p->p_vaddr,
- (struct Elf64_Rela *)
- (base + (uintptr_t)rela->sh_offset),
- rela_size,
- (struct Elf64_Sym *)
- (base + (uintptr_t)symtab->sh_offset),
- symtab->sh_size, p->p_vaddr, dest);
- }
- }
- }
-
- if (retentry != NULL) {
- *retentry = head->e_entry;
- }
-
- return 0;
-}
#include <stdio.h>
#include <barrelfish/barrelfish.h>
-#ifdef __scc__
-# define ENABLE_FEIGN_FRAME_CAP
-# include <barrelfish/sys_debug.h>
-#endif
#include <barrelfish/waitset.h>
#define WITH_BUFFER_CACHE
#include <vfs/vfs.h>
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-#endif
#include "bcached.h"
#include <hashtable/hashtable.h>
static errval_t create_cache_mem(size_t size)
{
// Create a Frame Capability
-#ifndef __scc__
errval_t r = frame_alloc(&cache_memory, size, &cache_size);
-#else
- errval_t r = slot_alloc(&cache_memory);
- assert(err_is_ok(r));
- r = sys_debug_feign_frame_cap(cache_memory, EXTRA_SHARED_MEM_MIN, 28);
- cache_size = size;
-#endif
if (err_is_fail(r)) {
return err_push(r, LIB_ERR_FRAME_ALLOC);
}
assert(cache_size >= size);
// Map the frame in local memory
-#ifdef __scc__
- r = vspace_map_one_frame_attr(&cache_pool, cache_size, cache_memory,
- VREGION_FLAGS_READ_WRITE_MPB, NULL, NULL);
-#else
r = vspace_map_one_frame(&cache_pool, cache_size, cache_memory, NULL, NULL);
-#endif
if (err_is_fail(r)) {
cap_destroy(cache_memory);
return err_push(r, LIB_ERR_VSPACE_MAP);
}
}
-#ifdef __scc__
-static void cl1flushmb_benchmark(void)
-{
- for(int i = 0; i < MICROBENCH_ITERATIONS; i++) {
- cl1flushmb();
- }
-}
-#endif
-
static void xchg_benchmark(void)
{
uint32_t mem = 1, reg = 7;
}
}
-#ifdef __scc__
-# include <barrelfish_kpi/shared_mem_arch.h>
-
-# define LUT_SIZE 0x1000000
-
-static void clr_shared_benchmark(void)
-{
- uintptr_t *mem;
- uint64_t start, end;
-
- for(int mc = 0; mc < 4; mc++) {
- struct capref frame;
- size_t framesize = BASE_PAGE_SIZE;
- ram_set_affinity(SHARED_MEM_MIN + mc * LUT_SIZE,
- SHARED_MEM_MIN + (mc + 1) * LUT_SIZE);
- errval_t err = frame_alloc(&frame, framesize, &framesize);
- assert(err_is_ok(err));
- ram_set_affinity(0, 0);
-
- // map it in
- void *buf;
- /* err = vspace_map_one_frame_attr(&buf, framesize, frame, */
- /* VREGION_FLAGS_READ_WRITE_NOCACHE, NULL, NULL); */
- err = vspace_map_one_frame_attr(&buf, framesize, frame,
- VREGION_FLAGS_READ_WRITE_MPB, NULL, NULL);
- assert(err_is_ok(err));
-
- mem = buf;
-
- printf("clear shared memory MC %d:\n", mc);
-
- start = rdtsc();
- for(int i = 0; i < MICROBENCH_ITERATIONS; i++) {
- __asm__ __volatile__ (
- "movl $0,%0\n\t"
- "movl $0,4%0\n\t"
- "movl $0,8%0\n\t"
- "movl $0,12%0\n\t"
- "movl $0,16%0\n\t"
- "movl $0,20%0\n\t"
- "movl $0,24%0\n\t"
- "movl $0,28%0\n\t"
- : /* no output */
- : "m" (*mem)
- : "%rax");
- }
-
- end = rdtsc();
- print_result(end - start);
- }
-}
-#endif
-
#ifndef BENCH_POSIX
#if 0
printf("NOP system call: ");
print_result(benchmark(syscall_benchmark));
-#ifdef __scc__
- printf("CL1FLUSHMB instruction: ");
- print_result(benchmark(cl1flushmb_benchmark));
-
- clr_shared_benchmark();
-#endif
-
printf("RDTSC instruction: ");
print_result(benchmark(rdtsc_benchmark));
// Init sender
struct capref frame;
- err = bulk_create(BULKSIZE, block_size, &frame, &bt, false);
+ err = bulk_create(BULKSIZE, block_size, &frame, &bt);
assert(err_is_ok(err));
err = peer->tx_vtbl.bulk_init(peer, NOP_CONT, frame);
#define MAXROUND 100000
#define ROUNDS_PER_SLICE 5
-#ifdef __scc__
-extern uint32_t yield_timeslices;
-#endif
-
int RCCE_APP(int argc, char **argv){
int YOU, ME, round;
#ifndef NO_FLOAT
RCCE_send(buffer, BUFSIZE, YOU);
sum += rdtsc() - timer;
-
-#if defined(ROUNDS_PER_SLICE) && defined(__scc__)
- if(round % ROUNDS_PER_SLICE == 0) {
- yield_timeslices = 1;
- thread_yield();
- yield_timeslices = 0;
- }
-#endif
}
}
#ifndef NO_FLOAT
struct frame_identity* id)
{
errval_t err;
-#ifdef __scc__
- *cpu_memory = X86_32_BASE_PAGE_SIZE;
- err = frame_alloc_identify(cpu_memory_cap, *cpu_memory, cpu_memory, id);
- if (err_is_fail(err)) {
- return err_push(err, LIB_ERR_FRAME_ALLOC);
- }
-#else
*cpu_memory = elf_virtual_size(cpu_binary) + page_size;
uint64_t old_minbase;
done:
ram_set_affinity(old_minbase, old_maxlimit);
-#endif
return SYS_ERR_OK;
}
+++ /dev/null
---------------------------------------------------------------------------
--- Copyright (c) 2007-2009, ETH Zurich.
--- All rights reserved.
---
--- This file is distributed under the terms in the attached LICENSE file.
--- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
---
--- Hakefile for /usr/drivers/eMAC
---
---------------------------------------------------------------------------
-
-[ build application { target = "eMAC",
- cFiles = [ "eMAC_driver.c", "eMAC_hwinit.c",
- "eMAC_debug.c"],
- flounderBindings = [ "net_queue_manager",
- "net_soft_filters" ],
- mackerelDevices = [ "eMAC" ],
- addLibraries = libDeps [ "netQmng" ]
- }
-]
-
+++ /dev/null
-/**
- * \file
- * \brief Intel eMAC driver: Debug functionality
- *
- * This file is a driver for the PCI Express e1000 card
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <stdio.h>
-#include "eMAC_driver.h"
-#include <net_queue_manager/net_queue_manager.h>
-//static eMAC_t *d;
-/*
- * Handy-dandy shorthand for printing registers: make sure you have a
- * suitable buffer declared.
- */
-#define PR_REG(t) eMAC_##t##_pr(pb, PRTBUF_SZ, &d); printf("%s\n",pb)
-#define PR_REGZ(t) eMAC_##t##_pri(pb, PRTBUF_SZ, &d, 0); printf("%s\n",pb)
-#define PRTBUF_SZ 4000
-
-
-void print_statistics(void)
-{
-
- // Transmit registers
-
- // Receive registers
-
- // Statistics registers
-
-}
-
+++ /dev/null
-/*
- * Copyright (c) 2007, 2008, 2009, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef _EMAC_DEBUG_H_
-#define _EMAC_DEBUG_H_
-
-
-/*****************************************************************
- * Debug printer:
- *****************************************************************/
-
-//#define EMAC_DEBUG(x...) printf("EMAC: " x)
-//#define EMAC_DEBUG(x...) ((void)0)
-
-
-#if defined(EMAC_SERVICE_DEBUG) || defined(GLOBAL_DEBUG)
-#define EMAC_DEBUG(x...) printf("EMAC: " x)
-#else
-#define EMAC_DEBUG(x...) ((void)0)
-#endif
-
-
-#endif // _EMAC_DEBUG_H_
+++ /dev/null
-/**
- * \file
- * \brief SCC eMAC driver.
- */
-
-/*
- * Copyright (c) 2007, 2008, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <net_queue_manager/net_queue_manager.h>
-#include "eMAC_driver.h"
-
-
-/// The only instance of the RTL8029AS we're handling
-//static eMAC_t emac;
-
-static uint64_t assumed_queue_id = 0; // queue_id that will be initialized
-
-uint64_t eMAC_mac;
-/// This buffers the card's MAC address upon card reset
-
-/* driver will initially copy the packet here. */
-//static uint8_t packetbuf[PACKET_SIZE];
-
-/* the length of packet copied into packetbuf */
-//static uint16_t packet_length;
-
-
-/**
- * \brief Send Ethernet packet.
- *
- * The packet should be a complete Ethernet frame. Nothing is added
- * by the card or the driver.
- *
- */
-/* FIXME: Modify the transmit_pbuf_list function to work with driver_buffer
- * datastructure instead of working with procon library. */
-//static errval_t EMAC_send_ethernet_packet_fn(struct client_closure *cl)
-static errval_t transmit_pbuf_list_fn(struct driver_buffer *buffers,
- size_t count)
-{
- EMAC_DEBUG("send pkt function called\n");
- assert(!"Older implementation, will not work without modification");
- return (ETHERSRV_ERR_CANT_TRANSMIT);
-// return (transmit_pbuf_list(cl));
-}
-
-
-static void get_mac_address_fn(uint8_t *mac)
-{
- uint64_t mac_value = eMAC_mac;
-
- for (int i = 5; i != 0; i--) {
- mac[i] = mac_value & 0xFF;
- mac_value >>= 8;
- }
-}
-
-static bool handle_free_TX_slot_fn(void)
-{
- // FIXME: Need better implementation of this function
- // FIXME: where is notify_client_next_free_tx for this driver
- return false;
-}
-
-static uint64_t rx_find_free_slot_count_fn(void)
-{
- // FIXME: temparary hardcoded value for free slot count
- return RX_max_slots - 100;
-}
-
-
-
-
-static void EMAC_init(uint8_t phy_id, char *service_name)
-{
-
- EMAC_DEBUG("starting hardware init\n");
- eMAC_hwinit(phy_id);
- /* FIXME: do hardware init*/
- EMAC_DEBUG("Done with hardware init\n");
-
- ethersrv_init(service_name, assumed_queue_id, get_mac_address_fn,
- NULL,
- transmit_pbuf_list_fn,
- get_tx_free_slots_count,
- handle_free_TX_slot_fn,
- RX_max_slots, // from eMAC_hwinit.c file
- NULL, // only needed when application owns the queue
- rx_find_free_slot_count_fn
- );
-}
-
-
-
-//this functions polls all the client's channels as well as the transmit and
-//receive descriptor rings
-static void polling_loop(void)
-{
- errval_t err;
- struct waitset *ws = get_default_waitset();
- while (1) {
- err = event_dispatch(ws);
- if (err_is_fail(err)) {
- DEBUG_ERR(err, "in event_dispatch");
- break;
- }
-// EMAC_DEBUG("inside event dispatch\n");
-/* notify_client_next_free_tx();
-*/
- }
- printf("ERROR: End of polling\n");
-}
-
-
-int main(int argc, char *argv[])
-{
- char *service_name = 0;
- uint8_t device = 2;
-
- EMAC_DEBUG("Starting EMAC standalone driver.....\n");
- for (int i = 0; i < argc; i++) {
- EMAC_DEBUG("arg %d = %s\n", i, argv[i]);
- if(strncmp(argv[i],"servicename=",strlen("servicename=")-1)==0) {
- service_name = argv[i] + strlen("servicename=");
- EMAC_DEBUG("service name = %s\n", service_name);
- }
- if(strncmp(argv[i],"device=",strlen("device=")-1)==0) {
- device = atoi(argv[i] + strlen("device="));
- EMAC_DEBUG("device = %u\n", device);
- }
- }
-
- if (service_name == 0) {
- uint8_t size = 16;
- service_name = (char *)malloc(size);
- snprintf(service_name, size, "eMAC%d_%d", device, disp_get_core_id());
- /* FIXME: make sure that there are no white-spaces in name */
- }
- EMAC_DEBUG("service name = [%s]\n", service_name);
-
- printf("Starting EMAC for hardware\n");
-
- // Initialize driver
- EMAC_init(device, service_name);
- EMAC_DEBUG("registered the driver.....\n");
-
- EMAC_DEBUG("starting to poll\n");
- polling_loop(); //loop myself
-}
-
+++ /dev/null
-/**
- * \file
- * \brief Intel e1000 driver: Prototypes
- *
- *
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef _EMAC_DRIVER_H_
-#define _EMAC_DRIVER_H_
-#include <barrelfish/barrelfish.h>
-#include <net_queue_manager/net_queue_manager.h>
-#include <dev/eMAC_dev.h>
-#include "eMAC_debug.h"
-
-
-errval_t transmit_pbuf_list(struct client_closure *cl);
-void eMAC_hwinit(uint8_t phy_id);
-uint64_t get_tx_free_slots_count(void);
-uint32_t RX_max_slots; // = SLOTS - 1;
-
-
-#endif // _EMAC_DRIVER_H_
+++ /dev/null
-/**
- * \file
- * \brief Intel e1000 driver: Initialize the hardware
- *
- *
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-
-
-#include <barrelfish/barrelfish.h>
-#include <string.h>
-// Following two are needed for call "sys_debug_feign_frame_cap"
-#define ENABLE_FEIGN_FRAME_CAP
-#include <barrelfish/sys_debug.h>
-#include <barrelfish/inthandler.h>
-#include <net_queue_manager/net_queue_manager.h>
-#include <trace/trace.h>
-#include <trace_definitions/trace_defs.h>
-
-
-#include <dev/eMAC_dev.h>
-#include "eMAC_driver.h"
-
-#include "eMAC_debug.h"
-
-/* Enable tracing based on the global settings. */
-#if CONFIG_TRACE && NETWORK_STACK_TRACE
-#define TRACE_ETHERSRV_MODE 1
-#endif // CONFIG_TRACE && NETWORK_STACK_TRACE
-
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-static eMAC_t emac;
-
-#define EMAC_CFG_REGS_BASE (0xF9000000)
-#define EMAC_CFG_REGS_SIZE (0x10000)
-
-#define EMAC_IRQ_CONFIG 1 /// Pin on core to use (1 == LINT1)
-/*
-#define EMAC0_IRQ 0x1 /// IRQ of eMAC #2
-#define EMAC1_IRQ 0x2 /// IRQ of eMAC #2
-#define EMAC2_IRQ 0x4 /// IRQ of eMAC #2
-#define EMAC3_IRQ 0x8 /// IRQ of eMAC #2
-*/
-
-#define CSIZE (32)
-#define SLOTS (1 << 16)
-#define BUFF_SIZE (SLOTS * CSIZE)
-#define TX_MAX_PKT_SIZE 1536
-
-
-static struct capref RX_capframe;
-static void *RX_internal_memory_pa = NULL;
-static void *RX_internal_memory_va = NULL;
-static uint32_t volatile RX_read_index = 0;
-
-static struct capref TX_capframe;
-static void *TX_internal_memory_pa = NULL;
-static void *TX_internal_memory_va = NULL;
-static uint32_t volatile TX_write_index = 0;
-static uint32_t TX_max_slots = SLOTS - 1;
-
-
-// For measurement of interrupts
-extern uint64_t interrupt_counter;
-
-/* MAC address */
-extern uint64_t eMAC_mac;
-
-/* set at hwinit */
-static uint8_t eMAC_PHY_id = 0; /* Which emac PHY you are using? */
-//static interrupt_handler_fn high_level_handler = NULL;
-
-
-/* FIXME: allocate following buffer with malloc (or get it from user apps) */
-
-#define MAX_FRAME_SIZE 1600
-static uint8_t dummy_pkt[MAX_FRAME_SIZE];
-
-/* FIXME: remove these */
-static volatile uint8_t *rb_RX = NULL;
-static volatile uint8_t *rb_TX = NULL;
-static volatile uint16_t *rb_TX_header = NULL;
-static volatile uint16_t *rb_RX_header = NULL;
-
-
-static unsigned long long rx_tile_offset = 0;
-static int rx_pos = 0;
-static int rx_mode = 0;
-
-static uint8_t core_id = 0;
-//static uint8_t core_id = 0;
-static uint64_t call_counter = 0;
-static uint64_t pkt_counter = 0;
-
-static size_t get_cachelines(uint64_t data_size)
-{
- size_t cachelines = (data_size)/ CSIZE;
- if (((data_size)%CSIZE) > 0) {
- ++cachelines;
- }
- return cachelines;
-}
-
-/*
-static void print_cline(uint8_t *cline)
-{
- EMAC_DEBUG("Cacheline [");
- for(int j = 0; j < 32; ++j) {
- printf("%x,", cline[j]);
- }
- printf("]\n");
-}
-*/
-/*
-static void increment_TX_write_index(void)
-{
- ++TX_write_index;
- if (TX_write_index > TX_max_slots ) {
- TX_write_index = 1;
- }
-} // end function: increment_TX_write_index
-*/
-
-static void increment_RX_read_index(void)
-{
- ++RX_read_index;
- if (RX_read_index > RX_max_slots || RX_read_index == 0) {
- RX_read_index = 1;
- }
-} /* end function: increment_read_index */
-
-/*
-static void my_memcpy(uint8_t *dst, uint8_t *src, size_t len)
-{
- for(int i = 0; i < len; ++i){
- dst[i] = src[i];
- }
-}
-*/
-
-static void show_packet(uint8_t *pkt, size_t len)
-{
-/*
- printf("\n[");
- for(int i = 0; i < len; ++i) {
- if(i % 16 == 0){
- printf("\n%04x", i);
- }
- printf(" %02x", pkt[i]);
- }
- printf("\n] = %u\n", len);
-*/
-} /* end function: show_packet */
-
-static void receive_frame_data(void)
-{
- /* 9.6.5.4 Receiving Frame Data */
- /*
- 1. Check for updated write index in head of buffer
- (or FPGA register) (RX buffer+0x00)
- a. Read 4 bytes from RX buffer at address 0 and compare
- the write index value to the internal read index value stored
- in the driver
- */
-
- eMAC_RX_Buffer_read_index_t idx_r;
- eMAC_RX_Buffer_write_index_t idx_w;
- /*
- uint16_t rid;
- uint16_t wid;
-*/
-
- cl1flushmb();
- uint16_t volatile wid = 0;
- uint8_t volatile *buf = (uint8_t *) RX_internal_memory_va;
- void *pkt_to_upload = NULL;
- ++call_counter;
-
- uint16_t volatile wid1 = 0;
- uint16_t volatile rid1 = 0;
- idx_r = eMAC_eMAC2_RX_Buffer_read_index_rd(&emac, core_id);
- idx_w = eMAC_eMAC2_RX_Buffer_write_index_rd(&emac, core_id);
- rid1 = idx_r.rid;
- wid1 = idx_w.wid;
-
- if (rid1 != wid1 ){
- EMAC_DEBUG("######## we have a packet! rid [%"PRIx16"] wid[%"PRIx16"]\n",
- rid1, wid1);
- EMAC_DEBUG("old values %"PRIx32", %"PRIx16", %"PRIx16"\n",
- RX_read_index, rb_RX_header[0], rb_RX_header[1]);
-// abort();
- }
-
- wid = rb_RX_header[0];
- wid = wid1;
- RX_read_index = rid1;
- if (RX_read_index == wid) {
- return;
- }
-
-
- assert( wid <= RX_max_slots);
-
-/* EMAC_DEBUG("%" PRIx64 ": new pkt [rid1 (%u) (%u) == wid1(%u) (%u)]\n",
- call_counter, rid1, rb_RX_header[1], wid1, rb_RX_header[0]);
-*/
- EMAC_DEBUG("MOVEMENT: %" PRIx64 " [rid (%x) != wid (%x)]\n",
- call_counter, RX_read_index, wid);
-
- do {
- increment_RX_read_index();
-
- uint16_t frame_len = 0;
- uint16_t *frame_len_ptr;
- uint32_t copied = 0;
-
- uint8_t *pkt_ptr = (uint8_t *)(buf + (RX_read_index * 32));
-// show_packet(pkt_ptr, 90);
- EMAC_DEBUG("buf location (%p) + index (%x) = pkt location (%p)\n",
- buf, RX_read_index * 32, pkt_ptr);
- frame_len_ptr = (uint16_t *)pkt_ptr;
- frame_len = *frame_len_ptr;
- if(frame_len == 0){
- /* printf("%d:invalid packet received, %x %x\n", RX_read_index, wid1); */
- RX_read_index = wid1;
- goto finish;
- }
- EMAC_DEBUG("[RX pkt len (%u)]\n", frame_len);
- uint32_t clines = get_cachelines(frame_len + 2);
- EMAC_DEBUG("[clines (%u)]\n", clines);
- if(RX_read_index + clines - 1 <= RX_max_slots) {
-
- pkt_to_upload = pkt_ptr + 2;
- copied = frame_len;
- RX_read_index = RX_read_index + clines - 1;
- EMAC_DEBUG("[directly passed the pkt of len (%u), new [rid (%x) != wid (%x)]]\n",
- copied, RX_read_index, wid);
- } else {
-
- EMAC_DEBUG("Broken packet received\n");
- memcpy_fast(dummy_pkt, pkt_ptr + 2, CSIZE - 2);
- copied = CSIZE - 2;
-
- while (copied < frame_len) {
- if(RX_read_index == wid) {
- /* FIXME: complete packet is not there. */
- /* discard the half packet, and return */
- printf("ERROR: Half packet received!!!, dropping it\n");
- return;
- }
- increment_RX_read_index();
- pkt_ptr = (uint8_t *)(buf + (RX_read_index * 32));
- uint16_t to_copy = MIN((frame_len - copied), CSIZE);
- memcpy_fast(dummy_pkt + copied, pkt_ptr, to_copy);
- copied = copied + to_copy;
- }
- pkt_to_upload = dummy_pkt;
- } /* end else: copy the pkt */
-
- EMAC_DEBUG("Following pkt received\n");
- show_packet(pkt_to_upload, copied);
- process_received_packet(pkt_to_upload, copied, true);
-
- } while (RX_read_index != wid);
-
- finish:
- /* processing the packet */
- eMAC_eMAC2_RX_Buffer_read_index_rid_wrf(&emac, core_id, RX_read_index);
- rb_RX_header[1] = RX_read_index;
- ++pkt_counter;
- EMAC_DEBUG("pkt no %" PRIx64 " processed. \n", pkt_counter);
- return;
-
-} /* end function: receive_frame_data */
-
-
-static void polling(void)
-{
- printf("started polling.....\n");
- while(1){
- receive_frame_data();
- }
-}
-
-
-static void read_out_regs(void)
-{
- char s[1000];
- s[0] = 0;
- EMAC_DEBUG("reading the registers\n");
-// eMAC_eMAC_start_IP_SCC_network_pr();
-// eMAC_eMAC_start_IP_SCC_network_reg_pr(s, 999, &emac);
- EMAC_DEBUG("### details[%s]\n", s);
-
- eMAC_eMAC_host_IP_addr_reg_pr(s, 999, &emac);
- EMAC_DEBUG("### details[%s]\n", s);
-
- eMAC_eMAC_host_GW_addr_reg_pr(s, 999, &emac);
- EMAC_DEBUG("### details[%s]\n", s);
-
- eMAC_eMAC_MAC_base_addr_upper_reg_pr(s, 999, &emac);
- EMAC_DEBUG("### MAC upper[%s]\n", s);
-
-
- eMAC_eMAC_MAC_base_addr_lower_reg_pr(s, 999, &emac);
- EMAC_DEBUG("### MAC lower[%s]\n", s);
-
-} /* end function: read_out_regs */
-
-
-/*****************************************************************
- * Transmit logic
- ****************************************************************/
-/*
- * pbuf_list_memcpy(addr + 2, skb->data, skb->len);
- * pbuf_list_memcpy(addr + 2, skb->data, bytes_to_copy);
- * pbuf_list_memcpy(addr, skb->data + bytes_to_copy, bytes_left);
- * */
-static void pbuf_list_memcpy(uint8_t *dst, struct client_closure *cl,
- size_t start_offset, size_t to_copy)
-{
- int pbuf_offset = 0;
- int copying = 0;
- int data_left = 0;
- int already_copied = 0;
- uint64_t pbuf_len = 0;
- struct shared_pool_private *spp = cl->spp_ptr;
- struct slot_data *sld = &spp->sp->slot_list[cl->tx_index].d;
- uint64_t rtpbuf = sld->no_pbufs;
-
- struct buffer_descriptor *buffer = find_buffer(sld->buffer_id);
-
- for (int idx = 0; idx < rtpbuf; idx++) {
- sld = &spp->sp->slot_list[cl->tx_index + idx].d;
- assert(buffer->buffer_id == sld->buffer_id);
-// paddr = (uint64_t) buffer->pa + sld->offset;
-
- /* check if this pbuf contains any data that is to be copied */
- if((pbuf_len + sld->len) < start_offset) {
- pbuf_len = (pbuf_len + sld->len);
- continue;
- }
- if(already_copied == 0) {
- /* Start offset lies somewhere in this pbuf.
- * So, this is the first pbuf where some data will get copied. */
- pbuf_offset = start_offset - pbuf_len;
- data_left = sld->len - pbuf_offset;
- } else {
- // copying already started. so, just continue onwards in this pbuf
- pbuf_offset = 0;
- data_left = sld->len;
- }
- if(pbuf_offset < 0){
- EMAC_DEBUG("idx %d, pbufs = %u, to copy %zu\n",
- idx, rtpbuf, to_copy);
- EMAC_DEBUG("start offset %zu, to_copy %zu\n", start_offset,
- to_copy);
- EMAC_DEBUG("pbuf_offset %d = start_offset(%zu) - "
- "pbuf_len (%"PRIu64")\n",
- pbuf_offset, start_offset, pbuf_len);
-
- EMAC_DEBUG("pbuflen (%"PRIu64") + (%"PRIu64") < "
- "start_offset(%zu)\n",
- pbuf_len, sld->len, start_offset);
- EMAC_DEBUG("prev pbuf len (%"PRIu64"), already copied %d, "
- "left %d\n", spp->sp->slot_list[cl->tx_index].d->len,
- already_copied, data_left);
- }
- assert(pbuf_offset >= 0);
- assert(data_left >= 0);
-
- copying = MIN(to_copy, data_left);
-
- uint8_t *src =((uint8_t *)buffer->va) + sld->offset
- + pbuf_offset;
-
- // FIXME: may be I should use memcpy_fast here!!
- memcpy_fast(dst + already_copied, src, copying);
- already_copied = already_copied + copying;
-
- if(already_copied == to_copy) {
- return;
- }
- pbuf_len = (pbuf_len + sld->len);
- } // end for:
-
- EMAC_DEBUG("ERROR: pbuf_list_memcpy: not enough data [%zu] in "
- "client_closure\n", to_copy);
- EMAC_DEBUG("pbufs = %u\n", rtpbuf);
- EMAC_DEBUG("already copied %d, left %d\n", already_copied, data_left);
- for (int idx = 0; idx < rtpbuf; idx++) {
- EMAC_DEBUG(" %d: pbuflen (%"PRIu64")\n", idx,
- spp->sp->slot_list[cl->tx_index + idx].d->len);
- }
- EMAC_DEBUG("start offset %zu, to_copy %zu\n", start_offset, to_copy);
-
- assert(!"Not enough data in pbuf_list to send");
-} // end function: pbuf_list_memcpy
-
-
-static uint64_t TX_pkt_counter = 0;
-
-// FIXME: dynamically calcluate this ring size
-#define eMAC_TX_RING_SIZE 1000
-uint64_t get_tx_free_slots_count(void)
-{
- // FIXME: dynamically calcluate this ring size
- return eMAC_TX_RING_SIZE;
-}
-
-errval_t transmit_pbuf_list(struct client_closure *cl)
-{
- uint8_t *addr = NULL;
- uint16_t read_offset = 0;
- int rest = 0;
- int packets = 0;
-
- assert(!"Using older version of communication library\n");
- abort();
- struct shared_pool_private *spp = cl->spp_ptr;
- struct slot_data *sld = &spp->sp->slot_list[cl->tx_index].d;
- uint64_t rtpbuf = sld->no_pbufs;
-
- // Find the length of entire packet
- uint64_t pkt_len = 0;
- for (int idx = 0; idx < rtpbuf; idx++) {
- pkt_len += spp->sp->slot_list[cl->tx_index + idx].d.len;
- }
-
-
-// assert(cl->rtpbuf == 1);
- if (pkt_len > TX_MAX_PKT_SIZE) {
- printf("ERROR: pkt too big (0x%"PRIu64")> %u\n",
- pkt_len, TX_MAX_PKT_SIZE);
- /* FIXME: maintain the stats of packet dropping */
- /* FIXME: define better error to return here */
- return ETHERSRV_ERR_CANT_TRANSMIT;
- }
- ++TX_pkt_counter;
-
-
- ++TX_write_index;
- if (TX_write_index > TX_max_slots ) {
- TX_write_index = 1;
- }
- packets = get_cachelines(pkt_len + 2);
- EMAC_DEBUG("^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n");
- EMAC_DEBUG("PKT_no:%"PRIu64", packet len: %"PRIu64", "
- "no. pbufs %"PRIu16", clines %d\n",
- TX_pkt_counter, pkt_len, rtpbuf, packets);
-
- eMAC_TX_Buffer_read_index_t idx_r;
- idx_r = eMAC_eMAC2_TX_Buffer_read_index_rd(&emac, core_id);
- read_offset = idx_r.rid;
-
- uint16_t volatile wid = 0;
- uint16_t volatile rid = 0;
-
- rid = rb_TX_header[0];
- wid = rb_TX_header[1];
-
- EMAC_DEBUG("TX rid: 0x%x, wid 0x%x\n", read_offset, TX_write_index);
- EMAC_DEBUG("TX_rid: 0x%x, _wid 0x%x\n", rid, wid);
-
- EMAC_DEBUG("TX rid: 0x%x, wid 0x%x\n", read_offset, TX_write_index);
-
- /* checking for overflow */
-/* if (TX_write_index == read_offset){
- printf("ERROR: no space left as write_index(%u) == read_index(%u)\n",
- TX_write_index, read_offset);
- return -1;
- }
-*/
-
-#ifdef OVERFLOW_CHECK
-again:
- int sum = 0;
- if (read_offset < TX_write_index) {
- sum = TX_max_slots - TX_write_index + read_offset - 1;
- } else if (read_offset > TX_write_index) {
- sum = read_offset - TX_write_index - 1;
- }
-
- if (sum < packets) {
- EMAC_DEBUG( "Warning: not enough space available. Retrying\n");
- goto again;
- }
-#endif // OVERFLOW_CHECK
-
- addr = TX_internal_memory_va + (TX_write_index * 32);
-
- /* Set frame length */
- ((uint8_t*)addr)[0] = pkt_len % 256;
- ((uint8_t*)addr)[1] = pkt_len / 256;
-
- size_t already_copied = 0;
- if (TX_write_index + packets - 1 <= TX_max_slots) {
- /* enough space, just copy */
- EMAC_DEBUG("######## TX: Simple case, just copy whole pkt ########\n");
- pbuf_list_memcpy(addr + 2, cl, 0, pkt_len);
-// my_memcpy(addr + 2, src, pkt_len);
- already_copied = already_copied + pkt_len;
- /* increment write ptr */
- TX_write_index += packets - 1;
- } else {
- /* wrap in offsets. first copy to the end, second at the starting
- * point
- */
- int bytes_left = pkt_len;
- int bytes_to_copy = (TX_max_slots - TX_write_index + 1) * 32 - 2;
-
- if (bytes_left < bytes_to_copy) {
- bytes_to_copy = bytes_left;
- }
-
- EMAC_DEBUG("#### special case: copy last %d bytes ####\n",
- bytes_to_copy);
-
- pbuf_list_memcpy(addr + 2, cl, 0, bytes_to_copy);
- //my_memcpy(addr + 2, src, bytes_to_copy);
- already_copied = already_copied + bytes_to_copy;
- bytes_left -= bytes_to_copy;
-
- if (bytes_left != 0) {
- TX_write_index = 1;
- addr = TX_internal_memory_va + 32;
-
- EMAC_DEBUG("#### special case: copy remaining %d bytes\n",
- bytes_left);
- pbuf_list_memcpy(addr, cl, already_copied, bytes_left);
- //my_memcpy(addr, src + bytes_to_copy, bytes_left);
- already_copied = already_copied + bytes_left;
-
- rest = bytes_left % 32;
- if (rest != 0) {
- rest = 32 - rest;
- }
- EMAC_DEBUG("#### Rest is %d\n", rest);
- TX_write_index += ((bytes_left + rest)/CSIZE) - 1;
- }
- }
- ((uint32_t *)TX_internal_memory_va)[0] = 2;
-// writel(2, priv->tx_buffer); // FIXME: what and why is this???
-
- /* set new write offset */
- EMAC_DEBUG("##### Update tx write offset: %d (read offset %d)\n",
- TX_write_index, read_offset);
- eMAC_eMAC2_TX_Buffer_write_index_wid_wrf(&emac, core_id, TX_write_index);
- cl1flushmb();
-
- EMAC_DEBUG("packet len: %"PRIu64", clines %d\n", pkt_len, packets);
- char s[1000];
- eMAC_eMAC2_TX_Buffer_read_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX read index [%s]\n", s);
-
- eMAC_eMAC2_TX_Buffer_write_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX write index [%s]\n", s);
-
- rid = rb_TX_header[0];
- wid = rb_TX_header[1];
-/* printf("END TX rid: 0x%x, wid 0x%x\n", read_offset, TX_write_index);
- printf("END TX_rid: 0x%x, _wid 0x%x\n", rid, wid);
-*/
- /* FIXME: update the stats about successfull packet transmissions */
-
-
- // Tell the client we sent them!!!
- for (int i = 0; i < rtpbuf; i++) {
- assert(!"FIXME: handle_tx_done should send back the opaque pointer");
- abort();
- // associated with buffer sent.
- //handle_tx_done(cl->app_connection, (cl->tx_index + i));
- handle_tx_done(NULL);
- } // end for:
-
-
-#if TRACE_ETHERSRV_MODE
- trace_event(TRACE_SUBSYS_NET, TRACE_EVENT_NET_NO_S,
- (uint32_t)cl);
-#endif // TRACE_ETHERSRV_MODE
-
-
- return SYS_ERR_OK;
-} /* end function: transmit_pbuf_list */
-
-
-static void initialize_TX(void)
-{
-
- char s[1000];
-
- /* 9.6.5.3 Initialization TX */
- uint8_t volatile *buf = TX_internal_memory_va;
-
- rb_TX = (uint8_t *)buf;
- rb_TX_header = (uint16_t *)rb_TX;
-
- EMAC_DEBUG("TX buffer mem: lva [%p] == lpa [%p]\n", TX_internal_memory_va,
- TX_internal_memory_pa);
-
- uint32_t physical_addr = (uint32_t)TX_internal_memory_pa;
- /* getting 34 bit address from 32 bit address */
- /* ref: SCC_EAS.pdf (section 8.2: System Address Lookup Table (LUT)) */
-
- /* step 1: get 24 bits from physical address */
-// physical_addr = physical_addr & 0x00FFFFFF;
-
-
- /* step 2: Get the address part generated by LUT */
- struct scc_frame_identity sf;
- errval_t err = invoke_scc_frame_identify(TX_capframe, &sf);
- if(err_is_fail(err)){
- USER_PANIC_ERR(err, "invoke_scc_frame_identify(TX_capframe): ");
- }
- EMAC_DEBUG("TX route details: route [%x], subdest [%x], addr[%x]\n",
- sf.route, sf.subdest, sf.addrbits);
-
- /* append */
- uint64_t big_address = ((sf.addrbits & 0x3FF) << 24) + physical_addr;
- lpaddr_t tmp_addr_p = 0;
- tmp_addr_p = (uint32_t)(big_address >> 5);
- EMAC_DEBUG("#### TX big addr %"PRIx64", in reg [%"PRIxLPADDR"]\n",
- big_address, tmp_addr_p);
-
- uint32_t tmp;
- tmp = (uint32_t)TX_internal_memory_pa;
- unsigned long long addr_offset = rx_tile_offset + tmp;
- EMAC_DEBUG("##### TX adder_offset [%llx]\n", addr_offset);
- addr_offset >>= 5;
- EMAC_DEBUG("##### TX in reg [%llx]\n", addr_offset);
-
-
- eMAC_eMAC2_TX_Buffer_start_addr_wr_raw(&emac, core_id, addr_offset);
-
- /*
- 1. Set TX buffer address (GRB+0x9900):
- Shift 5 times right and set address.
- */
-// eMAC_eMAC2_TX_Buffer_start_addr_ADDR_wrf(&emac, core_id, tmp_addr_p);
-
- /*
- 4. Set TX last index (GRB+0x9C00):
- Set last index to define buffer size (size = last index * 32).
- */
- eMAC_eMAC2_TX_Buffer_last_index_lid_wrf(&emac, core_id, TX_max_slots);
-
- s[0] = 0;
- eMAC_eMAC2_TX_Buffer_start_addr_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX start addr = %s\n", s);
-
- s[0] = 0;
- eMAC_eMAC2_TX_Buffer_last_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX write index = %s\n", s);
-
- cl1flushmb();
-
- /*
- 2. Read TX read index (GRB+0x9A00):
- Read TX read index (note that the read index is read only for SW,
- thus cannot be initialized).
- */
- s[0] = 0;
- eMAC_eMAC2_TX_Buffer_read_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX read index = %s\n", s);
-
- eMAC_TX_Buffer_read_index_t idx2;
- idx2 = eMAC_eMAC2_TX_Buffer_read_index_rd(&emac, core_id);
- uint16_t rid = idx2.rid;
-
- /*
- 3. Write TX write index (GRB+0x9B00):
- Set write index (both point to the same index now, thus the
- buffer is empty) and store value as driver internal write index.
- */
- eMAC_eMAC2_TX_Buffer_write_index_wid_wrf(&emac, core_id, rid);
- EMAC_DEBUG("TX rid (%u) == wid(%u)\n", rid, rid);
-
- s[0] = 0;
- eMAC_eMAC2_TX_Buffer_write_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX write index = %s\n", s);
-
- cl1flushmb();
-
-
- /* Write the value of Write-pointer, Read-pointer in the first block */
- rb_TX_header[0] = rid;
- rb_TX_header[1] = rid;
- TX_write_index = rid;
-
-// print_cline((uint8_t *)buf);
-
- /*
- 5. Set TX route/destination (GRB+0x9D00):
- Set route and destination depending on selected core
- (e.g. for core0 0x600).
- 0x0600 = 0b11000000000
- 110 00000000
- */
- eMAC_eMAC2_TX_routing_broute_wrf(&emac, core_id, sf.route);
- assert(sf.subdest <= 0b111);
- eMAC_eMAC2_TX_routing_bdest_wrf(&emac, core_id, (sf.subdest &0b111));
-
- s[0] = 0;
- eMAC_eMAC2_TX_routing_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX routing = %s\n", s);
-
- /*
- 6. Activate TX network port (GRB+0x9E00): Set to 1.
- */
- eMAC_eMAC2_TX_net_port_enable_enable_wrf(&emac, core_id, 1);
-
- s[0] = 0;
- eMAC_eMAC2_TX_net_port_enable_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("TX port enable = %s\n", s);
-
-} /* end function: initialize_TX */
-
-/*
-Determining the right MAC addresses can be done in different ways. The easiest way is to use the
-MAC Address Base Register (0x07e00 to 0x07e04) in the FPGA and to calculate the MAC address
-*/
-/* MAC address of core 0 00:45:4D:41:48:31 */
-/* [6] = {0x0, 0x45, 0x4D, 0x41, 0x48, 0x31}; MAC address */
-
-static void display_mac_address(uint8_t *mac)
-{
- printf("[%02x", mac[0]);
- for(int i = 1; i < 6; ++i){
- printf(":%02x", mac[i]);
- }
- printf("]\n");
-}
-
-
-
-static uint64_t get_mac_address(void)
-{
- uint64_t mac = 0;
-
-// uint8_t base_mac_addr[6];
- eMAC_eMAC_MAC_base_addr_upper_t mac_hi =
- eMAC_eMAC_MAC_base_addr_upper_reg_rd(&emac);
- mac = mac_hi.mac_upper;
- mac = mac << 32;
-
- eMAC_eMAC_MAC_base_addr_lower_t mac_low =
- eMAC_eMAC_MAC_base_addr_lower_reg_rd(&emac);
- mac = mac + mac_low.mac_lower;
-
- printf("Base mac address:");
- display_mac_address((uint8_t *)&mac);
-
-
- /* NOTE: This formula is used so that, MAC's generated will match the
- * SCC Linux distribution's MAC address. */
- mac = mac + (((1 << eMAC_PHY_id) * 0x100) + core_id);
- /* FIXME: core1 should get IP even with following line,
- * investigate why does it not get it?? */
-// mac = mac + (((1 << eMAC_PHY_id) * 0x100));
- eMAC_mac = mac;
- printf("Core MAC address:");
- display_mac_address((uint8_t *)&eMAC_mac);
- return eMAC_mac;
-} /* end function: get_mac_address */
-
-
-
-static int route[24][2] = {
- {0, 0},
- {0, 1},
- {0, 2},
- {0, 3},
- {0, 4},
- {0, 5},
- {1, 0},
- {1, 1},
- {1, 2},
- {1, 3},
- {1, 4},
- {1, 5},
- {2, 0},
- {2, 1},
- {2, 2},
- {2, 3},
- {2, 4},
- {2, 5},
- {3, 0},
- {3, 1},
- {3, 2},
- {3, 3},
- {3, 4},
- {3, 5}
-};
-
-
-static void initialize_RX(void)
-{
- char s[1000];
-
- /* 9.6.5.2 Initialization RX */
- uint8_t volatile *buf = (uint8_t *) RX_internal_memory_va;
-
- rb_RX = buf;
- rb_RX_header = (uint16_t *)rb_RX;
-
- EMAC_DEBUG("RX buffer mem: lva [%p] == lpa [%p]\n", RX_internal_memory_va,
- RX_internal_memory_pa);
-
- uint32_t physical_addr = (uint32_t)RX_internal_memory_pa;
- /* getting 34 bit address from 32 bit address */
- /* ref: SCC_EAS.pdf (section 8.2: System Address Lookup Table (LUT)) */
-
- /* step 1: get 24 bits from physical address */
-// physical_addr = physical_addr & 0x00FFFFFF;
-
-
- /* step 2: Get the address part generated by LUT */
- struct scc_frame_identity sf;
- errval_t err = invoke_scc_frame_identify(RX_capframe, &sf);
- if(err_is_fail(err)){
- USER_PANIC_ERR(err, "invoke_scc_frame_identify(TX_capframe): ");
- }
- EMAC_DEBUG("RX route details: route [%x], subdest [%x], addr[%x]\n",
- sf.route, sf.subdest, sf.addrbits);
-
- printf("#### phywsical addr %"PRIxLPADDR"\n", physical_addr);
- /* append */
- uint64_t big_address = ((sf.addrbits & 0x3FF) << 24) + physical_addr;
-
- /*
- 1. Set RX buffer address (GRB+0x9000):
- Shift 5 times to the right and set address.
- */
- lpaddr_t tmp_addr_p = 0;
- tmp_addr_p = (uint32_t)(big_address >> 5);
- EMAC_DEBUG("#### big addr %"PRIx64", in reg [%"PRIxLPADDR"]\n",
- big_address, tmp_addr_p);
-
- uint32_t tmp;
- tmp = (uint32_t)RX_internal_memory_pa;
- unsigned long long addr_offset = rx_tile_offset + tmp;
- EMAC_DEBUG("##### adder_offset [%llx]\n", addr_offset);
- addr_offset >>= 5;
- EMAC_DEBUG("##### in reg [%llx]\n", addr_offset);
-
- eMAC_eMAC2_RX_Buffer_start_addr_wr_raw(&emac, core_id, addr_offset);
-
-// eMAC_eMAC2_RX_Buffer_start_addr_wr_raw(&emac, core_id, (uint32_t)tmp_addr_p);
-// eMAC_eMAC2_RX_Buffer_start_addr_ADDR_wrf(&emac, core_id, tmp_addr_p);
-
- /*
- 4. Set RX last index (GRB+0x9300):
- Set last index to define buffer size (size = last index * 32).
- */
- eMAC_eMAC2_RX_Buffer_last_index_lid_wrf(&emac, core_id, RX_max_slots);
-
- s[0] = 0;
- eMAC_eMAC2_RX_Buffer_start_addr_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX start addr = %s\n", s);
-
- s[0] = 0;
- eMAC_eMAC2_RX_Buffer_last_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX write index = %s\n", s);
-
- cl1flushmb();
-
- /*
- 2. Read RX write index (GRB+0x9200):
- Read write index (note that the write index registers are read
- only by SW, thus cannot be set to an initial value).
- */
-
- s[0] = 0;
- eMAC_eMAC2_RX_Buffer_write_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX write index = %s\n", s);
-// uint16_t idx = eMAC_eMAC2_RX_Buffer_write_index_wid_rdf(&emac, core_id);
- eMAC_RX_Buffer_write_index_t idx2;
- idx2 = eMAC_eMAC2_RX_Buffer_write_index_rd(&emac, core_id);
- uint16_t wid = idx2.wid;
- /*
- 3. Set RX write index to RX read index (GRB+0x9100):
- Set read index (both point to the same index now, thus the buffer is empty) and store value as
- driver internal read index.
- */
- eMAC_eMAC2_RX_Buffer_read_index_rid_wrf(&emac, core_id, wid);
- EMAC_DEBUG("RX rid (%u) == wid(%u)\n", wid, wid);
-
- s[0] = 0;
- eMAC_eMAC2_RX_Buffer_read_index_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX write index = %s\n", s);
-
- cl1flushmb();
-
- /* Write the value of Write-pointer, Read-pointer in the first block */
- rb_RX_header[0] = wid;
- rb_RX_header[1] = wid;
- RX_read_index = wid;
-
-// print_cline((uint8_t *)buf);
-
- /*
- 5. Set RX route/destination (GRB+0x9500):
- Set route and destination depending on selected core
- (e.g. for core0 0x600).
- 0x0600 = 0b11000000000
- 110 000 00000
- */
-
-
-
- uint8_t route_val = (route[core_id/2][0] << 4) |(route[core_id/2][1]);
- assert(sf.subdest <= 0b111);
-
-
- uint32_t rr = 0;
-
- rr = rr + ((core_id & 1) << (32 - (5 + 3)));
- rr = rr + ((route_val & 0xFF) << (32 - (5 + 3 + 8)));
- rr = rr + ((sf.subdest & 0b111) << (32 - (5 + 3 + 8 + 5 + 3)));
- rr = rr + ((sf.route) << (32 - (5 + 3 + 8 + 5 + 3 + 8)));
-/*
- eMAC_eMAC2_RX_routing_broute_wrf(&emac, core_id, sf.route);
-
- eMAC_eMAC2_RX_routing_bdest_wrf(&emac, core_id, (sf.subdest & 0b111));
-
-
- eMAC_eMAC2_RX_routing_iroute_wrf(&emac, core_id, route_val);
- eMAC_eMAC2_RX_routing_idest_wrf(&emac, core_id, (core_id & 1));
-*/
- eMAC_eMAC2_RX_routing_wr_raw(&emac, core_id, rr);
- s[0] = 0;
- uint32_t rrr = eMAC_eMAC2_RX_routing_rd_raw(&emac, core_id);
- eMAC_eMAC2_RX_routing_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX routing = %s\n", s);
- if(rr != rrr){
- EMAC_DEBUG("WARNING: Prepared values do not match set values\n");
- }
- EMAC_DEBUG( "Raw value = [%"PRIx32"] and prepared[%"PRIx32"]\n", rrr, rr);
- /*
- 6. Set RX hi MAC address (GRB+0x9600):
- Set high MAC address (e.g. 0x0045).
- */
- uint64_t mac_addr_holder = get_mac_address();
- uint16_t mac_hi = (mac_addr_holder >> 32) & 0xFFFF;
- eMAC_eMAC2_RX_net_port_MAC_high_mac_hi_wrf(&emac, core_id, mac_hi);
-
- /*
- 7. Set RX lo MAC address (GRB+0x9700):
- Set low MAC address (e.g. 0x414D4500).
- */
- uint32_t mac_low = mac_addr_holder & 0xFFFFFFFF;
- eMAC_eMAC2_RX_net_port_MAC_low_mac_lo_wrf(&emac, core_id, mac_low);
-
- s[0] = 0;
- eMAC_eMAC2_RX_net_port_MAC_high_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX mac high = [%s]\n", s);
-
- s[0] = 0;
- eMAC_eMAC2_RX_net_port_MAC_low_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX mac low = [%s]\n", s);
-
- /*
- 8. Activate RX network port (GRB+0x9800):
- Set to 1.
- */
- eMAC_eMAC2_RX_net_port_enable_enable_wrf(&emac, core_id, 1);
-
- s[0] = 0;
- eMAC_eMAC2_RX_net_port_enable_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("RX port enable = %s\n", s);
-
-} /* end function: initialize_RX */
-
-
-
-/* CRB TILEID */
-#define RCK_TILEID 0x0100
-static long local_crb_offset = 0xF8000000;
-
-static uint32_t read_32(void *base, int x)
-{
- uint32_t *addr = (uint32_t *)(base + x);
- return(*addr);
-}
-
-static void rx_init_wrapper(void)
-{
- unsigned long long offset = 0;
- int tmp = 0;
- int x = 0;
- int y = 0;
- int z = 0;
- int position = 0;
- int lmode = 0;
- int subdest = 0;
- int lroute = 0;
- uint16_t framesize_bits = 13;
-
-
- /******** mapping the device ***********/
- struct capref frame;
- errval_t err = slot_alloc(&frame);
- assert(err_is_ok(err));
- EMAC_DEBUG("rck:calling system call to get cap for rck registers\n");
- EMAC_DEBUG("rck:with values %lx, %x\n", local_crb_offset, framesize_bits);
- err = sys_debug_feign_frame_cap(frame, local_crb_offset, framesize_bits);
- if(err_is_fail(err)) {
- USER_PANIC_ERR(err, "rck:feign_frame_cap failed:");
- assert(!"rck:feign_frame_cap failed");
- }
- assert(err_is_ok(err));
-
- struct frame_identity id;
- err = invoke_frame_identify(frame, &id);
- assert(err_is_ok(err));
-
- EMAC_DEBUG("rck:device register base = %" PRIxGENPADDR ", size = %u\n",
- id.base, id.bits);
-
-
- void *driver_memory_va = NULL;
- EMAC_DEBUG("rck:frame alloc done\n");
- errval_t r = vspace_map_one_frame_attr(&driver_memory_va,
- (1<<framesize_bits), frame,
- VREGION_FLAGS_READ_WRITE_NOCACHE, NULL, NULL);
- if (err_is_fail(r)) {
- assert(!"rck:vspace_map_one_frame failed");
- }
- EMAC_DEBUG("rck:vspace done\n");
-
- assert(driver_memory_va != NULL);
-
- /******** mapping the device ***********/
-
- /* Read tile id */
- tmp = read_32(driver_memory_va, RCK_TILEID);
- /* bits 06:03 */
- x = (tmp >> 3) & 0x0f;
- /* bits 10:07 */
- y = (tmp >> 7) & 0x0f;
- /* bits 02:00 */
- z = (tmp) & 0x07;
-
- position = 12 * y + 2 * x + z;
- assert(position == core_id);
- EMAC_DEBUG("Location:\n");
- EMAC_DEBUG(" X: %d Y: %d, Z: %d => Position: %d\n", x, y, z, position);
-
- /* Depending on core location read own private data
- * (offset, subdest, route)
- */
- if (z == 0) {
- tmp = read_32(driver_memory_va, 0x800);
- } else {
- tmp = read_32(driver_memory_va, 0x1000);
- }
- EMAC_DEBUG("#####read success %x, address bits[%x]\n", tmp, (tmp & 0x3FF));
-
- offset = (unsigned long long)((unsigned long long) tmp & 0x3FF) << 24;
- subdest = (tmp >> 10) & 0x07;
- lroute = (tmp >> 13) & 0xFF;
- lmode = (subdest << 8) + lroute;
- rx_tile_offset = offset;
- rx_mode = lmode;
- rx_pos = (y << 4) | x;
-
- EMAC_DEBUG("Using offset: %llx, route[%x], subdest[%x], mode[%x]\n",
- offset, lroute, subdest, lmode);
-}
-
-
-
-
-
-
-static void init_Xilinx_IP_block_eMAC2(void)
-{
- /* 9.6.5.1 Initialization Xilinx IP (block eMAC2) */
-
- /* In Xilinx IP Disable flow control */
- eMAC_eMAC2_flow_control_conf_RX_FC_enable_wrf(&emac, 0);
- eMAC_eMAC2_flow_control_conf_TX_FC_enable_wrf(&emac, 0);
-
- /* In Xilinx, enable transmitter, receiver */
- eMAC_eMAC2_receiver_conf_1_RX_wrf(&emac, 1);
- eMAC_eMAC2_transmiter_conf_TX_wrf(&emac, 1);
-
- /* In Xilinx, enable full duplex for transmitter, receiver */
- eMAC_eMAC2_receiver_conf_1_HD_wrf(&emac, 0);
- eMAC_eMAC2_transmiter_conf_HD_wrf(&emac, 0);
-
- /* FIXME: use 1GB as it was shown in example */
- /* In Xilinx, set MAC speed (setting to 10 Mb/s )*/
- eMAC_eMAC2_ethernet_mac_conf_LINK_SPEED_wrf(&emac, 0b10);
-
- /* Set promiscuous mode */
-// eMAC_eMAC2_address_filter_mode_PM_wrf(&emac, 1);
-
-} /* end function: init_Xilinx_IP_block_eMAC2 */
-
-
-
-
-/*****************************************************************
-* initialize the card
- *****************************************************************/
-
-
-static void *setup_internal_memory(void)
-{
- struct frame_identity frameid;
- lpaddr_t mem;
- errval_t r;
-
- EMAC_DEBUG("Setting up internal memory for receive\n");
-
- ram_set_affinity(0x13000000, 0x14000000);
-
- r = frame_alloc(&RX_capframe, BUFF_SIZE, NULL);
- if(err_is_fail(r)) {
- assert(!"frame_alloc for RX failed");
- }
-
- r = frame_alloc(&TX_capframe, BUFF_SIZE, NULL);
- if(err_is_fail(r)) {
- assert(!"frame_alloc for TX failed");
- }
- ram_set_affinity(0x0, 0x0);
-
- /********* Setting for RX memory ***********/
- r = invoke_frame_identify(RX_capframe, &frameid);
- assert(err_is_ok(r));
- mem = frameid.base;
-
- RX_internal_memory_pa = (void*)mem;
-
- r = vspace_map_one_frame_attr(&RX_internal_memory_va,
- BUFF_SIZE, RX_capframe,
- VREGION_FLAGS_READ_WRITE_NOCACHE, NULL, NULL);
- if (err_is_fail(r)) {
- assert(!"vspace_map_one_frame failed for RX");
- }
-
- assert(RX_internal_memory_pa);
- assert(RX_internal_memory_va);
-
- memset(RX_internal_memory_va, 0x00, CSIZE);
- memset(RX_internal_memory_va + CSIZE, 0xDA, CSIZE);
- EMAC_DEBUG("setup_internal_mem (RX) (size 0x%x), lpa[%p] = lva[%p]\n",
- BUFF_SIZE, RX_internal_memory_pa, RX_internal_memory_va);
-
-
- /***** Setting for TX memory *****/
- r = invoke_frame_identify(TX_capframe, &frameid);
- assert(err_is_ok(r));
- mem = frameid.base;
-
- TX_internal_memory_pa = (void*)mem;
-
- r = vspace_map_one_frame_attr(&TX_internal_memory_va,
- BUFF_SIZE, TX_capframe,
- VREGION_FLAGS_READ_WRITE_NOCACHE, NULL, NULL);
- if (err_is_fail(r)) {
- assert(!"vspace_map_one_frame failed for TX");
- }
-
- assert(TX_internal_memory_pa);
- assert(TX_internal_memory_va);
-
- memset(TX_internal_memory_va, 0x00, CSIZE);
- memset(TX_internal_memory_va + CSIZE, 0xDA, CSIZE);
- EMAC_DEBUG("setup_internal_mem (TX) (size 0x%x), lpa[%p] = lva[%p]\n",
- BUFF_SIZE, TX_internal_memory_pa, TX_internal_memory_va);
-
-
- return RX_internal_memory_va;
-}
-
-
-static bool can_handle_packet(void)
-{
-
- if(RX_internal_memory_pa == NULL || RX_internal_memory_va == NULL) {
- EMAC_DEBUG("no internal memory yet#####.\n");
- return false;
- }
-// return true;
-
- // Mask local APIC IRQ (prob not needed)
- if(waiting_for_netd()){
- EMAC_DEBUG("netd not connected\n");
- return false;
- }
-
- return true;
-} /* end function: can_handle_packet */
-
-
-
-static void interrupt_handler(void *dummy)
-{
- // Check that interrupt came from my device
- /* status = readl(RA(IRQ_STATUS, priv->pid * 2)); */
- if(!(eMAC_PIC_irq_status_rd(&emac, core_id) & (1 << eMAC_PHY_id))) {
- printf("interrupt from wrong device!\n");
- /* assuming that someone else will handle that error */
- /* abort(); */
- return;
- }
-
- EMAC_DEBUG("######## interrupt came!\n");
- if(can_handle_packet()){
- // Process packets
- EMAC_DEBUG("#### interrupt handling!\n");
- ++interrupt_counter;
-#if TRACE_ETHERSRV_MODE
- trace_event(TRACE_SUBSYS_NET, TRACE_EVENT_NET_NI_I, 0);
-#endif // TRACE_ETHERSRV_MODE
- receive_frame_data();
- }
-
- // EOI
- eMAC_PIC_irq_reset_wr(&emac, core_id, (1 << eMAC_PHY_id));
-}
-
-#if 0
-static void clear_interrupt(void)
-{
- // TODO:
- // Unset APIC mask (probably in kernel, prob not needed)
- // Unset interrupt bit in local CRB (prob in kernel)
- // Reset interrupt for eMAC2
-
- // For reference:
- /* /\* Set APIC mask *\/ */
- /* #define EMAC_LVT APIC_LVT1 */
- /* unset_lapic_mask(EMAC_LVT, dev->irq == 3); */
-
- /* /\* Set interrupt bit *\/ */
- /* #define EMAC_IRQ_MASK 0x00000001 */
- /* tmp = readl((void*)priv->irq_address); */
- /* tmp &= ~(EMAC_IRQ_MASK); */
- /* writel(tmp, (void*)priv->irq_address); */
-
- eMAC_PIC_irq_reset_wr(&emac, core_id, (1 << eMAC_PHY_id));
-
- /* /\* Reset *\/ */
- /* #define EMAC2 0x04 */
- /* tmp = priv->device == EMAC2; */
- /* writel(tmp, RA(IRQ_RESET, priv->pid * 2)); */
-}
-#endif
-
-
-static void eMAC_set_interrupt(void)
-{
- errval_t r;
-
- // Setup interrupt handling
- // Send EOI
- /* FIXME: set IRQ based on which EMAC, instead of hardcoding it*/
- eMAC_PIC_irq_reset_wr(&emac, core_id, (1 << eMAC_PHY_id));
-
- // Unmask IRQ
- uint64_t irqmask = eMAC_PIC_irq_mask_rd(&emac, core_id);
-
- /* tmp = readl(RA(IRQ_MASK, priv->pid * 2)); */
- /* FIXME: Don't hardcode EMAC2_IRQ */
- eMAC_PIC_irq_mask_wr(&emac, core_id, irqmask & ~((1 << eMAC_PHY_id)));
- /* eMAC_PIC_irq_mask_wr(&emac, core_id, 0); */
-
- char s[1000];
- eMAC_PIC_irq_status_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("irq status [%s]\n", s);
-
- // Configure which pin to use on our core (always LINT1)
- // eMAC_PIC_irq_config_wr(&emac, core_id, EMAC_IRQ_CONFIG);
- eMAC_PIC_irq_config_wr(&emac, core_id, EMAC_IRQ_CONFIG);
- /* writel(EMAC_IRQ_CONFIG, RA(IRQ_CONFIG, priv->pid)); */
-
- // Register interrupt handler
- uint32_t vector;
- r = inthandler_setup(interrupt_handler, NULL, &vector);
- if(err_is_fail(r)) {
- USER_PANIC_ERR(r, "inthandler_setup");
- }
- assert(vector == 0);
- EMAC_DEBUG("Interrupt set\n");
-
- cl1flushmb();
-
- eMAC_PIC_irq_status_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("irq status [%s]\n", s);
- eMAC_PIC_irq_mask_pri(s, 999, &emac, core_id);
- EMAC_DEBUG("irq mask [%s]\n", s);
-
- /* writel(tmp & ~(priv->device), RA(IRQ_MASK, priv->pid * 2)); */
-
-} /* end function: eMAC_set_interrupt */
-
-
-
-/**
- * Initialize RCK driver by mapping in config registers and MPBs.
- */
-void eMAC_hwinit(uint8_t phy_id)
-{
- errval_t r;
-// void *emac_base = NULL;
-
- RX_max_slots = SLOTS - 1; // initializing the value
-
-
- core_id = disp_get_core_id();
- eMAC_PHY_id = phy_id;
- EMAC_DEBUG("eMAC driver was called for eMAC%x on core %d(0x%x)\n",
- eMAC_PHY_id, core_id, core_id);
- /* Map the needed address-space on memory. */
-
- struct capref frame;
- errval_t err = slot_alloc(&frame);
- assert(err_is_ok(err));
- EMAC_DEBUG("calling system call to get cap for device registers\n");
- EMAC_DEBUG("with values %x, %x\n", EMAC_CFG_REGS_BASE, 16);
- err = sys_debug_feign_frame_cap(frame, EMAC_CFG_REGS_BASE,
- 16);
- if(err_is_fail(err)) {
- USER_PANIC_ERR(err, "feign_frame_cap failed:");
- assert(!"feign_frame_cap failed");
- }
- assert(err_is_ok(err));
-
- struct frame_identity id;
- err = invoke_frame_identify(frame, &id);
- assert(err_is_ok(err));
-
- EMAC_DEBUG("device register base = %" PRIxGENPADDR ", size = %u\n",
- id.base, id.bits);
-
-
- void *driver_memory_va = NULL;
- EMAC_DEBUG("frame alloc done\n");
- r = vspace_map_one_frame_attr(&driver_memory_va,
- EMAC_CFG_REGS_SIZE, frame,
- VREGION_FLAGS_READ_WRITE_NOCACHE, NULL, NULL);
- if (err_is_fail(r)) {
- assert(!"vspace_map_one_frame failed");
- }
- EMAC_DEBUG("vspace done\n");
-
- assert(driver_memory_va != NULL);
-
- eMAC_initialize(&emac, driver_memory_va);
-
- setup_internal_memory();
- EMAC_DEBUG("internal memory set\n");
-
-
-// test_address_conversion();
- read_out_regs();
-// return;
-
- /*
- * The software driver is responsible for configuring
- * and enabling the network ports.
- * Each driver does this independently for its own register sets.
- */
-
- /* Reset the register values */
- /* FIXME: should I do this? as it is not told in manual. */
-/*
- eMAC_eMAC2_receiver_conf_1_RST_wrf(&emac, 1);
- eMAC_eMAC2_transmiter_conf_RST_wrf(&emac, 1);
-*/
-
-// EMAC_DEBUG("eMAC driver resetted\n");
- /* Initialize the Xilinx block */
- init_Xilinx_IP_block_eMAC2();
-
- EMAC_DEBUG("### eMAC driver initiated\n");
- /* Initialize RX mode */
- rx_init_wrapper();
- initialize_RX();
- EMAC_DEBUG("eMAC driver: initialized RX\n");
-
- initialize_TX();
- EMAC_DEBUG("eMAC driver: initialized TX\n");
-
-// high_level_handler = handler;
- eMAC_set_interrupt();
- if (core_id == 55 )polling();
-} /* end function: eMAC_init */
-
+++ /dev/null
-/**
- * \file
- * \brief X86 inline asm utilities and defines
- */
-
-/*
- * Copyright (c) 2007, 2008, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef __EMAC_SPACES_H
-#define __EMAC_SPACES_H
-
-typedef int mackerel_one_byte_t;
-
-/*
- * Reading from Model-Specific Registers
- *
- * You might be tempted, gentle reader, to wonder why one should
- * bother with the apparently pointless volatile declaration here,
- * particularly if (as is the case with Barrelfish) rdmsr is an asm
- * volatile inline function anyway. If you don't understand why,
- * you're not qualified to change this code. If you do, you'll
- * understand why it should not be changed, as long as we are
- * compiling with GCC.
- */
-static inline uint32_t eMAC_one_byte_read_32(eMAC_t *base, mackerel_one_byte_t idx)
-{
- volatile uint32_t r = 0;
-// r = rdmsr(idx);
- assert(!"NYI");
- return r;
-}
-
-static inline uint64_t eMAC_one_byte_read_64(eMAC_t *base, mackerel_one_byte_t idx)
-{
- volatile uint64_t r = 0;
-// r = rdmsr(idx);
- assert(!"NYI");
- return r;
-}
-
-/*
- * Writing to Model-Specific Registers
- */
-static inline void eMAC_one_byte_write_32(eMAC_t *base, mackerel_one_byte_t idx, uint32_t v)
-{
-// wrmsr(idx, v);
- assert(!"NYI");
- return;
-}
-static inline void eMAC_one_byte_write_64(eMAC_t *base, mackerel_one_byte_t idx, uint64_t v)
-{
-// wrmsr(idx, v);
- assert(!"NYI");
- return;
-}
-
-#endif // __EMAC_SPACES_H
+++ /dev/null
---------------------------------------------------------------------------
--- Copyright (c) 2007-2010, ETH Zurich.
--- All rights reserved.
---
--- This file is distributed under the terms in the attached LICENSE file.
--- If you do not find this file, copies can be found by writing to:
--- ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
---
--- Hakefile for /usr/drivers/vbe
---
---------------------------------------------------------------------------
-
-[ build application { target = "sif",
- cFiles = [ "main.c", "sif.c" ],
- architectures = [ "x86_64" ],
- addLibraries = [ "pci" ],
- mackerelDevices = [ "crb_sif" ]
- }
-]
+++ /dev/null
-/**
- * \file
- * \brief SIF driver service handling.
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <barrelfish/barrelfish.h>
-#include <barrelfish/nameservice_client.h>
-
-#include "sif.h"
-
-#define PCI_CLASS_MEMORY 0x5
-#define PCI_DEVICE_ROCKYLAKE 0xc148
-
-int main(int argc, char *argv[])
-{
- // Register our device driver
- int r = pci_client_connect();
- assert(r == 0);
-
- r = pci_register_driver_irq(sif_init, PCI_CLASS_MEMORY, PCI_DONT_CARE,
- PCI_DONT_CARE, PCI_VENDOR_INTEL,
- PCI_DEVICE_ROCKYLAKE,
- PCI_DONT_CARE, PCI_DONT_CARE, PCI_DONT_CARE,
- sif_interrupt_handler, NULL);
- assert(r == 0);
-
- messages_handler_loop();
-}
+++ /dev/null
-/**
- * \file
- * \brief SIF driver.
- *
- * \bug Currently, this will only init the device, not drive it yet.
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#include <stdio.h>
-#include <assert.h>
-#include <inttypes.h>
-#include "sif.h"
-#include <dev/crb_sif_dev.h>
-
-static struct crb_sif_t sif;
-
-void sif_interrupt_handler(void *arg)
-{
- printf("SIF interrupt!\n");
-}
-
-void sif_init(struct device_mem *bar_info, int nr_mapped_regions)
-{
- struct device_mem *bar = &bar_info[0];
-
- assert(nr_mapped_regions == 1);
-
- map_device(bar);
-
- printf("SIF BAR at: %" PRIxGENPADDR ", size: %lu, mapped at: %p"
- "\n", bar->paddr, bar->bytes, bar->vaddr);
-
- crb_sif_initialize(&sif, (void *)bar->vaddr);
-
- printf("sif_init: BITSID: 0x%" PRIx32 "\n", crb_sif_id0_rd(&sif));
-
- uint64_t grbtest = crb_sif_id1_rd(&sif) |
- ((uint64_t)crb_sif_id2_rd(&sif) << 32);
- printf("sif_init: grbtest: 0x%" PRIx64 "\n", grbtest);
-
- crb_sif_id2_wr(&sif, 0x35377353);
- crb_sif_id1_wr(&sif, (grbtest & 0xffffffff) + 1);
-
- grbtest = crb_sif_id1_rd(&sif) | ((uint64_t)crb_sif_id2_rd(&sif) << 32);
- printf("sif_init: grbtest: 0x%" PRIx64 "\n", grbtest);
-
- char str[256];
- crb_sif_dcsr1_pr(str, 256, &sif);
- printf("%s\n", str);
-
- crb_sif_dlwstat_pr(str, 256, &sif);
- printf("%s\n", str);
-
- crb_sif_dltrsstat_pr(str, 256, &sif);
- printf("%s\n", str);
-
- crb_sif_dmisccont_pr(str, 256, &sif);
- printf("%s\n", str);
-}
+++ /dev/null
-/**
- * \file
- * \brief SIF driver.
- */
-
-/*
- * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
- * All rights reserved.
- *
- * This file is distributed under the terms in the attached LICENSE file.
- * If you do not find this file, copies can be found by writing to:
- * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
- */
-
-#ifndef SIF_H
-#define SIF_H
-
-#include <stdint.h>
-#include <barrelfish/barrelfish.h>
-#include <pci/pci.h>
-
-void sif_init(struct device_mem *bar_info, int nr_mapped_regions);
-void sif_interrupt_handler(void *arg);
-
-#endif
#elif defined(__x86_64__)
# define MONITOR_NAME BF_BINARY_PREFIX "x86_64/sbin/monitor"
# define MEM_SERV_NAME BF_BINARY_PREFIX "x86_64/sbin/mem_serv"
-#elif defined(__scc__)
-# define MONITOR_NAME BF_BINARY_PREFIX "scc/sbin/monitor"
-# define MEM_SERV_NAME BF_BINARY_PREFIX "scc/sbin/mem_serv"
#elif defined(__i386__)
# define MONITOR_NAME BF_BINARY_PREFIX "x86_32/sbin/monitor"
# define MEM_SERV_NAME BF_BINARY_PREFIX "x86_32/sbin/mem_serv"
/* Load monitor */
printf("Spawning monitor (%s)...\n", MONITOR_NAME);
struct spawninfo monitor_si;
-#ifdef __scc__
- if(argc > 2) {
- assert(argc == 5);
- char appargs[1024];
- snprintf(appargs, 1024, "%s %s %s", argv[2], argv[3], argv[4]);
- monitor_si.codeword = 0xcafebabe;
- monitor_si.append_args = appargs;
- }
-#endif
err = spawn_load_with_bootinfo(&monitor_si, bi, MONITOR_NAME, my_core_id);
if (err_is_fail(err)) {
return err_push(err, INIT_ERR_SPAWN_MONITOR);
}
#endif
-#ifdef CONFIG_INTERCONNECT_DRIVER_UMP
-#if 0 // XXX: Disabled until SCC has a decent memory allocator
- /* Give monitor the foreign frame capability */
- dest.cnode = si->taskcn;
- dest.slot = TASKCN_SLOT_MON_URPC;
- src.cnode = cnode_task;
- src.slot = TASKCN_SLOT_MON_URPC;
- err = cap_copy(dest, src);
- if (err_is_fail(err)) {
- return err_push(err, INIT_ERR_COPY_UMP_CAP);
- }
-#endif
-#endif // CONFIG_INTERCONNECT_DRIVER_UMP
-
return SYS_ERR_OK;
}
#include <if/monitor_defs.h>
#include <if/spawn_rpcclient_defs.h>
-#ifdef __scc__
-#include <barrelfish_kpi/shared_mem_arch.h>
-#endif
-
#include "skb.h"
#include "args.h"
/// simple slot allocator used by MM
static struct slot_prealloc percore_slot_alloc;
-#ifndef __scc__
static struct mm *mm_slots = &mm_percore;
-#else
-static struct mm *mm_slots = &mm_local;
-#endif
#if 0
static void dump_ram_region(int index, struct mem_region* m)
info.u.ram.bits, &mem_avail);
}
-#ifdef __scc__
-static errval_t local_free(struct capref ramcap)
-{
- struct capability info;
- errval_t ret;
-
- ret = debug_cap_identify(ramcap, &info);
- if (err_is_fail(ret)) {
- return err_push(ret, MON_ERR_CAP_IDENTIFY);
- }
-
- if (info.type != ObjType_RAM) {
- return SYS_ERR_INVALID_SOURCE_TYPE;
- }
-
- return do_free(&mm_local, ramcap, info.u.ram.base,
- info.u.ram.bits, &mem_local);
-}
-#endif
-
errval_t percore_free_handler_common(struct capref ramcap, genpaddr_t base,
uint8_t bits)
{
-#ifndef __scc__
return do_free(&mm_percore, ramcap, base, bits, &mem_avail);
-#else
- if (base < SHARED_MEM_MIN) {
- return do_free(&mm_local, ramcap, base, bits, &mem_local);
- } else {
- return do_free(&mm_percore, ramcap, base, bits, &mem_avail);
- }
-#endif
}
memsize_t mem_available_handler_common(void)
{
errval_t err;
-#ifdef __scc__
- // first try local memory
- err = do_alloc(&mm_local, ret, bits, minbase, maxlimit, &mem_local);
-
- // then try the general percore memory
- if (err_is_fail(err)) {
- err = percore_alloc(ret, bits, minbase, maxlimit);
- }
-#else
// first try the general percore memory
err = percore_alloc(ret, bits, minbase, maxlimit);
if (err_is_fail(err)) {
err = do_alloc(&mm_local, ret, bits, minbase, maxlimit, &mem_local);
}
-#endif
return err;
}
}
}
// make the cap available for a subsequent alloc
-#ifndef __scc__
percore_free(cap);
-#else
- local_free(cap);
-#endif
return SYS_ERR_OK;
}
}
// do the actual allocation
-#ifndef __scc__
ret = percore_alloc(&cap, bits, minbase, maxlimit);
-#else
- ret = local_alloc(&cap, bits, minbase, maxlimit);
-#endif
if (err_is_fail(ret)) {
// debug_printf("percore_alloc(%d (%lu)) failed\n", bits, 1UL << bits);
return err_push(err, MM_ERR_SLOT_ALLOC_INIT);
}
-#ifdef __scc__
- ram_set_affinity(0, EXTRA_SHARED_MEM_MIN);
- err = init_mm(&mm_local, local_nodebuf, sizeof(local_nodebuf),
- &percore_slot_alloc, &mem_local, &mem_total);
- if (err_is_fail(err)) {
- return err;
- }
- ram_set_affinity(SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-#endif
err = init_mm(&mm_percore, percore_nodebuf, sizeof(percore_nodebuf),
&percore_slot_alloc, &mem_avail, &mem_total);
if (err_is_fail(err)) {
return err;
}
-#ifndef __scc__
err = init_mm(&mm_local, local_nodebuf, sizeof(local_nodebuf),
&percore_slot_alloc, &mem_local, &mem_total);
if (err_is_fail(err)) {
return err;
}
-#endif
#ifdef MEMSERV_AFFINITY
set_affinity(core);
#endif
-#ifdef __scc__
- // Suck up private RAM
- ram_set_affinity(0, EXTRA_SHARED_MEM_MIN);
-#endif
-
// determine how much memory we need to get to fill up the percore mm
percore_mem -= mem_total; // memory we've already taken
percore_mem -= LOCAL_MEM; // memory we'll take for mm_local
-#ifdef __scc__
- // Take all of private RAM we can get
- percore_mem = PERCORE_MEM_SIZE;
-#endif
-
uint8_t percore_bits = log2floor(percore_mem);
if (percore_bits > MAXSIZEBITS) {
percore_bits = MAXSIZEBITS;
mem_local += fill_mm(&mm_local, LOCAL_MEM, LOCAL_MEMBITS, &mem_total);
-#ifdef __scc__
- ram_set_affinity(SHARED_MEM_MIN + (PERCORE_MEM_SIZE * disp_get_core_id()),
- SHARED_MEM_MIN + (PERCORE_MEM_SIZE * (disp_get_core_id() + 1)));
-#endif
-
mem_avail += fill_mm(&mm_percore, percore_mem, percore_bits, &mem_total);
// from now on we don't care where memory comes from anymore
#define NAME_LEN 20
#define MEMSERV_PERCORE_DYNAMIC
-#ifndef __scc__
-# define MEMSERV_AFFINITY
-#endif
+#define MEMSERV_AFFINITY
// appropriate size type for available RAM
typedef genpaddr_t memsize_t;
#define MINSIZEBITS OBJBITS_DISPATCHER ///< Min size of each allocation
#define MAXCHILDBITS 4 ///< Max branching of BTree nodes
-#ifndef __scc__
-# define LOCAL_MEMBITS 18 // amount of memory that we keep for
-# define LOCAL_MEM ((genpaddr_t)1 << LOCAL_MEMBITS)
+#define LOCAL_MEMBITS 18 // amount of memory that we keep for
+#define LOCAL_MEM ((genpaddr_t)1 << LOCAL_MEMBITS)
// internal use in each local server
-#else
-# define LOCAL_MEMBITS 29
-# define LOCAL_MEM EXTRA_SHARED_MEM_MIN
-#endif
#include "monitor.h"
#include <notify_ipi.h>
-#ifdef __scc__
-static int glbl_chanid = 0;
-#else
static int glbl_chanid = 1;
-#endif
errval_t notification_set(int chanid, struct capref ep)
{
/* Construct the notification capability */
struct capability notify_cap = {
-#ifdef __scc__
- .type = ObjType_Notify_RCK,
-#else
.type = ObjType_Notify_IPI,
-#endif
.rights = CAPRIGHTS_READ_WRITE, // XXX
-#ifdef __scc__
- .u.notify_rck = {
-#else
.u.notify_ipi = {
-#endif
.coreid = coreid,
.chanid = chanid
}
suspend).error;
}
-#ifdef __scc__
-static inline errval_t invoke_monitor_spawn_scc_core(uint8_t id,
- genpaddr_t urpcframe_base,
- uint8_t urpcframe_bits,
- int chanid)
-{
- uint8_t invoke_bits = get_cap_valid_bits(cap_kernel);
- capaddr_t invoke_cptr = get_cap_addr(cap_kernel) >> (CPTR_BITS - invoke_bits);
-
- return syscall4((invoke_bits << 16) | (KernelCmd_Spawn_SCC_Core << 8)
- | SYSCALL_INVOKE, invoke_cptr, urpcframe_base,
- (id << 24) | (urpcframe_bits << 16) | (chanid & 0xffff)).error;
-}
-#endif
-
static inline errval_t
invoke_monitor_remote_cap_retype(capaddr_t rootcap_addr, uint8_t rootcap_vbits,
capaddr_t src, enum objtype newtype,
struct intermon_binding *intermon_binding;
errval_t err;
-#ifndef __scc__
/* Create the self endpoint as the kernel doesn't do it */
err = cap_retype(cap_selfep, cap_dispatcher, ObjType_EndPoint, 0);
if (err_is_fail(err)) {
DEBUG_ERR(err, "Retyping dispatcher to self ep failed");
return err;
}
-#endif
err = boot_arch_app_core(argc, argv, &parent_core_id, &intermon_binding);
if(err_is_fail(err)) {
intermon_init(intermon_binding, parent_core_id);
/* Request memserv and nameserv iref */
-#ifndef __scc__
err = request_mem_serv_iref(intermon_binding);
assert(err_is_ok(err));
-#endif
err = request_name_serv_iref(intermon_binding);
assert(err_is_ok(err));
assert(err_is_ok(err));
#endif // BARRELFISH_MULTIHOP_CHAN_H
-#ifndef __scc__
/* initialize self ram alloc */
err = mon_ram_alloc_init(parent_core_id, intermon_binding);
if (err_is_fail(err)) {
return err_push(err, LIB_ERR_RAM_ALLOC_SET);
}
-#endif
/* with memory alloc running, take part in cap ops */
DEBUG_CAPOPS("sending capops_ready to %"PRIuCOREID"\n", parent_core_id);
#endif
// Spawn local spawnd
-#ifdef __scc__
- err = spawn_domain("spawnd");
-#else
err = spawn_spawnd(intermon_binding);
-#endif
if (err_is_fail(err)) {
USER_PANIC_ERR(err, "error spawning spawnd");
}
errval_t mon_ram_alloc_init(coreid_t core_id, struct intermon_binding *b)
{
-#ifdef __scc__
- assert(!"Should not be calling this on SCC platform");
-#endif
-
errval_t err;
/* Set memcore_id */
errval_t err;
vregion_flags_t vspace_fl;
- #ifdef __scc__
- vspace_fl = VREGION_FLAGS_READ_WRITE_MPB;
- #else
vspace_fl = VREGION_FLAGS_READ_WRITE;
- #endif
// Map the frame in local memory
void *pool;
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